1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
15 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
16 field bits<8> SI = si;
17 field bits<8> VI = vi;
19 field bits<9> SI3 = {0, si{7-0}};
20 field bits<10> VI3 = {0, 0, vi{7-0}};
23 class vop1 <bits<8> si, bits<8> vi = si> : vop {
24 field bits<8> SI = si;
25 field bits<8> VI = vi;
27 field bits<9> SI3 = {1, 1, si{6-0}};
28 field bits<10> VI3 = !add(0x140, vi);
31 class vop2 <bits<6> si, bits<6> vi = si> : vop {
32 field bits<6> SI = si;
33 field bits<6> VI = vi;
35 field bits<9> SI3 = {1, 0, 0, si{5-0}};
36 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
39 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
40 // that doesn't have VOP2 encoding on VI
41 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
45 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
50 class sop1 <bits<8> si, bits<8> vi = si> {
51 field bits<8> SI = si;
52 field bits<8> VI = vi;
55 class sop2 <bits<7> si, bits<7> vi = si> {
56 field bits<7> SI = si;
57 field bits<7> VI = vi;
60 class sopk <bits<5> si, bits<5> vi = si> {
61 field bits<5> SI = si;
62 field bits<5> VI = vi;
65 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
66 // in AMDGPUInstrInfo.cpp
73 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
77 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
78 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
79 [SDNPMayLoad, SDNPMemOperand]
82 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
84 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
85 SDTCisVT<1, iAny>, // vdata(VGPR)
86 SDTCisVT<2, i32>, // num_channels(imm)
87 SDTCisVT<3, i32>, // vaddr(VGPR)
88 SDTCisVT<4, i32>, // soffset(SGPR)
89 SDTCisVT<5, i32>, // inst_offset(imm)
90 SDTCisVT<6, i32>, // dfmt(imm)
91 SDTCisVT<7, i32>, // nfmt(imm)
92 SDTCisVT<8, i32>, // offen(imm)
93 SDTCisVT<9, i32>, // idxen(imm)
94 SDTCisVT<10, i32>, // glc(imm)
95 SDTCisVT<11, i32>, // slc(imm)
96 SDTCisVT<12, i32> // tfe(imm)
98 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
101 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
102 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
106 class SDSample<string opcode> : SDNode <opcode,
107 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
108 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
111 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
112 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
113 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
114 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
116 def SIconstdata_ptr : SDNode<
117 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
120 // Transformation function, extract the lower 32bit of a 64bit immediate
121 def LO32 : SDNodeXForm<imm, [{
122 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
125 def LO32f : SDNodeXForm<fpimm, [{
126 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
127 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
130 // Transformation function, extract the upper 32bit of a 64bit immediate
131 def HI32 : SDNodeXForm<imm, [{
132 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
135 def HI32f : SDNodeXForm<fpimm, [{
136 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
137 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
140 def IMM8bitDWORD : PatLeaf <(imm),
141 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
144 def as_dword_i32imm : SDNodeXForm<imm, [{
145 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
148 def as_i1imm : SDNodeXForm<imm, [{
149 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
152 def as_i8imm : SDNodeXForm<imm, [{
153 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
156 def as_i16imm : SDNodeXForm<imm, [{
157 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
160 def as_i32imm: SDNodeXForm<imm, [{
161 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
164 def as_i64imm: SDNodeXForm<imm, [{
165 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
168 // Copied from the AArch64 backend:
169 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
170 return CurDAG->getTargetConstant(
171 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
174 // Copied from the AArch64 backend:
175 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
176 return CurDAG->getTargetConstant(
177 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
180 def IMM8bit : PatLeaf <(imm),
181 [{return isUInt<8>(N->getZExtValue());}]
184 def IMM12bit : PatLeaf <(imm),
185 [{return isUInt<12>(N->getZExtValue());}]
188 def IMM16bit : PatLeaf <(imm),
189 [{return isUInt<16>(N->getZExtValue());}]
192 def IMM20bit : PatLeaf <(imm),
193 [{return isUInt<20>(N->getZExtValue());}]
196 def IMM32bit : PatLeaf <(imm),
197 [{return isUInt<32>(N->getZExtValue());}]
200 def mubuf_vaddr_offset : PatFrag<
201 (ops node:$ptr, node:$offset, node:$imm_offset),
202 (add (add node:$ptr, node:$offset), node:$imm_offset)
205 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
206 return isInlineImmediate(N);
209 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
210 return isInlineImmediate(N);
213 class SGPRImm <dag frag> : PatLeaf<frag, [{
214 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
215 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
218 const SIRegisterInfo *SIRI =
219 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
220 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
222 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
229 //===----------------------------------------------------------------------===//
231 //===----------------------------------------------------------------------===//
233 def FRAMEri32 : Operand<iPTR> {
234 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
237 def sopp_brtarget : Operand<OtherVT> {
238 let EncoderMethod = "getSOPPBrEncoding";
239 let OperandType = "OPERAND_PCREL";
242 include "SIInstrFormats.td"
243 include "VIInstrFormats.td"
245 let OperandType = "OPERAND_IMMEDIATE" in {
247 def offen : Operand<i1> {
248 let PrintMethod = "printOffen";
250 def idxen : Operand<i1> {
251 let PrintMethod = "printIdxen";
253 def addr64 : Operand<i1> {
254 let PrintMethod = "printAddr64";
256 def mbuf_offset : Operand<i16> {
257 let PrintMethod = "printMBUFOffset";
259 def ds_offset : Operand<i16> {
260 let PrintMethod = "printDSOffset";
262 def ds_offset0 : Operand<i8> {
263 let PrintMethod = "printDSOffset0";
265 def ds_offset1 : Operand<i8> {
266 let PrintMethod = "printDSOffset1";
268 def glc : Operand <i1> {
269 let PrintMethod = "printGLC";
271 def slc : Operand <i1> {
272 let PrintMethod = "printSLC";
274 def tfe : Operand <i1> {
275 let PrintMethod = "printTFE";
278 def omod : Operand <i32> {
279 let PrintMethod = "printOModSI";
282 def ClampMod : Operand <i1> {
283 let PrintMethod = "printClampSI";
286 } // End OperandType = "OPERAND_IMMEDIATE"
288 //===----------------------------------------------------------------------===//
290 //===----------------------------------------------------------------------===//
292 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
293 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
295 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
296 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
297 def MUBUFAddr64Atomic : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
298 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
299 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
300 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
302 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
303 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
304 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
305 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
307 //===----------------------------------------------------------------------===//
308 // SI assembler operands
309 //===----------------------------------------------------------------------===//
329 //===----------------------------------------------------------------------===//
331 // SI Instruction multiclass helpers.
333 // Instructions with _32 take 32-bit operands.
334 // Instructions with _64 take 64-bit operands.
336 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
337 // encoding is the standard encoding, but instruction that make use of
338 // any of the instruction modifiers must use the 64-bit encoding.
340 // Instructions with _e32 use the 32-bit encoding.
341 // Instructions with _e64 use the 64-bit encoding.
343 //===----------------------------------------------------------------------===//
345 class SIMCInstr <string pseudo, int subtarget> {
346 string PseudoInstr = pseudo;
347 int Subtarget = subtarget;
350 //===----------------------------------------------------------------------===//
352 //===----------------------------------------------------------------------===//
354 class EXPCommon : InstSI<
356 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
357 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
358 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
367 let isPseudo = 1 in {
368 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
371 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
373 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
376 //===----------------------------------------------------------------------===//
378 //===----------------------------------------------------------------------===//
380 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
381 SOP1 <outs, ins, "", pattern>,
382 SIMCInstr<opName, SISubtarget.NONE> {
386 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm,
388 SOP1 <outs, ins, asm, pattern>,
390 SIMCInstr<opName, SISubtarget.SI>;
392 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm,
394 SOP1 <outs, ins, asm, pattern>,
396 SIMCInstr<opName, SISubtarget.VI>;
398 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> {
399 def "" : SOP1_Pseudo <opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
402 def _si : SOP1_Real_si <op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
403 opName#" $dst, $src0", pattern>;
405 def _vi : SOP1_Real_vi <op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
406 opName#" $dst, $src0", pattern>;
409 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> {
410 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
413 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
414 opName#" $dst, $src0", pattern>;
416 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
417 opName#" $dst, $src0", pattern>;
420 // no input, 64-bit output.
421 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
422 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
424 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
425 opName#" $dst", pattern> {
429 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
430 opName#" $dst", pattern> {
435 // 64-bit input, 32-bit output.
436 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> {
437 def "" : SOP1_Pseudo <opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
440 def _si : SOP1_Real_si <op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
441 opName#" $dst, $src0", pattern>;
443 def _vi : SOP1_Real_vi <op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
444 opName#" $dst, $src0", pattern>;
447 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
448 SOP2<outs, ins, "", pattern>,
449 SIMCInstr<opName, SISubtarget.NONE> {
454 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm,
456 SOP2<outs, ins, asm, pattern>,
458 SIMCInstr<opName, SISubtarget.SI>;
460 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm,
462 SOP2<outs, ins, asm, pattern>,
464 SIMCInstr<opName, SISubtarget.VI>;
466 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
467 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
468 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
470 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
471 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
472 opName#" $dst, $src0, $src1 [$scc]", pattern>;
474 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
475 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
476 opName#" $dst, $src0, $src1 [$scc]", pattern>;
479 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> {
480 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
481 (ins SSrc_32:$src0, SSrc_32:$src1), pattern>;
483 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
484 (ins SSrc_32:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1", pattern>;
486 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
487 (ins SSrc_32:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1", pattern>;
490 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> {
491 def "" : SOP2_Pseudo <opName, (outs SReg_64:$dst),
492 (ins SSrc_64:$src0, SSrc_64:$src1), pattern>;
494 def _si : SOP2_Real_si <op, opName, (outs SReg_64:$dst),
495 (ins SSrc_64:$src0, SSrc_64:$src1), opName#" $dst, $src0, $src1", pattern>;
497 def _vi : SOP2_Real_vi <op, opName, (outs SReg_64:$dst),
498 (ins SSrc_64:$src0, SSrc_64:$src1), opName#" $dst, $src0, $src1", pattern>;
501 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> {
502 def "" : SOP2_Pseudo <opName, (outs SReg_64:$dst),
503 (ins SSrc_64:$src0, SSrc_32:$src1), pattern>;
505 def _si : SOP2_Real_si <op, opName, (outs SReg_64:$dst),
506 (ins SSrc_64:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1", pattern>;
508 def _vi : SOP2_Real_vi <op, opName, (outs SReg_64:$dst),
509 (ins SSrc_64:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1", pattern>;
513 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
514 string opName, PatLeaf cond> : SOPC <
515 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
516 opName#" $dst, $src0, $src1", []>;
518 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
519 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
521 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
522 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
524 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
525 SOPK <outs, ins, "", pattern>,
526 SIMCInstr<opName, SISubtarget.NONE> {
530 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm,
532 SOPK <outs, ins, asm, pattern>,
534 SIMCInstr<opName, SISubtarget.SI>;
536 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm,
538 SOPK <outs, ins, asm, pattern>,
540 SIMCInstr<opName, SISubtarget.VI>;
542 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
543 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
546 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
547 opName#" $dst, $src0", pattern>;
549 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
550 opName#" $dst, $src0", pattern>;
553 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
554 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
555 (ins SReg_32:$src0, u16imm:$src1), pattern>;
557 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
558 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0", pattern>;
560 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
561 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0", pattern>;
564 //===----------------------------------------------------------------------===//
566 //===----------------------------------------------------------------------===//
568 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
569 SMRD <outs, ins, "", pattern>,
570 SIMCInstr<opName, SISubtarget.NONE> {
574 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
576 SMRD <outs, ins, asm, []>,
578 SIMCInstr<opName, SISubtarget.SI>;
580 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
582 SMRD <outs, ins, asm, []>,
584 SIMCInstr<opName, SISubtarget.VI>;
586 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
587 string asm, list<dag> pattern> {
589 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
591 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
593 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
596 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
597 RegisterClass dstClass> {
599 op, opName#"_IMM", 1, (outs dstClass:$dst),
600 (ins baseClass:$sbase, u32imm:$offset),
601 opName#" $dst, $sbase, $offset", []
604 defm _SGPR : SMRD_m <
605 op, opName#"_SGPR", 0, (outs dstClass:$dst),
606 (ins baseClass:$sbase, SReg_32:$soff),
607 opName#" $dst, $sbase, $soff", []
611 //===----------------------------------------------------------------------===//
612 // Vector ALU classes
613 //===----------------------------------------------------------------------===//
615 // This must always be right before the operand being input modified.
616 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
617 let PrintMethod = "printOperandAndMods";
619 def InputModsNoDefault : Operand <i32> {
620 let PrintMethod = "printOperandAndMods";
623 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
625 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
626 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
630 // Returns the register class to use for the destination of VOP[123C]
631 // instructions for the given VT.
632 class getVALUDstForVT<ValueType VT> {
633 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32,
634 !if(!eq(VT.Size, 64), VReg_64,
635 SReg_64)); // else VT == i1
638 // Returns the register class to use for source 0 of VOP[12C]
639 // instructions for the given VT.
640 class getVOPSrc0ForVT<ValueType VT> {
641 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
644 // Returns the register class to use for source 1 of VOP[12C] for the
646 class getVOPSrc1ForVT<ValueType VT> {
647 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
650 // Returns the register classes for the source arguments of a VOP[12C]
651 // instruction for the given SrcVTs.
652 class getInRC32 <list<ValueType> SrcVT> {
653 list<DAGOperand> ret = [
654 getVOPSrc0ForVT<SrcVT[0]>.ret,
655 getVOPSrc1ForVT<SrcVT[1]>.ret
659 // Returns the register class to use for sources of VOP3 instructions for the
661 class getVOP3SrcForVT<ValueType VT> {
662 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
665 // Returns the register classes for the source arguments of a VOP3
666 // instruction for the given SrcVTs.
667 class getInRC64 <list<ValueType> SrcVT> {
668 list<DAGOperand> ret = [
669 getVOP3SrcForVT<SrcVT[0]>.ret,
670 getVOP3SrcForVT<SrcVT[1]>.ret,
671 getVOP3SrcForVT<SrcVT[2]>.ret
675 // Returns 1 if the source arguments have modifiers, 0 if they do not.
676 class hasModifiers<ValueType SrcVT> {
677 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
678 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
681 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
682 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
683 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
684 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
688 // Returns the input arguments for VOP3 instructions for the given SrcVT.
689 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
690 RegisterOperand Src2RC, int NumSrcArgs,
694 !if (!eq(NumSrcArgs, 1),
695 !if (!eq(HasModifiers, 1),
696 // VOP1 with modifiers
697 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
698 ClampMod:$clamp, omod:$omod)
700 // VOP1 without modifiers
703 !if (!eq(NumSrcArgs, 2),
704 !if (!eq(HasModifiers, 1),
705 // VOP 2 with modifiers
706 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
707 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
708 ClampMod:$clamp, omod:$omod)
710 // VOP2 without modifiers
711 (ins Src0RC:$src0, Src1RC:$src1)
713 /* NumSrcArgs == 3 */,
714 !if (!eq(HasModifiers, 1),
715 // VOP3 with modifiers
716 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
717 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
718 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
719 ClampMod:$clamp, omod:$omod)
721 // VOP3 without modifiers
722 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
726 // Returns the assembly string for the inputs and outputs of a VOP[12C]
727 // instruction. This does not add the _e32 suffix, so it can be reused
729 class getAsm32 <int NumSrcArgs> {
730 string src1 = ", $src1";
731 string src2 = ", $src2";
732 string ret = " $dst, $src0"#
733 !if(!eq(NumSrcArgs, 1), "", src1)#
734 !if(!eq(NumSrcArgs, 3), src2, "");
737 // Returns the assembly string for the inputs and outputs of a VOP3
739 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
740 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
741 string src1 = !if(!eq(NumSrcArgs, 1), "",
742 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
743 " $src1_modifiers,"));
744 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
746 !if(!eq(HasModifiers, 0),
747 getAsm32<NumSrcArgs>.ret,
748 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
752 class VOPProfile <list<ValueType> _ArgVT> {
754 field list<ValueType> ArgVT = _ArgVT;
756 field ValueType DstVT = ArgVT[0];
757 field ValueType Src0VT = ArgVT[1];
758 field ValueType Src1VT = ArgVT[2];
759 field ValueType Src2VT = ArgVT[3];
760 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
761 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
762 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
763 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
764 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
765 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
767 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
768 field bit HasModifiers = hasModifiers<Src0VT>.ret;
770 field dag Outs = (outs DstRC:$dst);
772 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
773 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
776 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
777 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
780 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
781 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
782 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
783 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
784 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
785 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
786 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
787 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
788 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
790 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
791 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
792 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
793 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
794 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
795 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
796 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
797 let Src0RC32 = VCSrc_32;
800 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
801 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
802 let Asm64 = " $dst, $src0_modifiers, $src1";
805 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
806 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
807 let Asm64 = " $dst, $src0_modifiers, $src1";
810 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
811 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
813 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
814 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
815 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
816 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
819 class VOP <string opName> {
820 string OpName = opName;
823 class VOP2_REV <string revOp, bit isOrig> {
824 string RevOp = revOp;
828 class AtomicNoRet <string noRetOp, bit isRet> {
829 string NoRetOp = noRetOp;
833 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
834 VOP1Common <outs, ins, "", pattern>,
836 SIMCInstr <opName#"_e32", SISubtarget.NONE> {
840 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
842 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
844 def _si : VOP1<op.SI, outs, ins, asm, []>,
845 SIMCInstr <opName#"_e32", SISubtarget.SI>;
846 def _vi : VOP1<op.VI, outs, ins, asm, []>,
847 SIMCInstr <opName#"_e32", SISubtarget.VI>;
850 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
851 VOP2Common <outs, ins, "", pattern>,
853 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
857 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
858 string opName, string revOpSI> {
859 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
860 VOP2_REV<revOpSI#"_e32", !eq(revOpSI, opName)>;
862 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
863 VOP2_REV<revOpSI#"_e32_si", !eq(revOpSI, opName)>,
864 SIMCInstr <opName#"_e32", SISubtarget.SI>;
867 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
868 string opName, string revOpSI, string revOpVI> {
869 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
870 VOP2_REV<revOpSI#"_e32", !eq(revOpSI, opName)>;
872 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
873 VOP2_REV<revOpSI#"_e32_si", !eq(revOpSI, opName)>,
874 SIMCInstr <opName#"_e32", SISubtarget.SI>;
875 def _vi : VOP2 <op.VI, outs, ins, opName#asm, []>,
876 VOP2_REV<revOpVI#"_e32_vi", !eq(revOpVI, opName)>,
877 SIMCInstr <opName#"_e32", SISubtarget.VI>;
880 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
882 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
883 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
884 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
885 bits<2> omod = !if(HasModifiers, ?, 0);
886 bits<1> clamp = !if(HasModifiers, ?, 0);
887 bits<9> src1 = !if(HasSrc1, ?, 0);
888 bits<9> src2 = !if(HasSrc2, ?, 0);
891 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
892 VOP3Common <outs, ins, "", pattern>,
894 SIMCInstr<opName#"_e64", SISubtarget.NONE> {
898 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
899 VOP3Common <outs, ins, asm, []>,
901 SIMCInstr<opName#"_e64", SISubtarget.SI>;
903 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
904 VOP3Common <outs, ins, asm, []>,
906 SIMCInstr <opName#"_e64", SISubtarget.VI>;
908 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
909 string opName, int NumSrcArgs, bit HasMods = 1> {
911 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
913 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
914 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
915 !if(!eq(NumSrcArgs, 2), 0, 1),
917 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
918 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
919 !if(!eq(NumSrcArgs, 2), 0, 1),
923 // VOP3_m without source modifiers
924 multiclass VOP3_m_nosrcmod <vop op, dag outs, dag ins, string asm, list<dag> pattern,
925 string opName, int NumSrcArgs, bit HasMods = 1> {
927 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
929 let src0_modifiers = 0,
931 src2_modifiers = 0 in {
932 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
933 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
937 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
938 list<dag> pattern, string opName, bit HasMods = 1> {
940 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
942 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
943 VOP3DisableFields<0, 0, HasMods>;
945 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
946 VOP3DisableFields<0, 0, HasMods>;
949 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
950 list<dag> pattern, string opName, string revOpSI, string revOpVI,
951 bit HasMods = 1, bit UseFullOp = 0> {
953 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
954 VOP2_REV<revOpSI#"_e64", !eq(revOpSI, opName)>;
956 def _si : VOP3_Real_si <op.SI3,
957 outs, ins, asm, opName>,
958 VOP2_REV<revOpSI#"_e64_si", !eq(revOpSI, opName)>,
959 VOP3DisableFields<1, 0, HasMods>;
961 def _vi : VOP3_Real_vi <op.VI3,
962 outs, ins, asm, opName>,
963 VOP2_REV<revOpVI#"_e64_vi", !eq(revOpVI, opName)>,
964 VOP3DisableFields<1, 0, HasMods>;
967 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
968 list<dag> pattern, string opName, string revOp,
969 bit HasMods = 1, bit UseFullOp = 0> {
970 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
971 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
973 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
974 // can write it into any SGPR. We currently don't use the carry out,
975 // so for now hardcode it to VCC as well.
976 let sdst = SIOperand.VCC, Defs = [VCC] in {
977 def _si : VOP3b <op.SI3, outs, ins, asm, pattern>,
978 VOP3DisableFields<1, 0, HasMods>,
979 SIMCInstr<opName#"_e64", SISubtarget.SI>,
980 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
982 // TODO: Do we need this VI variant here?
983 /*def _vi : VOP3b_vi <op.VI3, outs, ins, asm, pattern>,
984 VOP3DisableFields<1, 0, HasMods>,
985 SIMCInstr<opName#"_e64", SISubtarget.VI>,
986 VOP2_REV<revOp#"_e64_vi", !eq(revOp, opName)>;*/
987 } // End sdst = SIOperand.VCC, Defs = [VCC]
990 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
991 list<dag> pattern, string opName,
992 bit HasMods, bit defExec> {
994 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
996 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
997 VOP3DisableFields<1, 0, HasMods> {
998 let Defs = !if(defExec, [EXEC], []);
1001 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1002 VOP3DisableFields<1, 0, HasMods> {
1003 let Defs = !if(defExec, [EXEC], []);
1007 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1008 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1009 string asm, list<dag> pattern = []> {
1010 let isPseudo = 1 in {
1011 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1012 SIMCInstr<opName, SISubtarget.NONE>;
1015 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1016 SIMCInstr <opName, SISubtarget.SI>;
1018 def _vi : VOP3Common <outs, ins, asm, []>,
1020 VOP3DisableFields <1, 0, 0>,
1021 SIMCInstr <opName, SISubtarget.VI>;
1024 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1025 dag ins32, string asm32, list<dag> pat32,
1026 dag ins64, string asm64, list<dag> pat64,
1029 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1031 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
1034 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1035 SDPatternOperator node = null_frag> : VOP1_Helper <
1037 P.Ins32, P.Asm32, [],
1040 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1041 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1042 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1046 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1047 SDPatternOperator node = null_frag> {
1049 def _e32 : VOP1 <op.SI, P.Outs, P.Ins32, opName#P.Asm32, []>,
1052 def _e64 : VOP3Common <P.Outs, P.Ins64, opName#P.Asm64,
1054 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1055 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1056 [(set P.DstVT:$dst, (node P.Src0VT:$src0))])>,
1059 VOP3DisableFields<0, 0, P.HasModifiers>;
1062 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1063 dag ins32, string asm32, list<dag> pat32,
1064 dag ins64, string asm64, list<dag> pat64,
1065 string revOpSI, string revOpVI, bit HasMods> {
1066 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOpSI, revOpVI>;
1068 defm _e64 : VOP3_2_m <op,
1069 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOpSI, revOpVI, HasMods
1073 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1074 SDPatternOperator node = null_frag,
1075 string revOpSI = opName, string revOpVI = revOpSI> : VOP2_Helper <
1077 P.Ins32, P.Asm32, [],
1081 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1082 i1:$clamp, i32:$omod)),
1083 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1084 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1085 revOpSI, revOpVI, P.HasModifiers
1088 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1089 dag ins32, string asm32, list<dag> pat32,
1090 dag ins64, string asm64, list<dag> pat64,
1091 string revOp, bit HasMods> {
1093 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp, revOp>;
1095 defm _e64 : VOP3b_2_m <op,
1096 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1100 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1101 SDPatternOperator node = null_frag,
1102 string revOp = opName> : VOP2b_Helper <
1104 P.Ins32, P.Asm32, [],
1108 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1109 i1:$clamp, i32:$omod)),
1110 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1111 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1112 revOp, P.HasModifiers
1115 // A VOP2 instruction that is VOP3-only on VI.
1116 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1117 dag ins32, string asm32, list<dag> pat32,
1118 dag ins64, string asm64, list<dag> pat64,
1119 string revOpSI, string revOpVI, bit HasMods> {
1120 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOpSI>;
1122 defm _e64 : VOP3_2_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName,
1123 revOpSI, revOpVI, HasMods>;
1126 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1127 SDPatternOperator node = null_frag,
1128 string revOpSI = opName, string revOpVI = revOpSI>
1131 P.Ins32, P.Asm32, [],
1135 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1136 i1:$clamp, i32:$omod)),
1137 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1138 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1139 revOpSI, revOpVI, P.HasModifiers
1142 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1143 VOPCCommon <ins, "", pattern>,
1145 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1149 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1150 string opName, bit DefExec> {
1151 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1153 def _si : VOPC<op.SI, ins, asm, []>,
1154 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1155 let Defs = !if(DefExec, [EXEC], []);
1158 def _vi : VOPC<op.VI, ins, asm, []>,
1159 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1160 let Defs = !if(DefExec, [EXEC], []);
1164 multiclass VOPC_Helper <vopc op, string opName,
1165 dag ins32, string asm32, list<dag> pat32,
1166 dag out64, dag ins64, string asm64, list<dag> pat64,
1167 bit HasMods, bit DefExec> {
1168 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1170 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1171 opName, HasMods, DefExec>;
1174 multiclass VOPCInst <vopc op, string opName,
1175 VOPProfile P, PatLeaf cond = COND_NULL,
1176 bit DefExec = 0> : VOPC_Helper <
1178 P.Ins32, P.Asm32, [],
1179 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1182 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1183 i1:$clamp, i32:$omod)),
1184 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1186 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1187 P.HasModifiers, DefExec
1190 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1191 bit DefExec = 0> : VOPC_Helper <
1193 P.Ins32, P.Asm32, [],
1194 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1197 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1198 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1199 P.HasModifiers, DefExec
1203 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1204 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
1206 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1207 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
1209 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1210 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
1212 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1213 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
1216 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1217 PatLeaf cond = COND_NULL>
1218 : VOPCInst <op, opName, P, cond, 1>;
1220 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1221 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
1223 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1224 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
1226 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1227 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
1229 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1230 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
1232 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1233 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1234 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
1237 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1238 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1240 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1241 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1243 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1244 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1246 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1247 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1249 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1250 SDPatternOperator node = null_frag> : VOP3_Helper <
1251 op, opName, P.Outs, P.Ins64, P.Asm64,
1252 !if(!eq(P.NumSrcArgs, 3),
1255 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1256 i1:$clamp, i32:$omod)),
1257 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1258 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1259 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1261 !if(!eq(P.NumSrcArgs, 2),
1264 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1265 i1:$clamp, i32:$omod)),
1266 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1267 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1268 /* P.NumSrcArgs == 1 */,
1271 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1272 i1:$clamp, i32:$omod))))],
1273 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1274 P.NumSrcArgs, P.HasModifiers
1277 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1278 string opName, list<dag> pattern> :
1280 op, (outs vrc:$vdst, SReg_64:$sdst),
1281 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1282 InputModsNoDefault:$src1_modifiers, arc:$src1,
1283 InputModsNoDefault:$src2_modifiers, arc:$src2,
1284 ClampMod:$clamp, omod:$omod),
1285 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1286 opName, opName, 1, 1
1289 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1290 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1292 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1293 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1296 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1297 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1298 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1299 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1300 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1301 i32:$src1_modifiers, P.Src1VT:$src1,
1302 i32:$src2_modifiers, P.Src2VT:$src2,
1306 //===----------------------------------------------------------------------===//
1307 // Interpolation opcodes
1308 //===----------------------------------------------------------------------===//
1310 class VINTRP_Pseudo <string opName, dag outs, dag ins, string asm,
1311 list<dag> pattern> :
1312 VINTRPCommon <outs, ins, asm, pattern>,
1313 SIMCInstr<opName, SISubtarget.NONE> {
1317 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1318 string asm, list<dag> pattern> :
1319 VINTRPCommon <outs, ins, asm, pattern>,
1321 SIMCInstr<opName, SISubtarget.SI>;
1323 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1324 string asm, list<dag> pattern> :
1325 VINTRPCommon <outs, ins, asm, pattern>,
1327 SIMCInstr<opName, SISubtarget.VI>;
1329 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1330 string disableEncoding = "", string constraints = "",
1331 list<dag> pattern = []> {
1332 let DisableEncoding = disableEncoding,
1333 Constraints = constraints in {
1334 def "" : VINTRP_Pseudo <opName, outs, ins, asm, pattern>;
1336 def _si : VINTRP_Real_si <op, opName, outs, ins, asm, pattern>;
1338 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm, pattern>;
1342 //===----------------------------------------------------------------------===//
1343 // Vector I/O classes
1344 //===----------------------------------------------------------------------===//
1346 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1347 DS <outs, ins, "", pattern>,
1348 SIMCInstr <opName, SISubtarget.NONE> {
1352 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1353 DS <outs, ins, asm, []>,
1355 SIMCInstr <opName, SISubtarget.SI>;
1357 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1358 DS <outs, ins, asm, []>,
1360 SIMCInstr <opName, SISubtarget.VI>;
1362 class DS_1A_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1363 DS <outs, ins, asm, []>,
1365 SIMCInstr <opName, SISubtarget.SI> {
1367 // Single load interpret the 2 i8imm operands as a single i16 offset.
1369 let offset0 = offset{7-0};
1370 let offset1 = offset{15-8};
1373 class DS_1A_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1374 DS <outs, ins, asm, []>,
1376 SIMCInstr <opName, SISubtarget.VI> {
1378 // Single load interpret the 2 i8imm operands as a single i16 offset.
1380 let offset0 = offset{7-0};
1381 let offset1 = offset{15-8};
1384 multiclass DS_1A_Load_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1386 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1387 def "" : DS_Pseudo <opName, outs, ins, pat>;
1389 let data0 = 0, data1 = 0 in {
1390 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1391 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1396 multiclass DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass>
1400 (outs regClass:$vdst),
1401 (ins i1imm:$gds, VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
1402 asm#" $vdst, $addr"#"$offset"#" [M0]",
1405 multiclass DS_Load2_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1407 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1408 def "" : DS_Pseudo <opName, outs, ins, pat>;
1410 let data0 = 0, data1 = 0 in {
1411 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1412 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1417 multiclass DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass>
1421 (outs regClass:$vdst),
1422 (ins i1imm:$gds, VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1424 asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]",
1427 multiclass DS_1A_Store_m <bits<8> op, string opName, dag outs, dag ins,
1428 string asm, list<dag> pat> {
1429 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1430 def "" : DS_Pseudo <opName, outs, ins, pat>;
1432 let data1 = 0, vdst = 0 in {
1433 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1434 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1439 multiclass DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass>
1444 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, ds_offset:$offset, M0Reg:$m0),
1445 asm#" $addr, $data0"#"$offset"#" [M0]",
1448 multiclass DS_Store_m <bits<8> op, string opName, dag outs, dag ins,
1449 string asm, list<dag> pat> {
1450 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1451 def "" : DS_Pseudo <opName, outs, ins, pat>;
1454 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1455 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1460 multiclass DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass>
1465 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, regClass:$data1,
1466 ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0),
1467 asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]",
1470 class DS_1A_si <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
1471 DS_si <op, outs, ins, asm, pat> {
1474 // Single load interpret the 2 i8imm operands as a single i16 offset.
1475 let offset0 = offset{7-0};
1476 let offset1 = offset{15-8};
1478 let hasSideEffects = 0;
1481 // 1 address, 1 data.
1482 class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A_si <
1485 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1486 asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", []>,
1487 AtomicNoRet<noRetOp, 1> {
1493 let hasPostISelHook = 1; // Adjusted to no return version.
1496 // 1 address, 2 data.
1497 class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A_si <
1500 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1501 asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]",
1503 AtomicNoRet<noRetOp, 1> {
1506 let hasPostISelHook = 1; // Adjusted to no return version.
1509 // 1 address, 2 data.
1510 class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A_si <
1513 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1514 asm#" $addr, $data0, $data1"#"$offset"#" [M0]",
1516 AtomicNoRet<noRetOp, 0> {
1521 // 1 address, 1 data.
1522 class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A_si <
1525 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1526 asm#" $addr, $data0"#"$offset"#" [M0]",
1528 AtomicNoRet<noRetOp, 0> {
1535 //===----------------------------------------------------------------------===//
1537 //===----------------------------------------------------------------------===//
1539 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1540 MTBUF <outs, ins, "", pattern>,
1541 SIMCInstr<opName, SISubtarget.NONE> {
1545 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1547 MTBUF <outs, ins, asm, []>,
1549 SIMCInstr<opName, SISubtarget.SI>;
1551 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1552 MTBUF <outs, ins, asm, []>,
1554 SIMCInstr <opName, SISubtarget.VI>;
1556 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1557 list<dag> pattern> {
1559 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1561 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1563 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1567 let mayStore = 1, mayLoad = 0 in {
1569 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1570 RegisterClass regClass> : MTBUF_m <
1572 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1573 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
1574 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1575 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1576 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1579 } // mayStore = 1, mayLoad = 0
1581 let mayLoad = 1, mayStore = 0 in {
1583 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1584 RegisterClass regClass> : MTBUF_m <
1585 op, opName, (outs regClass:$dst),
1586 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1587 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
1588 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1589 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1590 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1593 } // mayLoad = 1, mayStore = 0
1595 //===----------------------------------------------------------------------===//
1597 //===----------------------------------------------------------------------===//
1599 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1600 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1604 class MUBUF_vi <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1605 MUBUF <outs, ins, asm, pattern>, MUBUFe_vi <op> {
1609 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1611 bit IsAddr64 = is_addr64;
1612 string OpName = NAME # suffix;
1615 class MUBUFAtomicAddr64 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1616 : MUBUF_si <op, outs, ins, asm, pattern> {
1626 class MUBUFAtomicOffset <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1627 : MUBUF_si <op, outs, ins, asm, pattern> {
1637 multiclass MUBUF_Atomic <bits<7> op, string name, RegisterClass rc,
1638 ValueType vt, SDPatternOperator atomic> {
1640 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1642 // No return variants
1645 def _ADDR64 : MUBUFAtomicAddr64 <
1647 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1648 mbuf_offset:$offset, slc:$slc),
1649 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#"$slc", []
1650 >, MUBUFAddr64Table<1>, AtomicNoRet<NAME#"_ADDR64", 0>;
1652 def _OFFSET : MUBUFAtomicOffset <
1654 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1655 SCSrc_32:$soffset, slc:$slc),
1656 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", []
1657 >, MUBUFAddr64Table<0>, AtomicNoRet<NAME#"_OFFSET", 0>;
1660 // Variant that return values
1661 let glc = 1, Constraints = "$vdata = $vdata_in",
1662 DisableEncoding = "$vdata_in" in {
1664 def _RTN_ADDR64 : MUBUFAtomicAddr64 <
1665 op, (outs rc:$vdata),
1666 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1667 mbuf_offset:$offset, slc:$slc),
1668 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#" glc"#"$slc",
1670 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i16:$offset,
1671 i1:$slc), vt:$vdata_in))]
1672 >, MUBUFAddr64Table<1, "_RTN">, AtomicNoRet<NAME#"_ADDR64", 1>;
1674 def _RTN_OFFSET : MUBUFAtomicOffset <
1675 op, (outs rc:$vdata),
1676 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1677 SCSrc_32:$soffset, slc:$slc),
1678 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1680 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1681 i1:$slc), vt:$vdata_in))]
1682 >, MUBUFAddr64Table<0, "_RTN">, AtomicNoRet<NAME#"_OFFSET", 1>;
1686 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1689 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
1690 ValueType load_vt = i32,
1691 SDPatternOperator ld = null_frag> {
1693 let mayLoad = 1, mayStore = 0 in {
1697 let offen = 0, idxen = 0, vaddr = 0 in {
1698 def _OFFSET : MUBUF_si <op, (outs regClass:$vdata),
1699 (ins SReg_128:$srsrc,
1700 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1701 slc:$slc, tfe:$tfe),
1702 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1703 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1704 i32:$soffset, i16:$offset,
1705 i1:$glc, i1:$slc, i1:$tfe)))]>,
1706 MUBUFAddr64Table<0>;
1709 let offen = 1, idxen = 0 in {
1710 def _OFFEN : MUBUF_si <op, (outs regClass:$vdata),
1711 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1712 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1714 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1717 let offen = 0, idxen = 1 in {
1718 def _IDXEN : MUBUF_si <op, (outs regClass:$vdata),
1719 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1720 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1721 slc:$slc, tfe:$tfe),
1722 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1725 let offen = 1, idxen = 1 in {
1726 def _BOTHEN : MUBUF_si <op, (outs regClass:$vdata),
1727 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1728 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1729 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1733 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
1734 def _ADDR64 : MUBUF_si <op, (outs regClass:$vdata),
1735 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1736 asm#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1737 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1738 i64:$vaddr, i16:$offset)))]>, MUBUFAddr64Table<1>;
1743 multiclass MUBUF_Load_Helper_vi <bits<7> op, string asm, RegisterClass regClass,
1744 ValueType load_vt = i32,
1745 SDPatternOperator ld = null_frag> {
1747 let lds = 0, mayLoad = 1 in {
1748 let offen = 0, idxen = 0, vaddr = 0 in {
1749 def _OFFSET : MUBUF_vi <op, (outs regClass:$vdata),
1750 (ins SReg_128:$srsrc,
1751 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1752 slc:$slc, tfe:$tfe),
1753 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1754 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1755 i32:$soffset, i16:$offset,
1756 i1:$glc, i1:$slc, i1:$tfe)))]>,
1757 MUBUFAddr64Table<0>;
1760 let offen = 1, idxen = 0 in {
1761 def _OFFEN : MUBUF_vi <op, (outs regClass:$vdata),
1762 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1763 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1765 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1768 let offen = 0, idxen = 1 in {
1769 def _IDXEN : MUBUF_vi <op, (outs regClass:$vdata),
1770 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1771 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1772 slc:$slc, tfe:$tfe),
1773 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1776 let offen = 1, idxen = 1 in {
1777 def _BOTHEN : MUBUF_vi <op, (outs regClass:$vdata),
1778 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1779 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1780 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1785 multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
1786 ValueType store_vt, SDPatternOperator st> {
1788 let mayLoad = 0, mayStore = 1 in {
1793 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1794 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1796 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1797 "$glc"#"$slc"#"$tfe",
1801 let offen = 0, idxen = 0, vaddr = 0 in {
1802 def _OFFSET : MUBUF_si <
1804 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1805 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1806 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1807 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1808 i16:$offset, i1:$glc, i1:$slc,
1810 >, MUBUFAddr64Table<0>;
1811 } // offen = 0, idxen = 0, vaddr = 0
1813 let offen = 1, idxen = 0 in {
1814 def _OFFEN : MUBUF_si <
1816 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1817 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1818 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1819 "$glc"#"$slc"#"$tfe",
1822 } // end offen = 1, idxen = 0
1826 def _ADDR64 : MUBUF_si <
1828 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1829 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1830 [(st store_vt:$vdata,
1831 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>, MUBUFAddr64Table<1>
1844 let soffset = 128; // ZERO
1846 } // End mayLoad = 0, mayStore = 1
1849 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1850 FLAT <op, (outs regClass:$data),
1851 (ins VReg_64:$addr),
1852 asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
1859 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1860 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1861 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1873 class MIMG_Mask <string op, int channels> {
1875 int Channels = channels;
1878 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1879 RegisterClass dst_rc,
1880 RegisterClass src_rc> : MIMG <
1882 (outs dst_rc:$vdata),
1883 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1884 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1886 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1887 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1892 let hasPostISelHook = 1;
1895 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1896 RegisterClass dst_rc,
1898 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
1899 MIMG_Mask<asm#"_V1", channels>;
1900 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1901 MIMG_Mask<asm#"_V2", channels>;
1902 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1903 MIMG_Mask<asm#"_V4", channels>;
1906 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1907 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
1908 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1909 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1910 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1913 class MIMG_Sampler_Helper <bits<7> op, string asm,
1914 RegisterClass dst_rc,
1915 RegisterClass src_rc> : MIMG <
1917 (outs dst_rc:$vdata),
1918 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1919 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1920 SReg_256:$srsrc, SReg_128:$ssamp),
1921 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1922 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1926 let hasPostISelHook = 1;
1929 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1930 RegisterClass dst_rc,
1932 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32>,
1933 MIMG_Mask<asm#"_V1", channels>;
1934 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1935 MIMG_Mask<asm#"_V2", channels>;
1936 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1937 MIMG_Mask<asm#"_V4", channels>;
1938 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1939 MIMG_Mask<asm#"_V8", channels>;
1940 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1941 MIMG_Mask<asm#"_V16", channels>;
1944 multiclass MIMG_Sampler <bits<7> op, string asm> {
1945 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1>;
1946 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1947 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1948 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1951 class MIMG_Gather_Helper <bits<7> op, string asm,
1952 RegisterClass dst_rc,
1953 RegisterClass src_rc> : MIMG <
1955 (outs dst_rc:$vdata),
1956 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1957 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1958 SReg_256:$srsrc, SReg_128:$ssamp),
1959 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1960 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1965 // DMASK was repurposed for GATHER4. 4 components are always
1966 // returned and DMASK works like a swizzle - it selects
1967 // the component to fetch. The only useful DMASK values are
1968 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1969 // (red,red,red,red) etc.) The ISA document doesn't mention
1971 // Therefore, disable all code which updates DMASK by setting these two:
1973 let hasPostISelHook = 0;
1976 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1977 RegisterClass dst_rc,
1979 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32>,
1980 MIMG_Mask<asm#"_V1", channels>;
1981 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1982 MIMG_Mask<asm#"_V2", channels>;
1983 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1984 MIMG_Mask<asm#"_V4", channels>;
1985 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1986 MIMG_Mask<asm#"_V8", channels>;
1987 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1988 MIMG_Mask<asm#"_V16", channels>;
1991 multiclass MIMG_Gather <bits<7> op, string asm> {
1992 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1>;
1993 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
1994 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
1995 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
1998 //===----------------------------------------------------------------------===//
1999 // Vector instruction mappings
2000 //===----------------------------------------------------------------------===//
2002 // Maps an opcode in e32 form to its e64 equivalent
2003 def getVOPe64 : InstrMapping {
2004 let FilterClass = "VOP";
2005 let RowFields = ["OpName"];
2006 let ColFields = ["Size"];
2008 let ValueCols = [["8"]];
2011 // Maps an opcode in e64 form to its e32 equivalent
2012 def getVOPe32 : InstrMapping {
2013 let FilterClass = "VOP";
2014 let RowFields = ["OpName"];
2015 let ColFields = ["Size"];
2017 let ValueCols = [["4"]];
2020 // Maps an original opcode to its commuted version
2021 def getCommuteRev : InstrMapping {
2022 let FilterClass = "VOP2_REV";
2023 let RowFields = ["RevOp"];
2024 let ColFields = ["IsOrig"];
2026 let ValueCols = [["0"]];
2029 def getMaskedMIMGOp : InstrMapping {
2030 let FilterClass = "MIMG_Mask";
2031 let RowFields = ["Op"];
2032 let ColFields = ["Channels"];
2034 let ValueCols = [["1"], ["2"], ["3"] ];
2037 // Maps an commuted opcode to its original version
2038 def getCommuteOrig : InstrMapping {
2039 let FilterClass = "VOP2_REV";
2040 let RowFields = ["RevOp"];
2041 let ColFields = ["IsOrig"];
2043 let ValueCols = [["1"]];
2046 def getMCOpcodeGen : InstrMapping {
2047 let FilterClass = "SIMCInstr";
2048 let RowFields = ["PseudoInstr"];
2049 let ColFields = ["Subtarget"];
2050 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2051 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2054 def getAddr64Inst : InstrMapping {
2055 let FilterClass = "MUBUFAddr64Table";
2056 let RowFields = ["OpName"];
2057 let ColFields = ["IsAddr64"];
2059 let ValueCols = [["1"]];
2062 // Maps an atomic opcode to its version with a return value.
2063 def getAtomicRetOp : InstrMapping {
2064 let FilterClass = "AtomicNoRet";
2065 let RowFields = ["NoRetOp"];
2066 let ColFields = ["IsRet"];
2068 let ValueCols = [["1"]];
2071 // Maps an atomic opcode to its returnless version.
2072 def getAtomicNoRetOp : InstrMapping {
2073 let FilterClass = "AtomicNoRet";
2074 let RowFields = ["NoRetOp"];
2075 let ColFields = ["IsRet"];
2077 let ValueCols = [["0"]];
2080 include "SIInstructions.td"
2081 include "CIInstructions.td"
2082 include "VIInstructions.td"