1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
11 // in AMDGPUMCInstLower.h
17 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
21 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
22 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
23 [SDNPMayLoad, SDNPMemOperand]
26 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
28 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
29 SDTCisVT<1, iAny>, // vdata(VGPR)
30 SDTCisVT<2, i32>, // num_channels(imm)
31 SDTCisVT<3, i32>, // vaddr(VGPR)
32 SDTCisVT<4, i32>, // soffset(SGPR)
33 SDTCisVT<5, i32>, // inst_offset(imm)
34 SDTCisVT<6, i32>, // dfmt(imm)
35 SDTCisVT<7, i32>, // nfmt(imm)
36 SDTCisVT<8, i32>, // offen(imm)
37 SDTCisVT<9, i32>, // idxen(imm)
38 SDTCisVT<10, i32>, // glc(imm)
39 SDTCisVT<11, i32>, // slc(imm)
40 SDTCisVT<12, i32> // tfe(imm)
42 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
45 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
46 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
50 class SDSample<string opcode> : SDNode <opcode,
51 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
52 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
55 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
56 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
57 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
58 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
60 def SIconstdata_ptr : SDNode<
61 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
64 // Transformation function, extract the lower 32bit of a 64bit immediate
65 def LO32 : SDNodeXForm<imm, [{
66 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
69 def LO32f : SDNodeXForm<fpimm, [{
70 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
71 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
74 // Transformation function, extract the upper 32bit of a 64bit immediate
75 def HI32 : SDNodeXForm<imm, [{
76 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
79 def HI32f : SDNodeXForm<fpimm, [{
80 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
81 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
84 def IMM8bitDWORD : PatLeaf <(imm),
85 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
88 def as_dword_i32imm : SDNodeXForm<imm, [{
89 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
92 def as_i1imm : SDNodeXForm<imm, [{
93 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
96 def as_i8imm : SDNodeXForm<imm, [{
97 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
100 def as_i16imm : SDNodeXForm<imm, [{
101 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
104 def as_i32imm: SDNodeXForm<imm, [{
105 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
108 def IMM8bit : PatLeaf <(imm),
109 [{return isUInt<8>(N->getZExtValue());}]
112 def IMM12bit : PatLeaf <(imm),
113 [{return isUInt<12>(N->getZExtValue());}]
116 def IMM16bit : PatLeaf <(imm),
117 [{return isUInt<16>(N->getZExtValue());}]
120 def IMM32bit : PatLeaf <(imm),
121 [{return isUInt<32>(N->getZExtValue());}]
124 def mubuf_vaddr_offset : PatFrag<
125 (ops node:$ptr, node:$offset, node:$imm_offset),
126 (add (add node:$ptr, node:$offset), node:$imm_offset)
129 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
130 return isInlineImmediate(N);
133 class SGPRImm <dag frag> : PatLeaf<frag, [{
134 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
135 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
138 const SIRegisterInfo *SIRI =
139 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
140 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
142 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
149 //===----------------------------------------------------------------------===//
151 //===----------------------------------------------------------------------===//
153 def FRAMEri32 : Operand<iPTR> {
154 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
157 def sopp_brtarget : Operand<OtherVT> {
158 let EncoderMethod = "getSOPPBrEncoding";
159 let OperandType = "OPERAND_PCREL";
162 include "SIInstrFormats.td"
164 let OperandType = "OPERAND_IMMEDIATE" in {
166 def offen : Operand<i1> {
167 let PrintMethod = "printOffen";
169 def idxen : Operand<i1> {
170 let PrintMethod = "printIdxen";
172 def addr64 : Operand<i1> {
173 let PrintMethod = "printAddr64";
175 def mbuf_offset : Operand<i16> {
176 let PrintMethod = "printMBUFOffset";
178 def glc : Operand <i1> {
179 let PrintMethod = "printGLC";
181 def slc : Operand <i1> {
182 let PrintMethod = "printSLC";
184 def tfe : Operand <i1> {
185 let PrintMethod = "printTFE";
188 def omod : Operand <i32> {
189 let PrintMethod = "printOModSI";
192 def ClampMod : Operand <i1> {
193 let PrintMethod = "printClampSI";
196 } // End OperandType = "OPERAND_IMMEDIATE"
198 //===----------------------------------------------------------------------===//
200 //===----------------------------------------------------------------------===//
202 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
203 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
205 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
206 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
207 def MUBUFAddr64Atomic : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
208 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
209 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
210 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
212 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
213 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
215 //===----------------------------------------------------------------------===//
216 // SI assembler operands
217 //===----------------------------------------------------------------------===//
237 //===----------------------------------------------------------------------===//
239 // SI Instruction multiclass helpers.
241 // Instructions with _32 take 32-bit operands.
242 // Instructions with _64 take 64-bit operands.
244 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
245 // encoding is the standard encoding, but instruction that make use of
246 // any of the instruction modifiers must use the 64-bit encoding.
248 // Instructions with _e32 use the 32-bit encoding.
249 // Instructions with _e64 use the 64-bit encoding.
251 //===----------------------------------------------------------------------===//
253 class SIMCInstr <string pseudo, int subtarget> {
254 string PseudoInstr = pseudo;
255 int Subtarget = subtarget;
258 //===----------------------------------------------------------------------===//
260 //===----------------------------------------------------------------------===//
262 class SOP1_32 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
263 op, (outs SReg_32:$dst), (ins SSrc_32:$src0),
264 opName#" $dst, $src0", pattern
267 class SOP1_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
268 op, (outs SReg_64:$dst), (ins SSrc_64:$src0),
269 opName#" $dst, $src0", pattern
272 // 64-bit input, 32-bit output.
273 class SOP1_32_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
274 op, (outs SReg_32:$dst), (ins SSrc_64:$src0),
275 opName#" $dst, $src0", pattern
278 class SOP2_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
279 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
280 opName#" $dst, $src0, $src1", pattern
283 class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
284 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
285 opName#" $dst, $src0, $src1", pattern
288 class SOP2_SHIFT_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
289 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
290 opName#" $dst, $src0, $src1", pattern
294 class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
295 string opName, PatLeaf cond> : SOPC <
296 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
297 opName#" $dst, $src0, $src1", []>;
299 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
300 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
302 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
303 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
305 class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
306 op, (outs SReg_32:$dst), (ins i16imm:$src0),
307 opName#" $dst, $src0", pattern
310 class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
311 op, (outs SReg_64:$dst), (ins i16imm:$src0),
312 opName#" $dst, $src0", pattern
315 //===----------------------------------------------------------------------===//
317 //===----------------------------------------------------------------------===//
319 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
320 SMRD <outs, ins, "", pattern>,
321 SIMCInstr<opName, SISubtarget.NONE> {
325 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
327 SMRD <outs, ins, asm, []>,
329 SIMCInstr<opName, SISubtarget.SI>;
331 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
332 string asm, list<dag> pattern> {
334 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
336 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
340 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
341 RegisterClass dstClass> {
343 op, opName#"_IMM", 1, (outs dstClass:$dst),
344 (ins baseClass:$sbase, u32imm:$offset),
345 opName#" $dst, $sbase, $offset", []
348 defm _SGPR : SMRD_m <
349 op, opName#"_SGPR", 0, (outs dstClass:$dst),
350 (ins baseClass:$sbase, SReg_32:$soff),
351 opName#" $dst, $sbase, $soff", []
355 //===----------------------------------------------------------------------===//
356 // Vector ALU classes
357 //===----------------------------------------------------------------------===//
359 // This must always be right before the operand being input modified.
360 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
361 let PrintMethod = "printOperandAndMods";
363 def InputModsNoDefault : Operand <i32> {
364 let PrintMethod = "printOperandAndMods";
367 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
369 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
370 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
374 // Returns the register class to use for the destination of VOP[123C]
375 // instructions for the given VT.
376 class getVALUDstForVT<ValueType VT> {
377 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
380 // Returns the register class to use for source 0 of VOP[12C]
381 // instructions for the given VT.
382 class getVOPSrc0ForVT<ValueType VT> {
383 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
386 // Returns the register class to use for source 1 of VOP[12C] for the
388 class getVOPSrc1ForVT<ValueType VT> {
389 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
392 // Returns the register classes for the source arguments of a VOP[12C]
393 // instruction for the given SrcVTs.
394 class getInRC32 <list<ValueType> SrcVT> {
395 list<RegisterClass> ret = [
396 getVOPSrc0ForVT<SrcVT[0]>.ret,
397 getVOPSrc1ForVT<SrcVT[1]>.ret
401 // Returns the register class to use for sources of VOP3 instructions for the
403 class getVOP3SrcForVT<ValueType VT> {
404 RegisterClass ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
407 // Returns the register classes for the source arguments of a VOP3
408 // instruction for the given SrcVTs.
409 class getInRC64 <list<ValueType> SrcVT> {
410 list<RegisterClass> ret = [
411 getVOP3SrcForVT<SrcVT[0]>.ret,
412 getVOP3SrcForVT<SrcVT[1]>.ret,
413 getVOP3SrcForVT<SrcVT[2]>.ret
417 // Returns 1 if the source arguments have modifiers, 0 if they do not.
418 class hasModifiers<ValueType SrcVT> {
419 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
420 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
423 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
424 class getIns32 <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
425 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
426 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
430 // Returns the input arguments for VOP3 instructions for the given SrcVT.
431 class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC,
432 RegisterClass Src2RC, int NumSrcArgs,
436 !if (!eq(NumSrcArgs, 1),
437 !if (!eq(HasModifiers, 1),
438 // VOP1 with modifiers
439 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
440 ClampMod:$clamp, omod:$omod)
442 // VOP1 without modifiers
445 !if (!eq(NumSrcArgs, 2),
446 !if (!eq(HasModifiers, 1),
447 // VOP 2 with modifiers
448 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
449 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
450 ClampMod:$clamp, omod:$omod)
452 // VOP2 without modifiers
453 (ins Src0RC:$src0, Src1RC:$src1)
455 /* NumSrcArgs == 3 */,
456 !if (!eq(HasModifiers, 1),
457 // VOP3 with modifiers
458 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
459 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
460 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
461 ClampMod:$clamp, omod:$omod)
463 // VOP3 without modifiers
464 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
468 // Returns the assembly string for the inputs and outputs of a VOP[12C]
469 // instruction. This does not add the _e32 suffix, so it can be reused
471 class getAsm32 <int NumSrcArgs> {
472 string src1 = ", $src1";
473 string src2 = ", $src2";
474 string ret = " $dst, $src0"#
475 !if(!eq(NumSrcArgs, 1), "", src1)#
476 !if(!eq(NumSrcArgs, 3), src2, "");
479 // Returns the assembly string for the inputs and outputs of a VOP3
481 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
482 string src0 = "$src0_modifiers,";
483 string src1 = !if(!eq(NumSrcArgs, 1), "",
484 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
485 " $src1_modifiers,"));
486 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
488 !if(!eq(HasModifiers, 0),
489 getAsm32<NumSrcArgs>.ret,
490 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
494 class VOPProfile <list<ValueType> _ArgVT> {
496 field list<ValueType> ArgVT = _ArgVT;
498 field ValueType DstVT = ArgVT[0];
499 field ValueType Src0VT = ArgVT[1];
500 field ValueType Src1VT = ArgVT[2];
501 field ValueType Src2VT = ArgVT[3];
502 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
503 field RegisterClass Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
504 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
505 field RegisterClass Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
506 field RegisterClass Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
507 field RegisterClass Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
509 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
510 field bit HasModifiers = hasModifiers<Src0VT>.ret;
512 field dag Outs = (outs DstRC:$dst);
514 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
515 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
518 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
519 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
522 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
523 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
524 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
525 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
526 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
527 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
528 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
529 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
530 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
532 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
533 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
534 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
535 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
536 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
537 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
538 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
539 let Src0RC32 = VCSrc_32;
541 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
542 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
544 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
545 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
546 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
547 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
550 class VOP <string opName> {
551 string OpName = opName;
554 class VOP2_REV <string revOp, bit isOrig> {
555 string RevOp = revOp;
559 class AtomicNoRet <string noRetOp, bit isRet> {
560 string NoRetOp = noRetOp;
564 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
566 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
567 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
568 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
569 bits<2> omod = !if(HasModifiers, ?, 0);
570 bits<1> clamp = !if(HasModifiers, ?, 0);
571 bits<9> src1 = !if(HasSrc1, ?, 0);
572 bits<9> src2 = !if(HasSrc2, ?, 0);
575 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
576 VOP3Common <outs, ins, "", pattern>,
578 SIMCInstr<opName, SISubtarget.NONE> {
582 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
583 VOP3 <op, outs, ins, asm, []>,
584 SIMCInstr<opName, SISubtarget.SI>;
586 multiclass VOP3_m <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern,
587 string opName, int NumSrcArgs, bit HasMods = 1> {
589 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
591 def _si : VOP3_Real_si <op, outs, ins, asm, opName>,
592 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
593 !if(!eq(NumSrcArgs, 2), 0, 1),
598 multiclass VOP3_1_m <bits<8> op, dag outs, dag ins, string asm,
599 list<dag> pattern, string opName, bit HasMods = 1> {
601 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
603 def _si : VOP3_Real_si <
604 {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
605 outs, ins, asm, opName>,
606 VOP3DisableFields<0, 0, HasMods>;
609 multiclass VOP3_2_m <bits<9> op, dag outs, dag ins, string asm,
610 list<dag> pattern, string opName, string revOp,
611 bit HasMods = 1, bit UseFullOp = 0> {
613 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
614 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
616 def _si : VOP3_Real_si <op,
617 outs, ins, asm, opName>,
618 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>,
619 VOP3DisableFields<1, 0, HasMods>;
622 multiclass VOP3b_2_m <bits<9> op, dag outs, dag ins, string asm,
623 list<dag> pattern, string opName, string revOp,
624 bit HasMods = 1, bit UseFullOp = 0> {
625 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
626 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
628 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
629 // can write it into any SGPR. We currently don't use the carry out,
630 // so for now hardcode it to VCC as well.
631 let sdst = SIOperand.VCC, Defs = [VCC] in {
632 def _si : VOP3b <op, outs, ins, asm, pattern>,
633 VOP3DisableFields<1, 0, HasMods>,
634 SIMCInstr<opName, SISubtarget.SI>,
635 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
636 } // End sdst = SIOperand.VCC, Defs = [VCC]
639 multiclass VOP3_C_m <bits<8> op, dag outs, dag ins, string asm,
640 list<dag> pattern, string opName,
641 bit HasMods, bit defExec> {
643 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
645 def _si : VOP3_Real_si <
646 {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
647 outs, ins, asm, opName>,
648 VOP3DisableFields<1, 0, HasMods> {
649 let Defs = !if(defExec, [EXEC], []);
653 multiclass VOP1_Helper <bits<8> op, string opName, dag outs,
654 dag ins32, string asm32, list<dag> pat32,
655 dag ins64, string asm64, list<dag> pat64,
658 def _e32 : VOP1 <op, outs, ins32, opName#asm32, pat32>, VOP<opName>;
660 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
663 multiclass VOP1Inst <bits<8> op, string opName, VOPProfile P,
664 SDPatternOperator node = null_frag> : VOP1_Helper <
666 P.Ins32, P.Asm32, [],
669 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
670 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
671 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
675 class VOP2_e32 <bits<6> op, string opName, dag outs, dag ins, string asm,
676 list<dag> pattern, string revOp> :
677 VOP2 <op, outs, ins, opName#asm, pattern>,
679 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
681 multiclass VOP2_Helper <bits<6> op, string opName, dag outs,
682 dag ins32, string asm32, list<dag> pat32,
683 dag ins64, string asm64, list<dag> pat64,
684 string revOp, bit HasMods> {
685 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
687 defm _e64 : VOP3_2_m <
688 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
689 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
693 multiclass VOP2Inst <bits<6> op, string opName, VOPProfile P,
694 SDPatternOperator node = null_frag,
695 string revOp = opName> : VOP2_Helper <
697 P.Ins32, P.Asm32, [],
701 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
702 i1:$clamp, i32:$omod)),
703 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
704 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
705 revOp, P.HasModifiers
708 multiclass VOP2b_Helper <bits<6> op, string opName, dag outs,
709 dag ins32, string asm32, list<dag> pat32,
710 dag ins64, string asm64, list<dag> pat64,
711 string revOp, bit HasMods> {
713 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
715 defm _e64 : VOP3b_2_m <
716 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
717 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
721 multiclass VOP2bInst <bits<6> op, string opName, VOPProfile P,
722 SDPatternOperator node = null_frag,
723 string revOp = opName> : VOP2b_Helper <
725 P.Ins32, P.Asm32, [],
729 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
730 i1:$clamp, i32:$omod)),
731 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
732 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
733 revOp, P.HasModifiers
736 multiclass VOPC_Helper <bits<8> op, string opName,
737 dag ins32, string asm32, list<dag> pat32,
738 dag out64, dag ins64, string asm64, list<dag> pat64,
739 bit HasMods, bit DefExec> {
740 def _e32 : VOPC <op, ins32, opName#asm32, pat32>, VOP <opName> {
741 let Defs = !if(DefExec, [EXEC], []);
744 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64, opName,
748 multiclass VOPCInst <bits<8> op, string opName,
749 VOPProfile P, PatLeaf cond = COND_NULL,
750 bit DefExec = 0> : VOPC_Helper <
752 P.Ins32, P.Asm32, [],
753 (outs SReg_64:$dst), P.Ins64, P.Asm64,
756 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
757 i1:$clamp, i32:$omod)),
758 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
760 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
761 P.HasModifiers, DefExec
764 multiclass VOPC_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
765 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
767 multiclass VOPC_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
768 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
770 multiclass VOPC_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
771 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
773 multiclass VOPC_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
774 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
777 multiclass VOPCX <bits<8> op, string opName, VOPProfile P,
778 PatLeaf cond = COND_NULL>
779 : VOPCInst <op, opName, P, cond, 1>;
781 multiclass VOPCX_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
782 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
784 multiclass VOPCX_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
785 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
787 multiclass VOPCX_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
788 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
790 multiclass VOPCX_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
791 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
793 multiclass VOP3_Helper <bits<9> op, string opName, dag outs, dag ins, string asm,
794 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
795 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
798 multiclass VOP3Inst <bits<9> op, string opName, VOPProfile P,
799 SDPatternOperator node = null_frag> : VOP3_Helper <
800 op, opName, P.Outs, P.Ins64, P.Asm64,
801 !if(!eq(P.NumSrcArgs, 3),
804 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
805 i1:$clamp, i32:$omod)),
806 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
807 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
808 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
810 !if(!eq(P.NumSrcArgs, 2),
813 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
814 i1:$clamp, i32:$omod)),
815 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
816 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
817 /* P.NumSrcArgs == 1 */,
820 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
821 i1:$clamp, i32:$omod))))],
822 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
823 P.NumSrcArgs, P.HasModifiers
826 multiclass VOP3b_Helper <bits<9> op, RegisterClass vrc, RegisterClass arc,
827 string opName, list<dag> pattern> :
829 op, (outs vrc:$dst0, SReg_64:$dst1),
830 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
831 InputModsNoDefault:$src1_modifiers, arc:$src1,
832 InputModsNoDefault:$src2_modifiers, arc:$src2,
833 ClampMod:$clamp, i32imm:$omod),
834 opName#" $dst0, $dst1, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
838 multiclass VOP3b_64 <bits<9> op, string opName, list<dag> pattern> :
839 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
841 multiclass VOP3b_32 <bits<9> op, string opName, list<dag> pattern> :
842 VOP3b_Helper <op, VReg_32, VSrc_32, opName, pattern>;
845 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
846 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
847 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
848 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
849 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
850 i32:$src1_modifiers, P.Src1VT:$src1,
851 i32:$src2_modifiers, P.Src2VT:$src2,
855 //===----------------------------------------------------------------------===//
856 // Vector I/O classes
857 //===----------------------------------------------------------------------===//
859 class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
860 DS <op, outs, ins, asm, pat> {
863 // Single load interpret the 2 i8imm operands as a single i16 offset.
864 let offset0 = offset{7-0};
865 let offset1 = offset{15-8};
868 class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
870 (outs regClass:$vdst),
871 (ins i1imm:$gds, VReg_32:$addr, u16imm:$offset),
872 asm#" $vdst, $addr, $offset, [M0]",
880 class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
882 (outs regClass:$vdst),
883 (ins i1imm:$gds, VReg_32:$addr, u8imm:$offset0, u8imm:$offset1),
884 asm#" $vdst, $addr, $offset0, $offset1, [M0]",
892 class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
895 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, u16imm:$offset),
896 asm#" $addr, $data0, $offset [M0]",
904 class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
907 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, regClass:$data1,
908 u8imm:$offset0, u8imm:$offset1),
909 asm#" $addr, $data0, $data1, $offset0, $offset1 [M0]",
916 // 1 address, 1 data.
917 class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
920 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
921 asm#" $vdst, $addr, $data0, $offset, [M0]", []>,
922 AtomicNoRet<noRetOp, 1> {
928 let hasPostISelHook = 1; // Adjusted to no return version.
931 // 1 address, 2 data.
932 class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
935 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
936 asm#" $vdst, $addr, $data0, $data1, $offset, [M0]",
938 AtomicNoRet<noRetOp, 1> {
942 let hasPostISelHook = 1; // Adjusted to no return version.
945 // 1 address, 2 data.
946 class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
949 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
950 asm#" $addr, $data0, $data1, $offset, [M0]",
952 AtomicNoRet<noRetOp, 0> {
957 // 1 address, 1 data.
958 class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
961 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
962 asm#" $addr, $data0, $offset, [M0]",
964 AtomicNoRet<noRetOp, 0> {
971 //===----------------------------------------------------------------------===//
973 //===----------------------------------------------------------------------===//
975 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
976 MTBUF <outs, ins, "", pattern>,
977 SIMCInstr<opName, SISubtarget.NONE> {
981 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
983 MTBUF <outs, ins, asm, []>,
985 SIMCInstr<opName, SISubtarget.SI>;
987 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
990 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
992 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
996 let mayStore = 1, mayLoad = 0 in {
998 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
999 RegisterClass regClass> : MTBUF_m <
1001 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1002 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
1003 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1004 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1005 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1008 } // mayStore = 1, mayLoad = 0
1010 let mayLoad = 1, mayStore = 0 in {
1012 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1013 RegisterClass regClass> : MTBUF_m <
1014 op, opName, (outs regClass:$dst),
1015 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1016 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
1017 i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1018 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1019 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1022 } // mayLoad = 1, mayStore = 0
1024 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1026 bit IsAddr64 = is_addr64;
1027 string OpName = NAME # suffix;
1030 class MUBUFAtomicAddr64 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1031 : MUBUF <op, outs, ins, asm, pattern> {
1041 class MUBUFAtomicOffset <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1042 : MUBUF <op, outs, ins, asm, pattern> {
1052 multiclass MUBUF_Atomic <bits<7> op, string name, RegisterClass rc,
1053 ValueType vt, SDPatternOperator atomic> {
1055 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1057 // No return variants
1060 def _ADDR64 : MUBUFAtomicAddr64 <
1062 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1063 mbuf_offset:$offset, slc:$slc),
1064 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#"$slc", []
1065 >, MUBUFAddr64Table<1>, AtomicNoRet<NAME#"_ADDR64", 0>;
1067 def _OFFSET : MUBUFAtomicOffset <
1069 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1070 SSrc_32:$soffset, slc:$slc),
1071 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", []
1072 >, MUBUFAddr64Table<0>, AtomicNoRet<NAME#"_OFFSET", 0>;
1075 // Variant that return values
1076 let glc = 1, Constraints = "$vdata = $vdata_in",
1077 DisableEncoding = "$vdata_in" in {
1079 def _RTN_ADDR64 : MUBUFAtomicAddr64 <
1080 op, (outs rc:$vdata),
1081 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1082 mbuf_offset:$offset, slc:$slc),
1083 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#" glc"#"$slc",
1085 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i16:$offset,
1086 i1:$slc), vt:$vdata_in))]
1087 >, MUBUFAddr64Table<1, "_RTN">, AtomicNoRet<NAME#"_ADDR64", 1>;
1089 def _RTN_OFFSET : MUBUFAtomicOffset <
1090 op, (outs rc:$vdata),
1091 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1092 SSrc_32:$soffset, slc:$slc),
1093 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1095 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1096 i1:$slc), vt:$vdata_in))]
1097 >, MUBUFAddr64Table<0, "_RTN">, AtomicNoRet<NAME#"_OFFSET", 1>;
1101 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1104 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
1105 ValueType load_vt = i32,
1106 SDPatternOperator ld = null_frag> {
1108 let lds = 0, mayLoad = 1 in {
1112 let offen = 0, idxen = 0, vaddr = 0 in {
1113 def _OFFSET : MUBUF <op, (outs regClass:$vdata),
1114 (ins SReg_128:$srsrc,
1115 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1116 slc:$slc, tfe:$tfe),
1117 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1118 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1119 i32:$soffset, i16:$offset,
1120 i1:$glc, i1:$slc, i1:$tfe)))]>,
1121 MUBUFAddr64Table<0>;
1124 let offen = 1, idxen = 0 in {
1125 def _OFFEN : MUBUF <op, (outs regClass:$vdata),
1126 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1127 SSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1129 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1132 let offen = 0, idxen = 1 in {
1133 def _IDXEN : MUBUF <op, (outs regClass:$vdata),
1134 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1135 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1136 slc:$slc, tfe:$tfe),
1137 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1140 let offen = 1, idxen = 1 in {
1141 def _BOTHEN : MUBUF <op, (outs regClass:$vdata),
1142 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1143 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1144 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1148 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
1149 def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
1150 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1151 asm#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1152 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1153 i64:$vaddr, i16:$offset)))]>, MUBUFAddr64Table<1>;
1158 multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
1159 ValueType store_vt, SDPatternOperator st> {
1161 let addr64 = 0, lds = 0 in {
1165 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1166 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1168 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1169 "$glc"#"$slc"#"$tfe",
1173 let offen = 0, idxen = 0, vaddr = 0 in {
1174 def _OFFSET : MUBUF <
1176 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1177 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1178 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1179 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1180 i16:$offset, i1:$glc, i1:$slc,
1182 >, MUBUFAddr64Table<0>;
1183 } // offen = 0, idxen = 0, vaddr = 0
1185 let offen = 1, idxen = 0 in {
1186 def _OFFEN : MUBUF <
1188 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1189 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1190 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1191 "$glc"#"$slc"#"$tfe",
1194 } // end offen = 1, idxen = 0
1196 } // End addr64 = 0, lds = 0
1198 def _ADDR64 : MUBUF <
1200 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1201 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1202 [(st store_vt:$vdata,
1203 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>, MUBUFAddr64Table<1>
1217 let soffset = 128; // ZERO
1221 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1222 FLAT <op, (outs regClass:$data),
1223 (ins VReg_64:$addr),
1224 asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
1231 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1232 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1233 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1245 class MIMG_Mask <string op, int channels> {
1247 int Channels = channels;
1250 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1251 RegisterClass dst_rc,
1252 RegisterClass src_rc> : MIMG <
1254 (outs dst_rc:$vdata),
1255 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1256 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1258 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1259 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1264 let hasPostISelHook = 1;
1267 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1268 RegisterClass dst_rc,
1270 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_32>,
1271 MIMG_Mask<asm#"_V1", channels>;
1272 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1273 MIMG_Mask<asm#"_V2", channels>;
1274 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1275 MIMG_Mask<asm#"_V4", channels>;
1278 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1279 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VReg_32, 1>;
1280 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1281 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1282 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1285 class MIMG_Sampler_Helper <bits<7> op, string asm,
1286 RegisterClass dst_rc,
1287 RegisterClass src_rc> : MIMG <
1289 (outs dst_rc:$vdata),
1290 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1291 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1292 SReg_256:$srsrc, SReg_128:$ssamp),
1293 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1294 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1298 let hasPostISelHook = 1;
1301 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1302 RegisterClass dst_rc,
1304 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_32>,
1305 MIMG_Mask<asm#"_V1", channels>;
1306 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1307 MIMG_Mask<asm#"_V2", channels>;
1308 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1309 MIMG_Mask<asm#"_V4", channels>;
1310 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1311 MIMG_Mask<asm#"_V8", channels>;
1312 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1313 MIMG_Mask<asm#"_V16", channels>;
1316 multiclass MIMG_Sampler <bits<7> op, string asm> {
1317 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VReg_32, 1>;
1318 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1319 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1320 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1323 class MIMG_Gather_Helper <bits<7> op, string asm,
1324 RegisterClass dst_rc,
1325 RegisterClass src_rc> : MIMG <
1327 (outs dst_rc:$vdata),
1328 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1329 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1330 SReg_256:$srsrc, SReg_128:$ssamp),
1331 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1332 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1337 // DMASK was repurposed for GATHER4. 4 components are always
1338 // returned and DMASK works like a swizzle - it selects
1339 // the component to fetch. The only useful DMASK values are
1340 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1341 // (red,red,red,red) etc.) The ISA document doesn't mention
1343 // Therefore, disable all code which updates DMASK by setting these two:
1345 let hasPostISelHook = 0;
1348 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1349 RegisterClass dst_rc,
1351 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_32>,
1352 MIMG_Mask<asm#"_V1", channels>;
1353 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1354 MIMG_Mask<asm#"_V2", channels>;
1355 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1356 MIMG_Mask<asm#"_V4", channels>;
1357 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1358 MIMG_Mask<asm#"_V8", channels>;
1359 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1360 MIMG_Mask<asm#"_V16", channels>;
1363 multiclass MIMG_Gather <bits<7> op, string asm> {
1364 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VReg_32, 1>;
1365 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
1366 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
1367 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
1370 //===----------------------------------------------------------------------===//
1371 // Vector instruction mappings
1372 //===----------------------------------------------------------------------===//
1374 // Maps an opcode in e32 form to its e64 equivalent
1375 def getVOPe64 : InstrMapping {
1376 let FilterClass = "VOP";
1377 let RowFields = ["OpName"];
1378 let ColFields = ["Size"];
1380 let ValueCols = [["8"]];
1383 // Maps an opcode in e64 form to its e32 equivalent
1384 def getVOPe32 : InstrMapping {
1385 let FilterClass = "VOP";
1386 let RowFields = ["OpName"];
1387 let ColFields = ["Size"];
1389 let ValueCols = [["4"]];
1392 // Maps an original opcode to its commuted version
1393 def getCommuteRev : InstrMapping {
1394 let FilterClass = "VOP2_REV";
1395 let RowFields = ["RevOp"];
1396 let ColFields = ["IsOrig"];
1398 let ValueCols = [["0"]];
1401 def getMaskedMIMGOp : InstrMapping {
1402 let FilterClass = "MIMG_Mask";
1403 let RowFields = ["Op"];
1404 let ColFields = ["Channels"];
1406 let ValueCols = [["1"], ["2"], ["3"] ];
1409 // Maps an commuted opcode to its original version
1410 def getCommuteOrig : InstrMapping {
1411 let FilterClass = "VOP2_REV";
1412 let RowFields = ["RevOp"];
1413 let ColFields = ["IsOrig"];
1415 let ValueCols = [["1"]];
1418 def isDS : InstrMapping {
1419 let FilterClass = "DS";
1420 let RowFields = ["Inst"];
1421 let ColFields = ["Size"];
1423 let ValueCols = [["8"]];
1426 def getMCOpcode : InstrMapping {
1427 let FilterClass = "SIMCInstr";
1428 let RowFields = ["PseudoInstr"];
1429 let ColFields = ["Subtarget"];
1430 let KeyCol = [!cast<string>(SISubtarget.NONE)];
1431 let ValueCols = [[!cast<string>(SISubtarget.SI)]];
1434 def getAddr64Inst : InstrMapping {
1435 let FilterClass = "MUBUFAddr64Table";
1436 let RowFields = ["OpName"];
1437 let ColFields = ["IsAddr64"];
1439 let ValueCols = [["1"]];
1442 // Maps an atomic opcode to its version with a return value.
1443 def getAtomicRetOp : InstrMapping {
1444 let FilterClass = "AtomicNoRet";
1445 let RowFields = ["NoRetOp"];
1446 let ColFields = ["IsRet"];
1448 let ValueCols = [["1"]];
1451 // Maps an atomic opcode to its returnless version.
1452 def getAtomicNoRetOp : InstrMapping {
1453 let FilterClass = "AtomicNoRet";
1454 let RowFields = ["NoRetOp"];
1455 let ColFields = ["IsRet"];
1457 let ValueCols = [["0"]];
1460 include "SIInstructions.td"