1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
15 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
16 field bits<8> SI = si;
17 field bits<8> VI = vi;
19 field bits<9> SI3 = {0, si{7-0}};
20 field bits<10> VI3 = {0, 0, vi{7-0}};
23 class vop1 <bits<8> si, bits<8> vi = si> : vop {
24 field bits<8> SI = si;
25 field bits<8> VI = vi;
27 field bits<9> SI3 = {1, 1, si{6-0}};
28 field bits<10> VI3 = !add(0x140, vi);
31 class vop2 <bits<6> si, bits<6> vi = si> : vop {
32 field bits<6> SI = si;
33 field bits<6> VI = vi;
35 field bits<9> SI3 = {1, 0, 0, si{5-0}};
36 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
39 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
40 // that doesn't have VOP2 encoding on VI
41 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
45 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
50 class sop1 <bits<8> si, bits<8> vi = si> {
51 field bits<8> SI = si;
52 field bits<8> VI = vi;
55 class sop2 <bits<7> si, bits<7> vi = si> {
56 field bits<7> SI = si;
57 field bits<7> VI = vi;
60 class sopk <bits<5> si, bits<5> vi = si> {
61 field bits<5> SI = si;
62 field bits<5> VI = vi;
65 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
66 // in AMDGPUInstrInfo.cpp
73 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
77 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
78 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
79 [SDNPMayLoad, SDNPMemOperand]
82 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
84 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
85 SDTCisVT<1, iAny>, // vdata(VGPR)
86 SDTCisVT<2, i32>, // num_channels(imm)
87 SDTCisVT<3, i32>, // vaddr(VGPR)
88 SDTCisVT<4, i32>, // soffset(SGPR)
89 SDTCisVT<5, i32>, // inst_offset(imm)
90 SDTCisVT<6, i32>, // dfmt(imm)
91 SDTCisVT<7, i32>, // nfmt(imm)
92 SDTCisVT<8, i32>, // offen(imm)
93 SDTCisVT<9, i32>, // idxen(imm)
94 SDTCisVT<10, i32>, // glc(imm)
95 SDTCisVT<11, i32>, // slc(imm)
96 SDTCisVT<12, i32> // tfe(imm)
98 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
101 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
102 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
106 class SDSample<string opcode> : SDNode <opcode,
107 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
108 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
111 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
112 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
113 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
114 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
116 def SIconstdata_ptr : SDNode<
117 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
120 // Transformation function, extract the lower 32bit of a 64bit immediate
121 def LO32 : SDNodeXForm<imm, [{
122 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
125 def LO32f : SDNodeXForm<fpimm, [{
126 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
127 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
130 // Transformation function, extract the upper 32bit of a 64bit immediate
131 def HI32 : SDNodeXForm<imm, [{
132 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
135 def HI32f : SDNodeXForm<fpimm, [{
136 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
137 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
140 def IMM8bitDWORD : PatLeaf <(imm),
141 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
144 def as_dword_i32imm : SDNodeXForm<imm, [{
145 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
148 def as_i1imm : SDNodeXForm<imm, [{
149 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
152 def as_i8imm : SDNodeXForm<imm, [{
153 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
156 def as_i16imm : SDNodeXForm<imm, [{
157 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
160 def as_i32imm: SDNodeXForm<imm, [{
161 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
164 def as_i64imm: SDNodeXForm<imm, [{
165 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
168 // Copied from the AArch64 backend:
169 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
170 return CurDAG->getTargetConstant(
171 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
174 // Copied from the AArch64 backend:
175 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
176 return CurDAG->getTargetConstant(
177 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
180 def IMM8bit : PatLeaf <(imm),
181 [{return isUInt<8>(N->getZExtValue());}]
184 def IMM12bit : PatLeaf <(imm),
185 [{return isUInt<12>(N->getZExtValue());}]
188 def IMM16bit : PatLeaf <(imm),
189 [{return isUInt<16>(N->getZExtValue());}]
192 def IMM20bit : PatLeaf <(imm),
193 [{return isUInt<20>(N->getZExtValue());}]
196 def IMM32bit : PatLeaf <(imm),
197 [{return isUInt<32>(N->getZExtValue());}]
200 def mubuf_vaddr_offset : PatFrag<
201 (ops node:$ptr, node:$offset, node:$imm_offset),
202 (add (add node:$ptr, node:$offset), node:$imm_offset)
205 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
206 return isInlineImmediate(N);
209 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
210 return isInlineImmediate(N);
213 class SGPRImm <dag frag> : PatLeaf<frag, [{
214 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
217 const SIRegisterInfo *SIRI =
218 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
219 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
221 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
228 //===----------------------------------------------------------------------===//
230 //===----------------------------------------------------------------------===//
232 def FRAMEri32 : Operand<iPTR> {
233 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
236 def sopp_brtarget : Operand<OtherVT> {
237 let EncoderMethod = "getSOPPBrEncoding";
238 let OperandType = "OPERAND_PCREL";
241 include "SIInstrFormats.td"
242 include "VIInstrFormats.td"
244 let OperandType = "OPERAND_IMMEDIATE" in {
246 def offen : Operand<i1> {
247 let PrintMethod = "printOffen";
249 def idxen : Operand<i1> {
250 let PrintMethod = "printIdxen";
252 def addr64 : Operand<i1> {
253 let PrintMethod = "printAddr64";
255 def mbuf_offset : Operand<i16> {
256 let PrintMethod = "printMBUFOffset";
258 def ds_offset : Operand<i16> {
259 let PrintMethod = "printDSOffset";
261 def ds_offset0 : Operand<i8> {
262 let PrintMethod = "printDSOffset0";
264 def ds_offset1 : Operand<i8> {
265 let PrintMethod = "printDSOffset1";
267 def glc : Operand <i1> {
268 let PrintMethod = "printGLC";
270 def slc : Operand <i1> {
271 let PrintMethod = "printSLC";
273 def tfe : Operand <i1> {
274 let PrintMethod = "printTFE";
277 def omod : Operand <i32> {
278 let PrintMethod = "printOModSI";
281 def ClampMod : Operand <i1> {
282 let PrintMethod = "printClampSI";
285 } // End OperandType = "OPERAND_IMMEDIATE"
287 //===----------------------------------------------------------------------===//
289 //===----------------------------------------------------------------------===//
291 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
292 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
294 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
295 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
296 def MUBUFAddr64Atomic : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
297 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
298 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
299 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
301 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
302 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
303 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
304 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
306 //===----------------------------------------------------------------------===//
307 // SI assembler operands
308 //===----------------------------------------------------------------------===//
328 //===----------------------------------------------------------------------===//
330 // SI Instruction multiclass helpers.
332 // Instructions with _32 take 32-bit operands.
333 // Instructions with _64 take 64-bit operands.
335 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
336 // encoding is the standard encoding, but instruction that make use of
337 // any of the instruction modifiers must use the 64-bit encoding.
339 // Instructions with _e32 use the 32-bit encoding.
340 // Instructions with _e64 use the 64-bit encoding.
342 //===----------------------------------------------------------------------===//
344 class SIMCInstr <string pseudo, int subtarget> {
345 string PseudoInstr = pseudo;
346 int Subtarget = subtarget;
349 //===----------------------------------------------------------------------===//
351 //===----------------------------------------------------------------------===//
353 class EXPCommon : InstSI<
355 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
356 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
357 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
366 let isPseudo = 1 in {
367 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
370 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
372 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
375 //===----------------------------------------------------------------------===//
377 //===----------------------------------------------------------------------===//
379 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
380 SOP1 <outs, ins, "", pattern>,
381 SIMCInstr<opName, SISubtarget.NONE> {
385 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
386 SOP1 <outs, ins, asm, []>,
388 SIMCInstr<opName, SISubtarget.SI>;
390 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
391 SOP1 <outs, ins, asm, []>,
393 SIMCInstr<opName, SISubtarget.VI>;
395 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> {
396 def "" : SOP1_Pseudo <opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
399 def _si : SOP1_Real_si <op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
400 opName#" $dst, $src0">;
402 def _vi : SOP1_Real_vi <op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
403 opName#" $dst, $src0">;
406 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> {
407 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
410 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
411 opName#" $dst, $src0">;
413 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
414 opName#" $dst, $src0">;
417 // no input, 64-bit output.
418 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
419 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
421 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
426 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
432 // 64-bit input, 32-bit output.
433 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> {
434 def "" : SOP1_Pseudo <opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
437 def _si : SOP1_Real_si <op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
438 opName#" $dst, $src0">;
440 def _vi : SOP1_Real_vi <op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
441 opName#" $dst, $src0">;
444 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
445 SOP2<outs, ins, "", pattern>,
446 SIMCInstr<opName, SISubtarget.NONE> {
451 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
452 SOP2<outs, ins, asm, []>,
454 SIMCInstr<opName, SISubtarget.SI>;
456 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
457 SOP2<outs, ins, asm, []>,
459 SIMCInstr<opName, SISubtarget.VI>;
461 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
462 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
463 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
465 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
466 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
467 opName#" $dst, $src0, $src1 [$scc]">;
469 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
470 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
471 opName#" $dst, $src0, $src1 [$scc]">;
474 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> {
475 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
476 (ins SSrc_32:$src0, SSrc_32:$src1), pattern>;
478 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
479 (ins SSrc_32:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
481 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
482 (ins SSrc_32:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
485 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> {
486 def "" : SOP2_Pseudo <opName, (outs SReg_64:$dst),
487 (ins SSrc_64:$src0, SSrc_64:$src1), pattern>;
489 def _si : SOP2_Real_si <op, opName, (outs SReg_64:$dst),
490 (ins SSrc_64:$src0, SSrc_64:$src1), opName#" $dst, $src0, $src1">;
492 def _vi : SOP2_Real_vi <op, opName, (outs SReg_64:$dst),
493 (ins SSrc_64:$src0, SSrc_64:$src1), opName#" $dst, $src0, $src1">;
496 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> {
497 def "" : SOP2_Pseudo <opName, (outs SReg_64:$dst),
498 (ins SSrc_64:$src0, SSrc_32:$src1), pattern>;
500 def _si : SOP2_Real_si <op, opName, (outs SReg_64:$dst),
501 (ins SSrc_64:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
503 def _vi : SOP2_Real_vi <op, opName, (outs SReg_64:$dst),
504 (ins SSrc_64:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1">;
508 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
509 string opName, PatLeaf cond> : SOPC <
510 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
511 opName#" $dst, $src0, $src1", []>;
513 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
514 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
516 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
517 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
519 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
520 SOPK <outs, ins, "", pattern>,
521 SIMCInstr<opName, SISubtarget.NONE> {
525 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
526 SOPK <outs, ins, asm, []>,
528 SIMCInstr<opName, SISubtarget.SI>;
530 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
531 SOPK <outs, ins, asm, []>,
533 SIMCInstr<opName, SISubtarget.VI>;
535 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
536 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
539 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
540 opName#" $dst, $src0">;
542 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
543 opName#" $dst, $src0">;
546 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
547 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
548 (ins SReg_32:$src0, u16imm:$src1), pattern>;
550 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
551 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
553 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
554 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
557 //===----------------------------------------------------------------------===//
559 //===----------------------------------------------------------------------===//
561 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
562 SMRD <outs, ins, "", pattern>,
563 SIMCInstr<opName, SISubtarget.NONE> {
567 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
569 SMRD <outs, ins, asm, []>,
571 SIMCInstr<opName, SISubtarget.SI>;
573 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
575 SMRD <outs, ins, asm, []>,
577 SIMCInstr<opName, SISubtarget.VI>;
579 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
580 string asm, list<dag> pattern> {
582 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
584 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
586 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
589 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
590 RegisterClass dstClass> {
592 op, opName#"_IMM", 1, (outs dstClass:$dst),
593 (ins baseClass:$sbase, u32imm:$offset),
594 opName#" $dst, $sbase, $offset", []
597 defm _SGPR : SMRD_m <
598 op, opName#"_SGPR", 0, (outs dstClass:$dst),
599 (ins baseClass:$sbase, SReg_32:$soff),
600 opName#" $dst, $sbase, $soff", []
604 //===----------------------------------------------------------------------===//
605 // Vector ALU classes
606 //===----------------------------------------------------------------------===//
608 // This must always be right before the operand being input modified.
609 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
610 let PrintMethod = "printOperandAndMods";
612 def InputModsNoDefault : Operand <i32> {
613 let PrintMethod = "printOperandAndMods";
616 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
618 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
619 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
623 // Returns the register class to use for the destination of VOP[123C]
624 // instructions for the given VT.
625 class getVALUDstForVT<ValueType VT> {
626 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32,
627 !if(!eq(VT.Size, 64), VReg_64,
628 SReg_64)); // else VT == i1
631 // Returns the register class to use for source 0 of VOP[12C]
632 // instructions for the given VT.
633 class getVOPSrc0ForVT<ValueType VT> {
634 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
637 // Returns the register class to use for source 1 of VOP[12C] for the
639 class getVOPSrc1ForVT<ValueType VT> {
640 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
643 // Returns the register classes for the source arguments of a VOP[12C]
644 // instruction for the given SrcVTs.
645 class getInRC32 <list<ValueType> SrcVT> {
646 list<DAGOperand> ret = [
647 getVOPSrc0ForVT<SrcVT[0]>.ret,
648 getVOPSrc1ForVT<SrcVT[1]>.ret
652 // Returns the register class to use for sources of VOP3 instructions for the
654 class getVOP3SrcForVT<ValueType VT> {
655 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
658 // Returns the register classes for the source arguments of a VOP3
659 // instruction for the given SrcVTs.
660 class getInRC64 <list<ValueType> SrcVT> {
661 list<DAGOperand> ret = [
662 getVOP3SrcForVT<SrcVT[0]>.ret,
663 getVOP3SrcForVT<SrcVT[1]>.ret,
664 getVOP3SrcForVT<SrcVT[2]>.ret
668 // Returns 1 if the source arguments have modifiers, 0 if they do not.
669 class hasModifiers<ValueType SrcVT> {
670 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
671 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
674 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
675 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
676 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
677 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
681 // Returns the input arguments for VOP3 instructions for the given SrcVT.
682 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
683 RegisterOperand Src2RC, int NumSrcArgs,
687 !if (!eq(NumSrcArgs, 1),
688 !if (!eq(HasModifiers, 1),
689 // VOP1 with modifiers
690 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
691 ClampMod:$clamp, omod:$omod)
693 // VOP1 without modifiers
696 !if (!eq(NumSrcArgs, 2),
697 !if (!eq(HasModifiers, 1),
698 // VOP 2 with modifiers
699 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
700 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
701 ClampMod:$clamp, omod:$omod)
703 // VOP2 without modifiers
704 (ins Src0RC:$src0, Src1RC:$src1)
706 /* NumSrcArgs == 3 */,
707 !if (!eq(HasModifiers, 1),
708 // VOP3 with modifiers
709 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
710 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
711 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
712 ClampMod:$clamp, omod:$omod)
714 // VOP3 without modifiers
715 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
719 // Returns the assembly string for the inputs and outputs of a VOP[12C]
720 // instruction. This does not add the _e32 suffix, so it can be reused
722 class getAsm32 <int NumSrcArgs> {
723 string src1 = ", $src1";
724 string src2 = ", $src2";
725 string ret = " $dst, $src0"#
726 !if(!eq(NumSrcArgs, 1), "", src1)#
727 !if(!eq(NumSrcArgs, 3), src2, "");
730 // Returns the assembly string for the inputs and outputs of a VOP3
732 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
733 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
734 string src1 = !if(!eq(NumSrcArgs, 1), "",
735 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
736 " $src1_modifiers,"));
737 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
739 !if(!eq(HasModifiers, 0),
740 getAsm32<NumSrcArgs>.ret,
741 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
745 class VOPProfile <list<ValueType> _ArgVT> {
747 field list<ValueType> ArgVT = _ArgVT;
749 field ValueType DstVT = ArgVT[0];
750 field ValueType Src0VT = ArgVT[1];
751 field ValueType Src1VT = ArgVT[2];
752 field ValueType Src2VT = ArgVT[3];
753 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
754 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
755 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
756 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
757 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
758 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
760 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
761 field bit HasModifiers = hasModifiers<Src0VT>.ret;
763 field dag Outs = (outs DstRC:$dst);
765 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
766 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
769 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
770 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
773 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
774 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
775 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
776 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
777 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
778 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
779 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
780 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
781 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
783 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
784 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
785 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
786 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
787 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
788 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
789 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
790 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
791 let Src0RC32 = VCSrc_32;
794 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
795 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
796 let Asm64 = " $dst, $src0_modifiers, $src1";
799 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
800 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
801 let Asm64 = " $dst, $src0_modifiers, $src1";
804 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
805 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
806 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
808 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
809 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
810 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
811 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
814 class VOP <string opName> {
815 string OpName = opName;
818 class VOP2_REV <string revOp, bit isOrig> {
819 string RevOp = revOp;
823 class AtomicNoRet <string noRetOp, bit isRet> {
824 string NoRetOp = noRetOp;
828 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
829 VOP1Common <outs, ins, "", pattern>,
831 SIMCInstr <opName#"_e32", SISubtarget.NONE> {
835 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
837 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
839 def _si : VOP1<op.SI, outs, ins, asm, []>,
840 SIMCInstr <opName#"_e32", SISubtarget.SI>;
841 def _vi : VOP1<op.VI, outs, ins, asm, []>,
842 SIMCInstr <opName#"_e32", SISubtarget.VI>;
845 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
846 VOP2Common <outs, ins, "", pattern>,
848 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
852 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
853 string opName, string revOp> {
854 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
855 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
857 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
858 SIMCInstr <opName#"_e32", SISubtarget.SI>;
861 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
862 string opName, string revOp> {
863 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
864 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
866 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
867 SIMCInstr <opName#"_e32", SISubtarget.SI>;
868 def _vi : VOP2 <op.VI, outs, ins, opName#asm, []>,
869 SIMCInstr <opName#"_e32", SISubtarget.VI>;
872 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
874 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
875 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
876 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
877 bits<2> omod = !if(HasModifiers, ?, 0);
878 bits<1> clamp = !if(HasModifiers, ?, 0);
879 bits<9> src1 = !if(HasSrc1, ?, 0);
880 bits<9> src2 = !if(HasSrc2, ?, 0);
883 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
884 VOP3Common <outs, ins, "", pattern>,
886 SIMCInstr<opName#"_e64", SISubtarget.NONE> {
890 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
891 VOP3Common <outs, ins, asm, []>,
893 SIMCInstr<opName#"_e64", SISubtarget.SI>;
895 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
896 VOP3Common <outs, ins, asm, []>,
898 SIMCInstr <opName#"_e64", SISubtarget.VI>;
900 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
901 string opName, int NumSrcArgs, bit HasMods = 1> {
903 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
905 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
906 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
907 !if(!eq(NumSrcArgs, 2), 0, 1),
909 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
910 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
911 !if(!eq(NumSrcArgs, 2), 0, 1),
915 // VOP3_m without source modifiers
916 multiclass VOP3_m_nosrcmod <vop op, dag outs, dag ins, string asm, list<dag> pattern,
917 string opName, int NumSrcArgs, bit HasMods = 1> {
919 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
921 let src0_modifiers = 0,
923 src2_modifiers = 0 in {
924 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
925 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
929 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
930 list<dag> pattern, string opName, bit HasMods = 1> {
932 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
934 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
935 VOP3DisableFields<0, 0, HasMods>;
937 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
938 VOP3DisableFields<0, 0, HasMods>;
941 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
942 list<dag> pattern, string opName, string revOp,
943 bit HasMods = 1, bit UseFullOp = 0> {
945 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
946 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
948 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
949 VOP3DisableFields<1, 0, HasMods>;
951 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
952 VOP3DisableFields<1, 0, HasMods>;
955 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
956 list<dag> pattern, string opName, string revOp,
957 bit HasMods = 1, bit UseFullOp = 0> {
959 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
960 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
962 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
963 VOP3DisableFields<1, 0, HasMods>;
965 // No VI instruction. This class is for SI only.
968 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
969 list<dag> pattern, string opName, string revOp,
970 bit HasMods = 1, bit UseFullOp = 0> {
971 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
972 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
974 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
975 // can write it into any SGPR. We currently don't use the carry out,
976 // so for now hardcode it to VCC as well.
977 let sdst = SIOperand.VCC, Defs = [VCC] in {
978 def _si : VOP3b <op.SI3, outs, ins, asm, []>,
979 VOP3DisableFields<1, 0, HasMods>,
980 SIMCInstr<opName#"_e64", SISubtarget.SI>;
982 // TODO: Do we need this VI variant here?
983 /*def _vi : VOP3b_vi <op.VI3, outs, ins, asm, []>,
984 VOP3DisableFields<1, 0, HasMods>,
985 SIMCInstr<opName#"_e64", SISubtarget.VI>;*/
986 } // End sdst = SIOperand.VCC, Defs = [VCC]
989 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
990 list<dag> pattern, string opName,
991 bit HasMods, bit defExec> {
993 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
995 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
996 VOP3DisableFields<1, 0, HasMods> {
997 let Defs = !if(defExec, [EXEC], []);
1000 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1001 VOP3DisableFields<1, 0, HasMods> {
1002 let Defs = !if(defExec, [EXEC], []);
1006 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1007 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1008 string asm, list<dag> pattern = []> {
1009 let isPseudo = 1 in {
1010 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1011 SIMCInstr<opName, SISubtarget.NONE>;
1014 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1015 SIMCInstr <opName, SISubtarget.SI>;
1017 def _vi : VOP3Common <outs, ins, asm, []>,
1019 VOP3DisableFields <1, 0, 0>,
1020 SIMCInstr <opName, SISubtarget.VI>;
1023 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1024 dag ins32, string asm32, list<dag> pat32,
1025 dag ins64, string asm64, list<dag> pat64,
1028 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1030 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
1033 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1034 SDPatternOperator node = null_frag> : VOP1_Helper <
1036 P.Ins32, P.Asm32, [],
1039 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1040 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1041 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1045 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1046 SDPatternOperator node = null_frag> {
1048 def _e32 : VOP1 <op.SI, P.Outs, P.Ins32, opName#P.Asm32, []>,
1051 def _e64 : VOP3Common <P.Outs, P.Ins64, opName#P.Asm64,
1053 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1054 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1055 [(set P.DstVT:$dst, (node P.Src0VT:$src0))])>,
1058 VOP3DisableFields<0, 0, P.HasModifiers>;
1061 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1062 dag ins32, string asm32, list<dag> pat32,
1063 dag ins64, string asm64, list<dag> pat64,
1064 string revOp, bit HasMods> {
1065 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1067 defm _e64 : VOP3_2_m <op,
1068 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1072 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1073 SDPatternOperator node = null_frag,
1074 string revOp = opName> : VOP2_Helper <
1076 P.Ins32, P.Asm32, [],
1080 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1081 i1:$clamp, i32:$omod)),
1082 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1083 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1084 revOp, P.HasModifiers
1087 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1088 SDPatternOperator node = null_frag,
1089 string revOp = opName> {
1090 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1092 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#"_e64"#P.Asm64,
1095 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1096 i1:$clamp, i32:$omod)),
1097 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1098 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1099 opName, revOp, P.HasModifiers>;
1102 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1103 dag ins32, string asm32, list<dag> pat32,
1104 dag ins64, string asm64, list<dag> pat64,
1105 string revOp, bit HasMods> {
1107 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1109 defm _e64 : VOP3b_2_m <op,
1110 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1114 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1115 SDPatternOperator node = null_frag,
1116 string revOp = opName> : VOP2b_Helper <
1118 P.Ins32, P.Asm32, [],
1122 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1123 i1:$clamp, i32:$omod)),
1124 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1125 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1126 revOp, P.HasModifiers
1129 // A VOP2 instruction that is VOP3-only on VI.
1130 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1131 dag ins32, string asm32, list<dag> pat32,
1132 dag ins64, string asm64, list<dag> pat64,
1133 string revOp, bit HasMods> {
1134 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1136 defm _e64 : VOP3_2_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName,
1140 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1141 SDPatternOperator node = null_frag,
1142 string revOp = opName>
1145 P.Ins32, P.Asm32, [],
1149 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1150 i1:$clamp, i32:$omod)),
1151 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1152 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1153 revOp, P.HasModifiers
1156 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1157 VOPCCommon <ins, "", pattern>,
1159 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1163 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1164 string opName, bit DefExec> {
1165 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1167 def _si : VOPC<op.SI, ins, asm, []>,
1168 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1169 let Defs = !if(DefExec, [EXEC], []);
1172 def _vi : VOPC<op.VI, ins, asm, []>,
1173 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1174 let Defs = !if(DefExec, [EXEC], []);
1178 multiclass VOPC_Helper <vopc op, string opName,
1179 dag ins32, string asm32, list<dag> pat32,
1180 dag out64, dag ins64, string asm64, list<dag> pat64,
1181 bit HasMods, bit DefExec> {
1182 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1184 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1185 opName, HasMods, DefExec>;
1188 multiclass VOPCInst <vopc op, string opName,
1189 VOPProfile P, PatLeaf cond = COND_NULL,
1190 bit DefExec = 0> : VOPC_Helper <
1192 P.Ins32, P.Asm32, [],
1193 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1196 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1197 i1:$clamp, i32:$omod)),
1198 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1200 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1201 P.HasModifiers, DefExec
1204 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1205 bit DefExec = 0> : VOPC_Helper <
1207 P.Ins32, P.Asm32, [],
1208 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1211 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1212 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1213 P.HasModifiers, DefExec
1217 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1218 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
1220 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1221 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
1223 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1224 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
1226 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1227 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
1230 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1231 PatLeaf cond = COND_NULL>
1232 : VOPCInst <op, opName, P, cond, 1>;
1234 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1235 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
1237 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1238 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
1240 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1241 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
1243 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1244 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
1246 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1247 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1248 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
1251 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1252 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1254 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1255 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1257 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1258 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1260 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1261 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1263 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1264 SDPatternOperator node = null_frag> : VOP3_Helper <
1265 op, opName, P.Outs, P.Ins64, P.Asm64,
1266 !if(!eq(P.NumSrcArgs, 3),
1269 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1270 i1:$clamp, i32:$omod)),
1271 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1272 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1273 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1275 !if(!eq(P.NumSrcArgs, 2),
1278 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1279 i1:$clamp, i32:$omod)),
1280 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1281 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1282 /* P.NumSrcArgs == 1 */,
1285 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1286 i1:$clamp, i32:$omod))))],
1287 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1288 P.NumSrcArgs, P.HasModifiers
1291 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1292 string opName, list<dag> pattern> :
1294 op, (outs vrc:$vdst, SReg_64:$sdst),
1295 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1296 InputModsNoDefault:$src1_modifiers, arc:$src1,
1297 InputModsNoDefault:$src2_modifiers, arc:$src2,
1298 ClampMod:$clamp, omod:$omod),
1299 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1300 opName, opName, 1, 1
1303 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1304 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1306 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1307 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1310 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1311 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1312 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1313 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1314 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1315 i32:$src1_modifiers, P.Src1VT:$src1,
1316 i32:$src2_modifiers, P.Src2VT:$src2,
1320 //===----------------------------------------------------------------------===//
1321 // Interpolation opcodes
1322 //===----------------------------------------------------------------------===//
1324 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1325 VINTRPCommon <outs, ins, "", pattern>,
1326 SIMCInstr<opName, SISubtarget.NONE> {
1330 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1332 VINTRPCommon <outs, ins, asm, []>,
1334 SIMCInstr<opName, SISubtarget.SI>;
1336 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1338 VINTRPCommon <outs, ins, asm, []>,
1340 SIMCInstr<opName, SISubtarget.VI>;
1342 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1343 string disableEncoding = "", string constraints = "",
1344 list<dag> pattern = []> {
1345 let DisableEncoding = disableEncoding,
1346 Constraints = constraints in {
1347 def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
1349 def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
1351 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
1355 //===----------------------------------------------------------------------===//
1356 // Vector I/O classes
1357 //===----------------------------------------------------------------------===//
1359 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1360 DS <outs, ins, "", pattern>,
1361 SIMCInstr <opName, SISubtarget.NONE> {
1365 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1366 DS <outs, ins, asm, []>,
1368 SIMCInstr <opName, SISubtarget.SI>;
1370 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1371 DS <outs, ins, asm, []>,
1373 SIMCInstr <opName, SISubtarget.VI>;
1375 class DS_1A_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1376 DS <outs, ins, asm, []>,
1378 SIMCInstr <opName, SISubtarget.SI> {
1380 // Single load interpret the 2 i8imm operands as a single i16 offset.
1382 let offset0 = offset{7-0};
1383 let offset1 = offset{15-8};
1386 class DS_1A_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1387 DS <outs, ins, asm, []>,
1389 SIMCInstr <opName, SISubtarget.VI> {
1391 // Single load interpret the 2 i8imm operands as a single i16 offset.
1393 let offset0 = offset{7-0};
1394 let offset1 = offset{15-8};
1397 multiclass DS_1A_Load_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1399 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1400 def "" : DS_Pseudo <opName, outs, ins, pat>;
1402 let data0 = 0, data1 = 0 in {
1403 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1404 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1409 multiclass DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass>
1413 (outs regClass:$vdst),
1414 (ins i1imm:$gds, VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
1415 asm#" $vdst, $addr"#"$offset"#" [M0]",
1418 multiclass DS_Load2_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1420 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1421 def "" : DS_Pseudo <opName, outs, ins, pat>;
1423 let data0 = 0, data1 = 0 in {
1424 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1425 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1430 multiclass DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass>
1434 (outs regClass:$vdst),
1435 (ins i1imm:$gds, VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1437 asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]",
1440 multiclass DS_1A_Store_m <bits<8> op, string opName, dag outs, dag ins,
1441 string asm, list<dag> pat> {
1442 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1443 def "" : DS_Pseudo <opName, outs, ins, pat>;
1445 let data1 = 0, vdst = 0 in {
1446 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1447 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1452 multiclass DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass>
1457 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, ds_offset:$offset, M0Reg:$m0),
1458 asm#" $addr, $data0"#"$offset"#" [M0]",
1461 multiclass DS_Store_m <bits<8> op, string opName, dag outs, dag ins,
1462 string asm, list<dag> pat> {
1463 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1464 def "" : DS_Pseudo <opName, outs, ins, pat>;
1467 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1468 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1473 multiclass DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass>
1478 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, regClass:$data1,
1479 ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0),
1480 asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]",
1483 // 1 address, 1 data.
1484 multiclass DS_1A1D_RET_m <bits<8> op, string opName, dag outs, dag ins,
1485 string asm, list<dag> pat, string noRetOp> {
1486 let mayLoad = 1, mayStore = 1,
1487 hasPostISelHook = 1 // Adjusted to no return version.
1489 def "" : DS_Pseudo <opName, outs, ins, pat>,
1490 AtomicNoRet<noRetOp, 1>;
1493 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1494 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1499 multiclass DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc,
1500 string noRetOp = ""> : DS_1A1D_RET_m <
1503 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1504 asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", [], noRetOp>;
1506 // 1 address, 2 data.
1507 multiclass DS_1A2D_RET_m <bits<8> op, string opName, dag outs, dag ins,
1508 string asm, list<dag> pat, string noRetOp> {
1509 let mayLoad = 1, mayStore = 1,
1510 hasPostISelHook = 1 // Adjusted to no return version.
1512 def "" : DS_Pseudo <opName, outs, ins, pat>,
1513 AtomicNoRet<noRetOp, 1>;
1515 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1516 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1520 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1521 string noRetOp = ""> : DS_1A2D_RET_m <
1524 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1525 asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]",
1528 // 1 address, 2 data.
1529 multiclass DS_1A2D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
1530 string asm, list<dag> pat, string noRetOp> {
1531 let mayLoad = 1, mayStore = 1 in {
1532 def "" : DS_Pseudo <opName, outs, ins, pat>,
1533 AtomicNoRet<noRetOp, 0>;
1535 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1536 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1540 multiclass DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc,
1541 string noRetOp = asm> : DS_1A2D_NORET_m <
1544 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1545 asm#" $addr, $data0, $data1"#"$offset"#" [M0]",
1548 // 1 address, 1 data.
1549 multiclass DS_1A1D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
1550 string asm, list<dag> pat, string noRetOp> {
1551 let mayLoad = 1, mayStore = 1 in {
1552 def "" : DS_Pseudo <opName, outs, ins, pat>,
1553 AtomicNoRet<noRetOp, 0>;
1556 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1557 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1562 multiclass DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc,
1563 string noRetOp = asm> : DS_1A1D_NORET_m <
1566 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1567 asm#" $addr, $data0"#"$offset"#" [M0]",
1570 //===----------------------------------------------------------------------===//
1572 //===----------------------------------------------------------------------===//
1574 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1575 MTBUF <outs, ins, "", pattern>,
1576 SIMCInstr<opName, SISubtarget.NONE> {
1580 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1582 MTBUF <outs, ins, asm, []>,
1584 SIMCInstr<opName, SISubtarget.SI>;
1586 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1587 MTBUF <outs, ins, asm, []>,
1589 SIMCInstr <opName, SISubtarget.VI>;
1591 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1592 list<dag> pattern> {
1594 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1596 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1598 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1602 let mayStore = 1, mayLoad = 0 in {
1604 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1605 RegisterClass regClass> : MTBUF_m <
1607 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1608 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
1609 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1610 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1611 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1614 } // mayStore = 1, mayLoad = 0
1616 let mayLoad = 1, mayStore = 0 in {
1618 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1619 RegisterClass regClass> : MTBUF_m <
1620 op, opName, (outs regClass:$dst),
1621 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1622 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
1623 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1624 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1625 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1628 } // mayLoad = 1, mayStore = 0
1630 //===----------------------------------------------------------------------===//
1632 //===----------------------------------------------------------------------===//
1634 class mubuf <bits<7> si, bits<7> vi = si> {
1635 field bits<7> SI = si;
1636 field bits<7> VI = vi;
1639 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1640 bit IsAddr64 = is_addr64;
1641 string OpName = NAME # suffix;
1644 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1645 MUBUF <outs, ins, "", pattern>,
1646 SIMCInstr<opName, SISubtarget.NONE> {
1649 // dummy fields, so that we can use let statements around multiclasses
1659 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
1661 MUBUF <outs, ins, asm, []>,
1663 SIMCInstr<opName, SISubtarget.SI> {
1667 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
1669 MUBUF <outs, ins, asm, []>,
1671 SIMCInstr<opName, SISubtarget.VI> {
1675 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
1676 list<dag> pattern> {
1678 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1679 MUBUFAddr64Table <0>;
1682 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1685 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1688 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
1689 dag ins, string asm, list<dag> pattern> {
1691 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1692 MUBUFAddr64Table <1>;
1695 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1698 // There is no VI version. If the pseudo is selected, it should be lowered
1699 // for VI appropriately.
1702 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1703 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1707 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
1708 string asm, list<dag> pattern, bit is_return> {
1710 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1711 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
1712 AtomicNoRet<NAME#"_OFFSET", is_return>;
1714 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
1716 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1719 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1723 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
1724 string asm, list<dag> pattern, bit is_return> {
1726 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1727 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
1728 AtomicNoRet<NAME#"_ADDR64", is_return>;
1730 let offen = 0, idxen = 0, addr64 = 1, tfe = 0, soffset = 128 in {
1731 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1734 // There is no VI version. If the pseudo is selected, it should be lowered
1735 // for VI appropriately.
1738 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
1739 ValueType vt, SDPatternOperator atomic> {
1741 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1743 // No return variants
1746 defm _ADDR64 : MUBUFAtomicAddr64_m <
1747 op, name#"_addr64", (outs),
1748 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1749 mbuf_offset:$offset, slc:$slc),
1750 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#"$slc", [], 0
1753 defm _OFFSET : MUBUFAtomicOffset_m <
1754 op, name#"_offset", (outs),
1755 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1756 SCSrc_32:$soffset, slc:$slc),
1757 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
1761 // Variant that return values
1762 let glc = 1, Constraints = "$vdata = $vdata_in",
1763 DisableEncoding = "$vdata_in" in {
1765 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
1766 op, name#"_rtn_addr64", (outs rc:$vdata),
1767 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1768 mbuf_offset:$offset, slc:$slc),
1769 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#" glc"#"$slc",
1771 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i16:$offset,
1772 i1:$slc), vt:$vdata_in))], 1
1775 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
1776 op, name#"_rtn_offset", (outs rc:$vdata),
1777 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1778 SCSrc_32:$soffset, slc:$slc),
1779 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1781 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1782 i1:$slc), vt:$vdata_in))], 1
1787 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1790 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
1791 ValueType load_vt = i32,
1792 SDPatternOperator ld = null_frag> {
1794 let mayLoad = 1, mayStore = 0 in {
1795 let offen = 0, idxen = 0, vaddr = 0 in {
1796 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
1797 (ins SReg_128:$srsrc,
1798 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1799 slc:$slc, tfe:$tfe),
1800 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1801 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1802 i32:$soffset, i16:$offset,
1803 i1:$glc, i1:$slc, i1:$tfe)))]>;
1806 let offen = 1, idxen = 0 in {
1807 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
1808 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1809 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1811 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1814 let offen = 0, idxen = 1 in {
1815 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
1816 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1817 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1818 slc:$slc, tfe:$tfe),
1819 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1822 let offen = 1, idxen = 1 in {
1823 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
1824 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1825 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1826 name#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1829 let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
1830 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
1831 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1832 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1833 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1834 i64:$vaddr, i16:$offset)))]>;
1839 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
1840 ValueType store_vt, SDPatternOperator st> {
1841 let mayLoad = 0, mayStore = 1 in {
1842 defm : MUBUF_m <op, name, (outs),
1843 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1844 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1846 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1847 "$glc"#"$slc"#"$tfe", []>;
1849 let offen = 0, idxen = 0, vaddr = 0 in {
1850 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
1851 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1852 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1853 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1854 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1855 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
1856 } // offen = 0, idxen = 0, vaddr = 0
1858 let offen = 1, idxen = 0 in {
1859 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
1860 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1861 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1862 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1863 "$glc"#"$slc"#"$tfe", []>;
1864 } // end offen = 1, idxen = 0
1866 let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0,
1867 soffset = 128 /* ZERO */ in {
1868 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
1869 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1870 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1871 [(st store_vt:$vdata,
1872 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>;
1874 } // End mayLoad = 0, mayStore = 1
1877 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1878 FLAT <op, (outs regClass:$data),
1879 (ins VReg_64:$addr),
1880 asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
1887 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1888 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1889 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1901 class MIMG_Mask <string op, int channels> {
1903 int Channels = channels;
1906 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1907 RegisterClass dst_rc,
1908 RegisterClass src_rc> : MIMG <
1910 (outs dst_rc:$vdata),
1911 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1912 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1914 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1915 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1920 let hasPostISelHook = 1;
1923 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1924 RegisterClass dst_rc,
1926 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
1927 MIMG_Mask<asm#"_V1", channels>;
1928 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1929 MIMG_Mask<asm#"_V2", channels>;
1930 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1931 MIMG_Mask<asm#"_V4", channels>;
1934 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1935 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
1936 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1937 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1938 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1941 class MIMG_Sampler_Helper <bits<7> op, string asm,
1942 RegisterClass dst_rc,
1943 RegisterClass src_rc> : MIMG <
1945 (outs dst_rc:$vdata),
1946 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1947 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1948 SReg_256:$srsrc, SReg_128:$ssamp),
1949 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1950 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1954 let hasPostISelHook = 1;
1957 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1958 RegisterClass dst_rc,
1960 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32>,
1961 MIMG_Mask<asm#"_V1", channels>;
1962 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1963 MIMG_Mask<asm#"_V2", channels>;
1964 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1965 MIMG_Mask<asm#"_V4", channels>;
1966 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1967 MIMG_Mask<asm#"_V8", channels>;
1968 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1969 MIMG_Mask<asm#"_V16", channels>;
1972 multiclass MIMG_Sampler <bits<7> op, string asm> {
1973 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1>;
1974 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1975 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1976 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1979 class MIMG_Gather_Helper <bits<7> op, string asm,
1980 RegisterClass dst_rc,
1981 RegisterClass src_rc> : MIMG <
1983 (outs dst_rc:$vdata),
1984 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1985 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1986 SReg_256:$srsrc, SReg_128:$ssamp),
1987 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1988 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1993 // DMASK was repurposed for GATHER4. 4 components are always
1994 // returned and DMASK works like a swizzle - it selects
1995 // the component to fetch. The only useful DMASK values are
1996 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1997 // (red,red,red,red) etc.) The ISA document doesn't mention
1999 // Therefore, disable all code which updates DMASK by setting these two:
2001 let hasPostISelHook = 0;
2004 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2005 RegisterClass dst_rc,
2007 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32>,
2008 MIMG_Mask<asm#"_V1", channels>;
2009 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
2010 MIMG_Mask<asm#"_V2", channels>;
2011 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
2012 MIMG_Mask<asm#"_V4", channels>;
2013 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
2014 MIMG_Mask<asm#"_V8", channels>;
2015 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
2016 MIMG_Mask<asm#"_V16", channels>;
2019 multiclass MIMG_Gather <bits<7> op, string asm> {
2020 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1>;
2021 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
2022 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
2023 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
2026 //===----------------------------------------------------------------------===//
2027 // Vector instruction mappings
2028 //===----------------------------------------------------------------------===//
2030 // Maps an opcode in e32 form to its e64 equivalent
2031 def getVOPe64 : InstrMapping {
2032 let FilterClass = "VOP";
2033 let RowFields = ["OpName"];
2034 let ColFields = ["Size"];
2036 let ValueCols = [["8"]];
2039 // Maps an opcode in e64 form to its e32 equivalent
2040 def getVOPe32 : InstrMapping {
2041 let FilterClass = "VOP";
2042 let RowFields = ["OpName"];
2043 let ColFields = ["Size"];
2045 let ValueCols = [["4"]];
2048 // Maps an original opcode to its commuted version
2049 def getCommuteRev : InstrMapping {
2050 let FilterClass = "VOP2_REV";
2051 let RowFields = ["RevOp"];
2052 let ColFields = ["IsOrig"];
2054 let ValueCols = [["0"]];
2057 def getMaskedMIMGOp : InstrMapping {
2058 let FilterClass = "MIMG_Mask";
2059 let RowFields = ["Op"];
2060 let ColFields = ["Channels"];
2062 let ValueCols = [["1"], ["2"], ["3"] ];
2065 // Maps an commuted opcode to its original version
2066 def getCommuteOrig : InstrMapping {
2067 let FilterClass = "VOP2_REV";
2068 let RowFields = ["RevOp"];
2069 let ColFields = ["IsOrig"];
2071 let ValueCols = [["1"]];
2074 def getMCOpcodeGen : InstrMapping {
2075 let FilterClass = "SIMCInstr";
2076 let RowFields = ["PseudoInstr"];
2077 let ColFields = ["Subtarget"];
2078 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2079 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2082 def getAddr64Inst : InstrMapping {
2083 let FilterClass = "MUBUFAddr64Table";
2084 let RowFields = ["OpName"];
2085 let ColFields = ["IsAddr64"];
2087 let ValueCols = [["1"]];
2090 // Maps an atomic opcode to its version with a return value.
2091 def getAtomicRetOp : InstrMapping {
2092 let FilterClass = "AtomicNoRet";
2093 let RowFields = ["NoRetOp"];
2094 let ColFields = ["IsRet"];
2096 let ValueCols = [["1"]];
2099 // Maps an atomic opcode to its returnless version.
2100 def getAtomicNoRetOp : InstrMapping {
2101 let FilterClass = "AtomicNoRet";
2102 let RowFields = ["NoRetOp"];
2103 let ColFields = ["IsRet"];
2105 let ValueCols = [["0"]];
2108 include "SIInstructions.td"
2109 include "CIInstructions.td"
2110 include "VIInstructions.td"