1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
11 // in AMDGPUMCInstLower.h
17 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
21 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
22 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
23 [SDNPMayLoad, SDNPMemOperand]
26 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
28 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
29 SDTCisVT<1, iAny>, // vdata(VGPR)
30 SDTCisVT<2, i32>, // num_channels(imm)
31 SDTCisVT<3, i32>, // vaddr(VGPR)
32 SDTCisVT<4, i32>, // soffset(SGPR)
33 SDTCisVT<5, i32>, // inst_offset(imm)
34 SDTCisVT<6, i32>, // dfmt(imm)
35 SDTCisVT<7, i32>, // nfmt(imm)
36 SDTCisVT<8, i32>, // offen(imm)
37 SDTCisVT<9, i32>, // idxen(imm)
38 SDTCisVT<10, i32>, // glc(imm)
39 SDTCisVT<11, i32>, // slc(imm)
40 SDTCisVT<12, i32> // tfe(imm)
42 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
45 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
46 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
50 class SDSample<string opcode> : SDNode <opcode,
51 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
52 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
55 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
56 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
57 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
58 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
60 def SIconstdata_ptr : SDNode<
61 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
64 // Transformation function, extract the lower 32bit of a 64bit immediate
65 def LO32 : SDNodeXForm<imm, [{
66 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
69 def LO32f : SDNodeXForm<fpimm, [{
70 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
71 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
74 // Transformation function, extract the upper 32bit of a 64bit immediate
75 def HI32 : SDNodeXForm<imm, [{
76 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
79 def HI32f : SDNodeXForm<fpimm, [{
80 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
81 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
84 def IMM8bitDWORD : PatLeaf <(imm),
85 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
88 def as_dword_i32imm : SDNodeXForm<imm, [{
89 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
92 def as_i1imm : SDNodeXForm<imm, [{
93 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
96 def as_i8imm : SDNodeXForm<imm, [{
97 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
100 def as_i16imm : SDNodeXForm<imm, [{
101 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
104 def as_i32imm: SDNodeXForm<imm, [{
105 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
108 def IMM8bit : PatLeaf <(imm),
109 [{return isUInt<8>(N->getZExtValue());}]
112 def IMM12bit : PatLeaf <(imm),
113 [{return isUInt<12>(N->getZExtValue());}]
116 def IMM16bit : PatLeaf <(imm),
117 [{return isUInt<16>(N->getZExtValue());}]
120 def IMM32bit : PatLeaf <(imm),
121 [{return isUInt<32>(N->getZExtValue());}]
124 def mubuf_vaddr_offset : PatFrag<
125 (ops node:$ptr, node:$offset, node:$imm_offset),
126 (add (add node:$ptr, node:$offset), node:$imm_offset)
129 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
130 return isInlineImmediate(N);
133 class SGPRImm <dag frag> : PatLeaf<frag, [{
134 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
135 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
138 const SIRegisterInfo *SIRI =
139 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
140 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
142 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
149 //===----------------------------------------------------------------------===//
151 //===----------------------------------------------------------------------===//
153 def FRAMEri32 : Operand<iPTR> {
154 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
157 def sopp_brtarget : Operand<OtherVT> {
158 let EncoderMethod = "getSOPPBrEncoding";
159 let OperandType = "OPERAND_PCREL";
162 include "SIInstrFormats.td"
164 let OperandType = "OPERAND_IMMEDIATE" in {
166 def offen : Operand<i1> {
167 let PrintMethod = "printOffen";
169 def idxen : Operand<i1> {
170 let PrintMethod = "printIdxen";
172 def addr64 : Operand<i1> {
173 let PrintMethod = "printAddr64";
175 def mbuf_offset : Operand<i16> {
176 let PrintMethod = "printMBUFOffset";
178 def glc : Operand <i1> {
179 let PrintMethod = "printGLC";
181 def slc : Operand <i1> {
182 let PrintMethod = "printSLC";
184 def tfe : Operand <i1> {
185 let PrintMethod = "printTFE";
188 } // End OperandType = "OPERAND_IMMEDIATE"
190 //===----------------------------------------------------------------------===//
192 //===----------------------------------------------------------------------===//
194 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
196 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
197 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
198 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
199 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
201 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
202 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
204 //===----------------------------------------------------------------------===//
205 // SI assembler operands
206 //===----------------------------------------------------------------------===//
225 //===----------------------------------------------------------------------===//
227 // SI Instruction multiclass helpers.
229 // Instructions with _32 take 32-bit operands.
230 // Instructions with _64 take 64-bit operands.
232 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
233 // encoding is the standard encoding, but instruction that make use of
234 // any of the instruction modifiers must use the 64-bit encoding.
236 // Instructions with _e32 use the 32-bit encoding.
237 // Instructions with _e64 use the 64-bit encoding.
239 //===----------------------------------------------------------------------===//
241 //===----------------------------------------------------------------------===//
243 //===----------------------------------------------------------------------===//
245 class SOP1_32 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
246 op, (outs SReg_32:$dst), (ins SSrc_32:$src0),
247 opName#" $dst, $src0", pattern
250 class SOP1_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
251 op, (outs SReg_64:$dst), (ins SSrc_64:$src0),
252 opName#" $dst, $src0", pattern
255 // 64-bit input, 32-bit output.
256 class SOP1_32_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
257 op, (outs SReg_32:$dst), (ins SSrc_64:$src0),
258 opName#" $dst, $src0", pattern
261 class SOP2_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
262 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
263 opName#" $dst, $src0, $src1", pattern
266 class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
267 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
268 opName#" $dst, $src0, $src1", pattern
271 class SOP2_SHIFT_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
272 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
273 opName#" $dst, $src0, $src1", pattern
277 class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
278 string opName, PatLeaf cond> : SOPC <
279 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
280 opName#" $dst, $src0, $src1", []>;
282 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
283 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
285 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
286 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
288 class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
289 op, (outs SReg_32:$dst), (ins i16imm:$src0),
290 opName#" $dst, $src0", pattern
293 class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
294 op, (outs SReg_64:$dst), (ins i16imm:$src0),
295 opName#" $dst, $src0", pattern
298 multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass baseClass,
299 RegisterClass dstClass> {
301 op, 1, (outs dstClass:$dst),
302 (ins baseClass:$sbase, u32imm:$offset),
303 asm#" $dst, $sbase, $offset", []
307 op, 0, (outs dstClass:$dst),
308 (ins baseClass:$sbase, SReg_32:$soff),
309 asm#" $dst, $sbase, $soff", []
313 //===----------------------------------------------------------------------===//
314 // Vector ALU classes
315 //===----------------------------------------------------------------------===//
317 // This must always be right before the operand being input modified.
318 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
319 let PrintMethod = "printOperandAndMods";
321 def InputModsNoDefault : Operand <i32> {
322 let PrintMethod = "printOperandAndMods";
325 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
327 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
328 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
332 // Returns the register class to use for the destination of VOP[123C]
333 // instructions for the given VT.
334 class getVALUDstForVT<ValueType VT> {
335 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
338 // Returns the register class to use for source 0 of VOP[12C]
339 // instructions for the given VT.
340 class getVOPSrc0ForVT<ValueType VT> {
341 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
344 // Returns the register class to use for source 1 of VOP[12C] for the
346 class getVOPSrc1ForVT<ValueType VT> {
347 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
350 // Returns the register classes for the source arguments of a VOP[12C]
351 // instruction for the given SrcVTs.
352 class getInRC32 <list<ValueType> SrcVT> {
353 list<RegisterClass> ret = [
354 getVOPSrc0ForVT<SrcVT[0]>.ret,
355 getVOPSrc1ForVT<SrcVT[1]>.ret
359 // Returns the register class to use for sources of VOP3 instructions for the
361 class getVOP3SrcForVT<ValueType VT> {
362 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
365 // Returns the register classes for the source arguments of a VOP3
366 // instruction for the given SrcVTs.
367 class getInRC64 <list<ValueType> SrcVT> {
368 list<RegisterClass> ret = [
369 getVOP3SrcForVT<SrcVT[0]>.ret,
370 getVOP3SrcForVT<SrcVT[1]>.ret,
371 getVOP3SrcForVT<SrcVT[2]>.ret
375 // Returns 1 if the source arguments have modifiers, 0 if they do not.
376 class hasModifiers<ValueType SrcVT> {
377 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
378 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
381 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
382 class getIns32 <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
383 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
384 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
388 // Returns the input arguments for VOP3 instructions for the given SrcVT.
389 class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC,
390 RegisterClass Src2RC, int NumSrcArgs,
394 !if (!eq(NumSrcArgs, 1),
395 !if (!eq(HasModifiers, 1),
396 // VOP1 with modifiers
397 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
398 i32imm:$clamp, i32imm:$omod)
400 // VOP1 without modifiers
403 !if (!eq(NumSrcArgs, 2),
404 !if (!eq(HasModifiers, 1),
405 // VOP 2 with modifiers
406 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
407 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
408 i32imm:$clamp, i32imm:$omod)
410 // VOP2 without modifiers
411 (ins Src0RC:$src0, Src1RC:$src1)
413 /* NumSrcArgs == 3 */,
414 !if (!eq(HasModifiers, 1),
415 // VOP3 with modifiers
416 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
417 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
418 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
419 i32imm:$clamp, i32imm:$omod)
421 // VOP3 without modifiers
422 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
426 // Returns the assembly string for the inputs and outputs of a VOP[12C]
427 // instruction. This does not add the _e32 suffix, so it can be reused
429 class getAsm32 <int NumSrcArgs> {
430 string src1 = ", $src1";
431 string src2 = ", $src2";
432 string ret = " $dst, $src0"#
433 !if(!eq(NumSrcArgs, 1), "", src1)#
434 !if(!eq(NumSrcArgs, 3), src2, "");
437 // Returns the assembly string for the inputs and outputs of a VOP3
439 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
440 string src0 = "$src0_modifiers,";
441 string src1 = !if(!eq(NumSrcArgs, 1), "", " $src1_modifiers,");
442 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers,", "");
444 !if(!eq(HasModifiers, 0),
445 getAsm32<NumSrcArgs>.ret,
446 " $dst, "#src0#src1#src2#" $clamp, $omod");
450 class VOPProfile <list<ValueType> _ArgVT> {
452 field list<ValueType> ArgVT = _ArgVT;
454 field ValueType DstVT = ArgVT[0];
455 field ValueType Src0VT = ArgVT[1];
456 field ValueType Src1VT = ArgVT[2];
457 field ValueType Src2VT = ArgVT[3];
458 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
459 field RegisterClass Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
460 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
461 field RegisterClass Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
462 field RegisterClass Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
463 field RegisterClass Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
465 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
466 field bit HasModifiers = hasModifiers<Src0VT>.ret;
468 field dag Outs = (outs DstRC:$dst);
470 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
471 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
474 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
475 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
478 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
479 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
480 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
481 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
482 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
483 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
484 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
485 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
486 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
488 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
489 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
490 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
491 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
492 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
493 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
494 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
495 let Src0RC32 = VReg_32;
497 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
498 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
500 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
501 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
502 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
503 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
506 class VOP <string opName> {
507 string OpName = opName;
510 class VOP2_REV <string revOp, bit isOrig> {
511 string RevOp = revOp;
515 class SIMCInstr <string pseudo, int subtarget> {
516 string PseudoInstr = pseudo;
517 int Subtarget = subtarget;
520 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
522 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
523 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
524 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
525 bits<2> omod = !if(HasModifiers, ?, 0);
526 bits<1> clamp = !if(HasModifiers, ?, 0);
527 bits<9> src1 = !if(HasSrc1, ?, 0);
528 bits<9> src2 = !if(HasSrc2, ?, 0);
531 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
532 VOP3Common <outs, ins, "", pattern>,
534 SIMCInstr<opName, SISubtarget.NONE> {
538 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
539 VOP3 <op, outs, ins, asm, []>,
540 SIMCInstr<opName, SISubtarget.SI>;
542 multiclass VOP3_m <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern,
543 string opName, int NumSrcArgs, bit HasMods = 1> {
545 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
547 def _si : VOP3_Real_si <op, outs, ins, asm, opName>,
548 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
549 !if(!eq(NumSrcArgs, 2), 0, 1),
554 multiclass VOP3_1_m <bits<8> op, dag outs, dag ins, string asm,
555 list<dag> pattern, string opName, bit HasMods = 1> {
557 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
559 def _si : VOP3_Real_si <
560 {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
561 outs, ins, asm, opName>,
562 VOP3DisableFields<0, 0, HasMods>;
565 multiclass VOP3_2_m <bits<9> op, dag outs, dag ins, string asm,
566 list<dag> pattern, string opName, string revOp,
567 bit HasMods = 1, bit UseFullOp = 0> {
569 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
570 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
572 def _si : VOP3_Real_si <op,
573 outs, ins, asm, opName>,
574 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>,
575 VOP3DisableFields<1, 0, HasMods>;
578 multiclass VOP3b_2_m <bits<9> op, dag outs, dag ins, string asm,
579 list<dag> pattern, string opName, string revOp,
580 bit HasMods = 1, bit UseFullOp = 0> {
581 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
582 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
584 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
585 // can write it into any SGPR. We currently don't use the carry out,
586 // so for now hardcode it to VCC as well.
587 let sdst = SIOperand.VCC, Defs = [VCC] in {
588 def _si : VOP3b <op, outs, ins, asm, pattern>,
589 VOP3DisableFields<1, 0, HasMods>,
590 SIMCInstr<opName, SISubtarget.SI>,
591 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
592 } // End sdst = SIOperand.VCC, Defs = [VCC]
595 multiclass VOP3_C_m <bits<8> op, dag outs, dag ins, string asm,
596 list<dag> pattern, string opName,
597 bit HasMods, bit defExec> {
599 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
601 def _si : VOP3_Real_si <
602 {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
603 outs, ins, asm, opName>,
604 VOP3DisableFields<1, 0, HasMods> {
605 let Defs = !if(defExec, [EXEC], []);
609 multiclass VOP1_Helper <bits<8> op, string opName, dag outs,
610 dag ins32, string asm32, list<dag> pat32,
611 dag ins64, string asm64, list<dag> pat64,
614 def _e32 : VOP1 <op, outs, ins32, opName#asm32, pat32>, VOP<opName>;
616 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
619 multiclass VOP1Inst <bits<8> op, string opName, VOPProfile P,
620 SDPatternOperator node = null_frag> : VOP1_Helper <
622 P.Ins32, P.Asm32, [],
625 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
626 i32:$src0_modifiers, i32:$clamp, i32:$omod))))],
627 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
631 class VOP2_e32 <bits<6> op, string opName, dag outs, dag ins, string asm,
632 list<dag> pattern, string revOp> :
633 VOP2 <op, outs, ins, opName#asm, pattern>,
635 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
637 multiclass VOP2_Helper <bits<6> op, string opName, dag outs,
638 dag ins32, string asm32, list<dag> pat32,
639 dag ins64, string asm64, list<dag> pat64,
640 string revOp, bit HasMods> {
641 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
643 defm _e64 : VOP3_2_m <
644 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
645 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
649 multiclass VOP2Inst <bits<6> op, string opName, VOPProfile P,
650 SDPatternOperator node = null_frag,
651 string revOp = opName> : VOP2_Helper <
653 P.Ins32, P.Asm32, [],
657 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
658 i32:$clamp, i32:$omod)),
659 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
660 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
661 revOp, P.HasModifiers
664 multiclass VOP2b_Helper <bits<6> op, string opName, dag outs,
665 dag ins32, string asm32, list<dag> pat32,
666 dag ins64, string asm64, list<dag> pat64,
667 string revOp, bit HasMods> {
669 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
671 defm _e64 : VOP3b_2_m <
672 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
673 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
677 multiclass VOP2bInst <bits<6> op, string opName, VOPProfile P,
678 SDPatternOperator node = null_frag,
679 string revOp = opName> : VOP2b_Helper <
681 P.Ins32, P.Asm32, [],
685 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
686 i32:$clamp, i32:$omod)),
687 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
688 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
689 revOp, P.HasModifiers
692 multiclass VOPC_Helper <bits<8> op, string opName,
693 dag ins32, string asm32, list<dag> pat32,
694 dag out64, dag ins64, string asm64, list<dag> pat64,
695 bit HasMods, bit DefExec> {
696 def _e32 : VOPC <op, ins32, opName#asm32, pat32>, VOP <opName> {
697 let Defs = !if(DefExec, [EXEC], []);
700 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64, opName,
704 multiclass VOPCInst <bits<8> op, string opName,
705 VOPProfile P, PatLeaf cond = COND_NULL,
706 bit DefExec = 0> : VOPC_Helper <
708 P.Ins32, P.Asm32, [],
709 (outs SReg_64:$dst), P.Ins64, P.Asm64,
712 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
713 i32:$clamp, i32:$omod)),
714 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
716 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
717 P.HasModifiers, DefExec
720 multiclass VOPC_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
721 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
723 multiclass VOPC_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
724 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
726 multiclass VOPC_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
727 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
729 multiclass VOPC_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
730 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
733 multiclass VOPCX <bits<8> op, string opName, VOPProfile P,
734 PatLeaf cond = COND_NULL>
735 : VOPCInst <op, opName, P, cond, 1>;
737 multiclass VOPCX_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
738 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
740 multiclass VOPCX_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
741 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
743 multiclass VOPCX_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
744 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
746 multiclass VOPCX_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
747 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
749 multiclass VOP3_Helper <bits<9> op, string opName, dag outs, dag ins, string asm,
750 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
751 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
754 multiclass VOP3Inst <bits<9> op, string opName, VOPProfile P,
755 SDPatternOperator node = null_frag> : VOP3_Helper <
756 op, opName, P.Outs, P.Ins64, P.Asm64,
757 !if(!eq(P.NumSrcArgs, 3),
760 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
761 i32:$clamp, i32:$omod)),
762 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
763 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
764 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
766 !if(!eq(P.NumSrcArgs, 2),
769 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
770 i32:$clamp, i32:$omod)),
771 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
772 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
773 /* P.NumSrcArgs == 1 */,
776 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
777 i32:$clamp, i32:$omod))))],
778 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
779 P.NumSrcArgs, P.HasModifiers
782 multiclass VOP3b_Helper <bits<9> op, RegisterClass vrc, RegisterClass arc,
783 string opName, list<dag> pattern> :
785 op, (outs vrc:$dst0, SReg_64:$dst1),
786 (ins arc:$src0, arc:$src1, arc:$src2,
787 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
788 opName#" $dst0, $dst1, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern,
792 multiclass VOP3b_64 <bits<9> op, string opName, list<dag> pattern> :
793 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
795 multiclass VOP3b_32 <bits<9> op, string opName, list<dag> pattern> :
796 VOP3b_Helper <op, VReg_32, VSrc_32, opName, pattern>;
798 //===----------------------------------------------------------------------===//
799 // Vector I/O classes
800 //===----------------------------------------------------------------------===//
802 class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
803 DS <op, outs, ins, asm, pat> {
806 // Single load interpret the 2 i8imm operands as a single i16 offset.
807 let offset0 = offset{7-0};
808 let offset1 = offset{15-8};
811 class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
813 (outs regClass:$vdst),
814 (ins i1imm:$gds, VReg_32:$addr, u16imm:$offset),
815 asm#" $vdst, $addr, $offset, [M0]",
823 class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
825 (outs regClass:$vdst),
826 (ins i1imm:$gds, VReg_32:$addr, u8imm:$offset0, u8imm:$offset1),
827 asm#" $vdst, $addr, $offset0, $offset1, [M0]",
835 class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
838 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, u16imm:$offset),
839 asm#" $addr, $data0, $offset [M0]",
847 class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
850 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, regClass:$data1,
851 u8imm:$offset0, u8imm:$offset1),
852 asm#" $addr, $data0, $data1, $offset0, $offset1 [M0]",
859 // 1 address, 1 data.
860 class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
863 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
864 asm#" $vdst, $addr, $data0, $offset, [M0]",
872 // 1 address, 2 data.
873 class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
876 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
877 asm#" $vdst, $addr, $data0, $data1, $offset, [M0]",
883 // 1 address, 2 data.
884 class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
887 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
888 asm#" $addr, $data0, $data1, $offset, [M0]",
894 // 1 address, 1 data.
895 class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
898 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
899 asm#" $addr, $data0, $offset, [M0]",
907 class MUBUFAddr64Table <bit is_addr64> {
909 bit IsAddr64 = is_addr64;
912 class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
915 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
916 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
917 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
918 asm#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
919 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
925 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
926 ValueType load_vt = i32,
927 SDPatternOperator ld = null_frag> {
929 let lds = 0, mayLoad = 1 in {
933 let offen = 0, idxen = 0, vaddr = 0 in {
934 def _OFFSET : MUBUF <op, (outs regClass:$vdata),
935 (ins SReg_128:$srsrc,
936 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
938 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
939 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
940 i32:$soffset, i16:$offset,
941 i1:$glc, i1:$slc, i1:$tfe)))]>,
945 let offen = 1, idxen = 0 in {
946 def _OFFEN : MUBUF <op, (outs regClass:$vdata),
947 (ins SReg_128:$srsrc, VReg_32:$vaddr,
948 SSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
950 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
953 let offen = 0, idxen = 1 in {
954 def _IDXEN : MUBUF <op, (outs regClass:$vdata),
955 (ins SReg_128:$srsrc, VReg_32:$vaddr,
956 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
958 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
961 let offen = 1, idxen = 1 in {
962 def _BOTHEN : MUBUF <op, (outs regClass:$vdata),
963 (ins SReg_128:$srsrc, VReg_64:$vaddr,
964 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
965 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
969 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
970 def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
971 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
972 asm#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
973 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
974 i64:$vaddr, i16:$offset)))]>, MUBUFAddr64Table<1>;
979 multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
980 ValueType store_vt, SDPatternOperator st> {
982 let addr64 = 0, lds = 0 in {
986 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
987 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
989 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
990 "$glc"#"$slc"#"$tfe",
994 let offen = 0, idxen = 0, vaddr = 0 in {
995 def _OFFSET : MUBUF <
997 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
998 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
999 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1000 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1001 i16:$offset, i1:$glc, i1:$slc,
1003 >, MUBUFAddr64Table<0>;
1004 } // offen = 0, idxen = 0, vaddr = 0
1006 let offen = 1, idxen = 0 in {
1007 def _OFFEN : MUBUF <
1009 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1010 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1011 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1012 "$glc"#"$slc"#"$tfe",
1015 } // end offen = 1, idxen = 0
1017 } // End addr64 = 0, lds = 0
1019 def _ADDR64 : MUBUF <
1021 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1022 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1023 [(st store_vt:$vdata,
1024 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>, MUBUFAddr64Table<1>
1038 let soffset = 128; // ZERO
1042 class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
1044 (outs regClass:$dst),
1045 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1046 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
1047 i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1048 asm#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1049 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
1055 class MIMG_Mask <string op, int channels> {
1057 int Channels = channels;
1060 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1061 RegisterClass dst_rc,
1062 RegisterClass src_rc> : MIMG <
1064 (outs dst_rc:$vdata),
1065 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1066 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1068 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1069 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1074 let hasPostISelHook = 1;
1077 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1078 RegisterClass dst_rc,
1080 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_32>,
1081 MIMG_Mask<asm#"_V1", channels>;
1082 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1083 MIMG_Mask<asm#"_V2", channels>;
1084 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1085 MIMG_Mask<asm#"_V4", channels>;
1088 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1089 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VReg_32, 1>;
1090 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1091 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1092 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1095 class MIMG_Sampler_Helper <bits<7> op, string asm,
1096 RegisterClass dst_rc,
1097 RegisterClass src_rc> : MIMG <
1099 (outs dst_rc:$vdata),
1100 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1101 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1102 SReg_256:$srsrc, SReg_128:$ssamp),
1103 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1104 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1108 let hasPostISelHook = 1;
1111 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1112 RegisterClass dst_rc,
1114 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_32>,
1115 MIMG_Mask<asm#"_V1", channels>;
1116 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1117 MIMG_Mask<asm#"_V2", channels>;
1118 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1119 MIMG_Mask<asm#"_V4", channels>;
1120 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1121 MIMG_Mask<asm#"_V8", channels>;
1122 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1123 MIMG_Mask<asm#"_V16", channels>;
1126 multiclass MIMG_Sampler <bits<7> op, string asm> {
1127 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VReg_32, 1>;
1128 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1129 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1130 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1133 class MIMG_Gather_Helper <bits<7> op, string asm,
1134 RegisterClass dst_rc,
1135 RegisterClass src_rc> : MIMG <
1137 (outs dst_rc:$vdata),
1138 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1139 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1140 SReg_256:$srsrc, SReg_128:$ssamp),
1141 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1142 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1147 // DMASK was repurposed for GATHER4. 4 components are always
1148 // returned and DMASK works like a swizzle - it selects
1149 // the component to fetch. The only useful DMASK values are
1150 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1151 // (red,red,red,red) etc.) The ISA document doesn't mention
1153 // Therefore, disable all code which updates DMASK by setting these two:
1155 let hasPostISelHook = 0;
1158 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1159 RegisterClass dst_rc,
1161 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_32>,
1162 MIMG_Mask<asm#"_V1", channels>;
1163 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1164 MIMG_Mask<asm#"_V2", channels>;
1165 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1166 MIMG_Mask<asm#"_V4", channels>;
1167 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1168 MIMG_Mask<asm#"_V8", channels>;
1169 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1170 MIMG_Mask<asm#"_V16", channels>;
1173 multiclass MIMG_Gather <bits<7> op, string asm> {
1174 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VReg_32, 1>;
1175 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
1176 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
1177 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
1180 //===----------------------------------------------------------------------===//
1181 // Vector instruction mappings
1182 //===----------------------------------------------------------------------===//
1184 // Maps an opcode in e32 form to its e64 equivalent
1185 def getVOPe64 : InstrMapping {
1186 let FilterClass = "VOP";
1187 let RowFields = ["OpName"];
1188 let ColFields = ["Size"];
1190 let ValueCols = [["8"]];
1193 // Maps an opcode in e64 form to its e32 equivalent
1194 def getVOPe32 : InstrMapping {
1195 let FilterClass = "VOP";
1196 let RowFields = ["OpName"];
1197 let ColFields = ["Size"];
1199 let ValueCols = [["4"]];
1202 // Maps an original opcode to its commuted version
1203 def getCommuteRev : InstrMapping {
1204 let FilterClass = "VOP2_REV";
1205 let RowFields = ["RevOp"];
1206 let ColFields = ["IsOrig"];
1208 let ValueCols = [["0"]];
1211 def getMaskedMIMGOp : InstrMapping {
1212 let FilterClass = "MIMG_Mask";
1213 let RowFields = ["Op"];
1214 let ColFields = ["Channels"];
1216 let ValueCols = [["1"], ["2"], ["3"] ];
1219 // Maps an commuted opcode to its original version
1220 def getCommuteOrig : InstrMapping {
1221 let FilterClass = "VOP2_REV";
1222 let RowFields = ["RevOp"];
1223 let ColFields = ["IsOrig"];
1225 let ValueCols = [["1"]];
1228 def isDS : InstrMapping {
1229 let FilterClass = "DS";
1230 let RowFields = ["Inst"];
1231 let ColFields = ["Size"];
1233 let ValueCols = [["8"]];
1236 def getMCOpcode : InstrMapping {
1237 let FilterClass = "SIMCInstr";
1238 let RowFields = ["PseudoInstr"];
1239 let ColFields = ["Subtarget"];
1240 let KeyCol = [!cast<string>(SISubtarget.NONE)];
1241 let ValueCols = [[!cast<string>(SISubtarget.SI)]];
1244 def getAddr64Inst : InstrMapping {
1245 let FilterClass = "MUBUFAddr64Table";
1246 let RowFields = ["NAME"];
1247 let ColFields = ["IsAddr64"];
1249 let ValueCols = [["1"]];
1252 include "SIInstructions.td"