1 //===-- SIInstrInfo.td - SI Instruction Encodings ---------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 // SMRD takes a 64bit memory address and can only add an 32bit offset
15 def SIadd64bit32bit : SDNode<"ISD::ADD",
16 SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisVT<0, i64>, SDTCisVT<2, i32>]>
19 // Transformation function, extract the lower 32bit of a 64bit immediate
20 def LO32 : SDNodeXForm<imm, [{
21 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
24 // Transformation function, extract the upper 32bit of a 64bit immediate
25 def HI32 : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
29 def IMM8bitDWORD : ImmLeaf <
31 return (Imm & ~0x3FC) == 0;
32 }], SDNodeXForm<imm, [{
33 return CurDAG->getTargetConstant(
34 N->getZExtValue() >> 2, MVT::i32);
38 def IMM12bit : ImmLeaf <
40 [{return isUInt<12>(Imm);}]
43 class InlineImm <ValueType vt> : ImmLeaf <vt, [{
44 return -16 <= Imm && Imm <= 64;
47 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
48 AMDGPUInst<outs, ins, asm, pattern> {
50 field bits<1> VM_CNT = 0;
51 field bits<1> EXP_CNT = 0;
52 field bits<1> LGKM_CNT = 0;
54 let TSFlags{0} = VM_CNT;
55 let TSFlags{1} = EXP_CNT;
56 let TSFlags{2} = LGKM_CNT;
59 class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
60 InstSI <outs, ins, asm, pattern> {
66 class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
67 InstSI <outs, ins, asm, pattern> {
73 class SIOperand <ValueType vt, dag opInfo>: Operand <vt> {
74 let EncoderMethod = "encodeOperand";
75 let MIOperandInfo = opInfo;
78 class GPR4Align <RegisterClass rc> : Operand <vAny> {
79 let EncoderMethod = "GPR4AlignEncode";
80 let MIOperandInfo = (ops rc:$reg);
83 class GPR2Align <RegisterClass rc> : Operand <iPTR> {
84 let EncoderMethod = "GPR2AlignEncode";
85 let MIOperandInfo = (ops rc:$reg);
88 let Uses = [EXEC] in {
92 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
93 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
94 "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
109 let Inst{10} = COMPR;
112 let Inst{31-26} = 0x3e;
113 let Inst{39-32} = VSRC0;
114 let Inst{47-40} = VSRC1;
115 let Inst{55-48} = VSRC2;
116 let Inst{63-56} = VSRC3;
121 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
122 Enc64 <outs, ins, asm, pattern> {
137 let Inst{11-8} = DMASK;
138 let Inst{12} = UNORM;
144 let Inst{24-18} = op;
146 let Inst{31-26} = 0x3c;
147 let Inst{39-32} = VADDR;
148 let Inst{47-40} = VDATA;
149 let Inst{52-48} = SRSRC;
150 let Inst{57-53} = SSAMP;
156 class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
157 Enc64<outs, ins, asm, pattern> {
173 let Inst{11-0} = OFFSET;
174 let Inst{12} = OFFEN;
175 let Inst{13} = IDXEN;
177 let Inst{15} = ADDR64;
178 let Inst{18-16} = op;
179 let Inst{22-19} = DFMT;
180 let Inst{25-23} = NFMT;
181 let Inst{31-26} = 0x3a; //encoding
182 let Inst{39-32} = VADDR;
183 let Inst{47-40} = VDATA;
184 let Inst{52-48} = SRSRC;
187 let Inst{63-56} = SOFFSET;
192 let neverHasSideEffects = 1;
195 class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
196 Enc64<outs, ins, asm, pattern> {
211 let Inst{11-0} = OFFSET;
212 let Inst{12} = OFFEN;
213 let Inst{13} = IDXEN;
215 let Inst{15} = ADDR64;
217 let Inst{24-18} = op;
218 let Inst{31-26} = 0x38; //encoding
219 let Inst{39-32} = VADDR;
220 let Inst{47-40} = VDATA;
221 let Inst{52-48} = SRSRC;
224 let Inst{63-56} = SOFFSET;
229 let neverHasSideEffects = 1;
232 } // End Uses = [EXEC]
234 class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm,
235 list<dag> pattern> : Enc32<outs, ins, asm, pattern> {
241 let Inst{7-0} = OFFSET;
243 let Inst{14-9} = SBASE;
244 let Inst{21-15} = SDST;
245 let Inst{26-22} = op;
246 let Inst{31-27} = 0x18; //encoding
251 class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
252 Enc32<outs, ins, asm, pattern> {
257 let Inst{7-0} = SSRC0;
259 let Inst{22-16} = SDST;
260 let Inst{31-23} = 0x17d; //encoding;
264 let hasSideEffects = 0;
267 class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
268 Enc32 <outs, ins, asm, pattern> {
274 let Inst{7-0} = SSRC0;
275 let Inst{15-8} = SSRC1;
276 let Inst{22-16} = SDST;
277 let Inst{29-23} = op;
278 let Inst{31-30} = 0x2; // encoding
282 let hasSideEffects = 0;
285 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
286 Enc32<outs, ins, asm, pattern> {
291 let Inst{7-0} = SSRC0;
292 let Inst{15-8} = SSRC1;
293 let Inst{22-16} = op;
294 let Inst{31-23} = 0x17e;
296 let DisableEncoding = "$dst";
299 let hasSideEffects = 0;
302 class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
303 Enc32 <outs, ins , asm, pattern> {
308 let Inst{15-0} = SIMM16;
309 let Inst{22-16} = SDST;
310 let Inst{27-23} = op;
311 let Inst{31-28} = 0xb; //encoding
315 let hasSideEffects = 0;
318 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> : Enc32 <
326 let Inst{15-0} = SIMM16;
327 let Inst{22-16} = op;
328 let Inst{31-23} = 0x17f; // encoding
332 let hasSideEffects = 0;
335 let Uses = [EXEC] in {
337 class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
338 Enc32 <outs, ins, asm, pattern> {
345 let Inst{7-0} = VSRC;
346 let Inst{9-8} = ATTRCHAN;
347 let Inst{15-10} = ATTR;
348 let Inst{17-16} = op;
349 let Inst{25-18} = VDST;
350 let Inst{31-26} = 0x32; // encoding
352 let neverHasSideEffects = 1;
357 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
358 Enc32 <outs, ins, asm, pattern> {
363 let Inst{8-0} = SRC0;
365 let Inst{24-17} = VDST;
366 let Inst{31-25} = 0x3f; //encoding
370 let hasSideEffects = 0;
373 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
374 Enc32 <outs, ins, asm, pattern> {
380 let Inst{8-0} = SRC0;
381 let Inst{16-9} = VSRC1;
382 let Inst{24-17} = VDST;
383 let Inst{30-25} = op;
384 let Inst{31} = 0x0; //encoding
388 let hasSideEffects = 0;
391 class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
392 Enc64 <outs, ins, asm, pattern> {
403 let Inst{7-0} = VDST;
404 let Inst{10-8} = ABS;
405 let Inst{11} = CLAMP;
406 let Inst{25-17} = op;
407 let Inst{31-26} = 0x34; //encoding
408 let Inst{40-32} = SRC0;
409 let Inst{49-41} = SRC1;
410 let Inst{58-50} = SRC2;
411 let Inst{60-59} = OMOD;
412 let Inst{63-61} = NEG;
416 let hasSideEffects = 0;
419 class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
420 Enc64 <outs, ins, asm, pattern> {
430 let Inst{7-0} = VDST;
431 let Inst{14-8} = SDST;
432 let Inst{25-17} = op;
433 let Inst{31-26} = 0x34; //encoding
434 let Inst{40-32} = SRC0;
435 let Inst{49-41} = SRC1;
436 let Inst{58-50} = SRC2;
437 let Inst{60-59} = OMOD;
438 let Inst{63-61} = NEG;
442 let hasSideEffects = 0;
445 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
446 Enc32 <(outs VCCReg:$dst), ins, asm, pattern> {
451 let Inst{8-0} = SRC0;
452 let Inst{16-9} = VSRC1;
453 let Inst{24-17} = op;
454 let Inst{31-25} = 0x3e;
456 let DisableEncoding = "$dst";
459 let hasSideEffects = 0;
462 } // End Uses = [EXEC]
464 include "SIInstrFormats.td"
465 include "SIInstructions.td"