1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
11 // in AMDGPUMCInstLower.h
17 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
21 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
22 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
23 [SDNPMayLoad, SDNPMemOperand]
26 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
28 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
29 SDTCisVT<1, iAny>, // vdata(VGPR)
30 SDTCisVT<2, i32>, // num_channels(imm)
31 SDTCisVT<3, i32>, // vaddr(VGPR)
32 SDTCisVT<4, i32>, // soffset(SGPR)
33 SDTCisVT<5, i32>, // inst_offset(imm)
34 SDTCisVT<6, i32>, // dfmt(imm)
35 SDTCisVT<7, i32>, // nfmt(imm)
36 SDTCisVT<8, i32>, // offen(imm)
37 SDTCisVT<9, i32>, // idxen(imm)
38 SDTCisVT<10, i32>, // glc(imm)
39 SDTCisVT<11, i32>, // slc(imm)
40 SDTCisVT<12, i32> // tfe(imm)
42 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
45 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
46 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
50 class SDSample<string opcode> : SDNode <opcode,
51 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
52 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
55 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
56 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
57 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
58 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
60 def SIconstdata_ptr : SDNode<
61 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
64 // Transformation function, extract the lower 32bit of a 64bit immediate
65 def LO32 : SDNodeXForm<imm, [{
66 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
69 def LO32f : SDNodeXForm<fpimm, [{
70 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
71 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
74 // Transformation function, extract the upper 32bit of a 64bit immediate
75 def HI32 : SDNodeXForm<imm, [{
76 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
79 def HI32f : SDNodeXForm<fpimm, [{
80 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
81 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
84 def IMM8bitDWORD : PatLeaf <(imm),
85 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
88 def as_dword_i32imm : SDNodeXForm<imm, [{
89 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
92 def as_i1imm : SDNodeXForm<imm, [{
93 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
96 def as_i8imm : SDNodeXForm<imm, [{
97 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
100 def as_i16imm : SDNodeXForm<imm, [{
101 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
104 def as_i32imm: SDNodeXForm<imm, [{
105 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
108 def IMM8bit : PatLeaf <(imm),
109 [{return isUInt<8>(N->getZExtValue());}]
112 def IMM12bit : PatLeaf <(imm),
113 [{return isUInt<12>(N->getZExtValue());}]
116 def IMM16bit : PatLeaf <(imm),
117 [{return isUInt<16>(N->getZExtValue());}]
120 def IMM32bit : PatLeaf <(imm),
121 [{return isUInt<32>(N->getZExtValue());}]
124 def mubuf_vaddr_offset : PatFrag<
125 (ops node:$ptr, node:$offset, node:$imm_offset),
126 (add (add node:$ptr, node:$offset), node:$imm_offset)
129 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
130 return isInlineImmediate(N);
133 class SGPRImm <dag frag> : PatLeaf<frag, [{
134 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
135 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
138 const SIRegisterInfo *SIRI =
139 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
140 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
142 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
149 //===----------------------------------------------------------------------===//
151 //===----------------------------------------------------------------------===//
153 def FRAMEri32 : Operand<iPTR> {
154 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
157 def sopp_brtarget : Operand<OtherVT> {
158 let EncoderMethod = "getSOPPBrEncoding";
159 let OperandType = "OPERAND_PCREL";
162 include "SIInstrFormats.td"
164 let OperandType = "OPERAND_IMMEDIATE" in {
166 def offen : Operand<i1> {
167 let PrintMethod = "printOffen";
169 def idxen : Operand<i1> {
170 let PrintMethod = "printIdxen";
172 def addr64 : Operand<i1> {
173 let PrintMethod = "printAddr64";
175 def mbuf_offset : Operand<i16> {
176 let PrintMethod = "printMBUFOffset";
178 def glc : Operand <i1> {
179 let PrintMethod = "printGLC";
181 def slc : Operand <i1> {
182 let PrintMethod = "printSLC";
184 def tfe : Operand <i1> {
185 let PrintMethod = "printTFE";
188 } // End OperandType = "OPERAND_IMMEDIATE"
190 //===----------------------------------------------------------------------===//
192 //===----------------------------------------------------------------------===//
194 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
195 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
197 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
198 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
199 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
200 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
202 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
203 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
205 //===----------------------------------------------------------------------===//
206 // SI assembler operands
207 //===----------------------------------------------------------------------===//
226 //===----------------------------------------------------------------------===//
228 // SI Instruction multiclass helpers.
230 // Instructions with _32 take 32-bit operands.
231 // Instructions with _64 take 64-bit operands.
233 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
234 // encoding is the standard encoding, but instruction that make use of
235 // any of the instruction modifiers must use the 64-bit encoding.
237 // Instructions with _e32 use the 32-bit encoding.
238 // Instructions with _e64 use the 64-bit encoding.
240 //===----------------------------------------------------------------------===//
242 //===----------------------------------------------------------------------===//
244 //===----------------------------------------------------------------------===//
246 class SOP1_32 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
247 op, (outs SReg_32:$dst), (ins SSrc_32:$src0),
248 opName#" $dst, $src0", pattern
251 class SOP1_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
252 op, (outs SReg_64:$dst), (ins SSrc_64:$src0),
253 opName#" $dst, $src0", pattern
256 // 64-bit input, 32-bit output.
257 class SOP1_32_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
258 op, (outs SReg_32:$dst), (ins SSrc_64:$src0),
259 opName#" $dst, $src0", pattern
262 class SOP2_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
263 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
264 opName#" $dst, $src0, $src1", pattern
267 class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
268 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
269 opName#" $dst, $src0, $src1", pattern
272 class SOP2_SHIFT_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
273 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
274 opName#" $dst, $src0, $src1", pattern
278 class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
279 string opName, PatLeaf cond> : SOPC <
280 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
281 opName#" $dst, $src0, $src1", []>;
283 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
284 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
286 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
287 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
289 class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
290 op, (outs SReg_32:$dst), (ins i16imm:$src0),
291 opName#" $dst, $src0", pattern
294 class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
295 op, (outs SReg_64:$dst), (ins i16imm:$src0),
296 opName#" $dst, $src0", pattern
299 multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass baseClass,
300 RegisterClass dstClass> {
302 op, 1, (outs dstClass:$dst),
303 (ins baseClass:$sbase, u32imm:$offset),
304 asm#" $dst, $sbase, $offset", []
308 op, 0, (outs dstClass:$dst),
309 (ins baseClass:$sbase, SReg_32:$soff),
310 asm#" $dst, $sbase, $soff", []
314 //===----------------------------------------------------------------------===//
315 // Vector ALU classes
316 //===----------------------------------------------------------------------===//
318 // This must always be right before the operand being input modified.
319 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
320 let PrintMethod = "printOperandAndMods";
322 def InputModsNoDefault : Operand <i32> {
323 let PrintMethod = "printOperandAndMods";
326 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
328 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
329 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
333 // Returns the register class to use for the destination of VOP[123C]
334 // instructions for the given VT.
335 class getVALUDstForVT<ValueType VT> {
336 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
339 // Returns the register class to use for source 0 of VOP[12C]
340 // instructions for the given VT.
341 class getVOPSrc0ForVT<ValueType VT> {
342 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
345 // Returns the register class to use for source 1 of VOP[12C] for the
347 class getVOPSrc1ForVT<ValueType VT> {
348 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
351 // Returns the register classes for the source arguments of a VOP[12C]
352 // instruction for the given SrcVTs.
353 class getInRC32 <list<ValueType> SrcVT> {
354 list<RegisterClass> ret = [
355 getVOPSrc0ForVT<SrcVT[0]>.ret,
356 getVOPSrc1ForVT<SrcVT[1]>.ret
360 // Returns the register class to use for sources of VOP3 instructions for the
362 class getVOP3SrcForVT<ValueType VT> {
363 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
366 // Returns the register classes for the source arguments of a VOP3
367 // instruction for the given SrcVTs.
368 class getInRC64 <list<ValueType> SrcVT> {
369 list<RegisterClass> ret = [
370 getVOP3SrcForVT<SrcVT[0]>.ret,
371 getVOP3SrcForVT<SrcVT[1]>.ret,
372 getVOP3SrcForVT<SrcVT[2]>.ret
376 // Returns 1 if the source arguments have modifiers, 0 if they do not.
377 class hasModifiers<ValueType SrcVT> {
378 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
379 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
382 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
383 class getIns32 <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
384 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
385 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
389 // Returns the input arguments for VOP3 instructions for the given SrcVT.
390 class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC,
391 RegisterClass Src2RC, int NumSrcArgs,
395 !if (!eq(NumSrcArgs, 1),
396 !if (!eq(HasModifiers, 1),
397 // VOP1 with modifiers
398 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
399 i32imm:$clamp, i32imm:$omod)
401 // VOP1 without modifiers
404 !if (!eq(NumSrcArgs, 2),
405 !if (!eq(HasModifiers, 1),
406 // VOP 2 with modifiers
407 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
408 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
409 i32imm:$clamp, i32imm:$omod)
411 // VOP2 without modifiers
412 (ins Src0RC:$src0, Src1RC:$src1)
414 /* NumSrcArgs == 3 */,
415 !if (!eq(HasModifiers, 1),
416 // VOP3 with modifiers
417 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
418 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
419 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
420 i32imm:$clamp, i32imm:$omod)
422 // VOP3 without modifiers
423 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
427 // Returns the assembly string for the inputs and outputs of a VOP[12C]
428 // instruction. This does not add the _e32 suffix, so it can be reused
430 class getAsm32 <int NumSrcArgs> {
431 string src1 = ", $src1";
432 string src2 = ", $src2";
433 string ret = " $dst, $src0"#
434 !if(!eq(NumSrcArgs, 1), "", src1)#
435 !if(!eq(NumSrcArgs, 3), src2, "");
438 // Returns the assembly string for the inputs and outputs of a VOP3
440 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
441 string src0 = "$src0_modifiers,";
442 string src1 = !if(!eq(NumSrcArgs, 1), "", " $src1_modifiers,");
443 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers,", "");
445 !if(!eq(HasModifiers, 0),
446 getAsm32<NumSrcArgs>.ret,
447 " $dst, "#src0#src1#src2#" $clamp, $omod");
451 class VOPProfile <list<ValueType> _ArgVT> {
453 field list<ValueType> ArgVT = _ArgVT;
455 field ValueType DstVT = ArgVT[0];
456 field ValueType Src0VT = ArgVT[1];
457 field ValueType Src1VT = ArgVT[2];
458 field ValueType Src2VT = ArgVT[3];
459 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
460 field RegisterClass Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
461 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
462 field RegisterClass Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
463 field RegisterClass Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
464 field RegisterClass Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
466 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
467 field bit HasModifiers = hasModifiers<Src0VT>.ret;
469 field dag Outs = (outs DstRC:$dst);
471 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
472 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
475 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
476 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
479 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
480 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
481 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
482 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
483 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
484 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
485 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
486 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
487 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
489 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
490 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
491 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
492 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
493 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
494 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
495 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
496 let Src0RC32 = VReg_32;
498 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
499 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
501 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
502 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
503 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
504 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
507 class VOP <string opName> {
508 string OpName = opName;
511 class VOP2_REV <string revOp, bit isOrig> {
512 string RevOp = revOp;
516 class AtomicNoRet <string noRetOp, bit isRet> {
517 string NoRetOp = noRetOp;
521 class SIMCInstr <string pseudo, int subtarget> {
522 string PseudoInstr = pseudo;
523 int Subtarget = subtarget;
526 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
528 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
529 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
530 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
531 bits<2> omod = !if(HasModifiers, ?, 0);
532 bits<1> clamp = !if(HasModifiers, ?, 0);
533 bits<9> src1 = !if(HasSrc1, ?, 0);
534 bits<9> src2 = !if(HasSrc2, ?, 0);
537 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
538 VOP3Common <outs, ins, "", pattern>,
540 SIMCInstr<opName, SISubtarget.NONE> {
544 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
545 VOP3 <op, outs, ins, asm, []>,
546 SIMCInstr<opName, SISubtarget.SI>;
548 multiclass VOP3_m <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern,
549 string opName, int NumSrcArgs, bit HasMods = 1> {
551 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
553 def _si : VOP3_Real_si <op, outs, ins, asm, opName>,
554 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
555 !if(!eq(NumSrcArgs, 2), 0, 1),
560 multiclass VOP3_1_m <bits<8> op, dag outs, dag ins, string asm,
561 list<dag> pattern, string opName, bit HasMods = 1> {
563 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
565 def _si : VOP3_Real_si <
566 {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
567 outs, ins, asm, opName>,
568 VOP3DisableFields<0, 0, HasMods>;
571 multiclass VOP3_2_m <bits<9> op, dag outs, dag ins, string asm,
572 list<dag> pattern, string opName, string revOp,
573 bit HasMods = 1, bit UseFullOp = 0> {
575 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
576 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
578 def _si : VOP3_Real_si <op,
579 outs, ins, asm, opName>,
580 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>,
581 VOP3DisableFields<1, 0, HasMods>;
584 multiclass VOP3b_2_m <bits<9> op, dag outs, dag ins, string asm,
585 list<dag> pattern, string opName, string revOp,
586 bit HasMods = 1, bit UseFullOp = 0> {
587 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
588 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
590 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
591 // can write it into any SGPR. We currently don't use the carry out,
592 // so for now hardcode it to VCC as well.
593 let sdst = SIOperand.VCC, Defs = [VCC] in {
594 def _si : VOP3b <op, outs, ins, asm, pattern>,
595 VOP3DisableFields<1, 0, HasMods>,
596 SIMCInstr<opName, SISubtarget.SI>,
597 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
598 } // End sdst = SIOperand.VCC, Defs = [VCC]
601 multiclass VOP3_C_m <bits<8> op, dag outs, dag ins, string asm,
602 list<dag> pattern, string opName,
603 bit HasMods, bit defExec> {
605 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
607 def _si : VOP3_Real_si <
608 {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
609 outs, ins, asm, opName>,
610 VOP3DisableFields<1, 0, HasMods> {
611 let Defs = !if(defExec, [EXEC], []);
615 multiclass VOP1_Helper <bits<8> op, string opName, dag outs,
616 dag ins32, string asm32, list<dag> pat32,
617 dag ins64, string asm64, list<dag> pat64,
620 def _e32 : VOP1 <op, outs, ins32, opName#asm32, pat32>, VOP<opName>;
622 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
625 multiclass VOP1Inst <bits<8> op, string opName, VOPProfile P,
626 SDPatternOperator node = null_frag> : VOP1_Helper <
628 P.Ins32, P.Asm32, [],
631 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
632 i32:$src0_modifiers, i32:$clamp, i32:$omod))))],
633 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
637 class VOP2_e32 <bits<6> op, string opName, dag outs, dag ins, string asm,
638 list<dag> pattern, string revOp> :
639 VOP2 <op, outs, ins, opName#asm, pattern>,
641 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
643 multiclass VOP2_Helper <bits<6> op, string opName, dag outs,
644 dag ins32, string asm32, list<dag> pat32,
645 dag ins64, string asm64, list<dag> pat64,
646 string revOp, bit HasMods> {
647 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
649 defm _e64 : VOP3_2_m <
650 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
651 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
655 multiclass VOP2Inst <bits<6> op, string opName, VOPProfile P,
656 SDPatternOperator node = null_frag,
657 string revOp = opName> : VOP2_Helper <
659 P.Ins32, P.Asm32, [],
663 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
664 i32:$clamp, i32:$omod)),
665 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
666 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
667 revOp, P.HasModifiers
670 multiclass VOP2b_Helper <bits<6> op, string opName, dag outs,
671 dag ins32, string asm32, list<dag> pat32,
672 dag ins64, string asm64, list<dag> pat64,
673 string revOp, bit HasMods> {
675 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
677 defm _e64 : VOP3b_2_m <
678 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
679 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
683 multiclass VOP2bInst <bits<6> op, string opName, VOPProfile P,
684 SDPatternOperator node = null_frag,
685 string revOp = opName> : VOP2b_Helper <
687 P.Ins32, P.Asm32, [],
691 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
692 i32:$clamp, i32:$omod)),
693 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
694 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
695 revOp, P.HasModifiers
698 multiclass VOPC_Helper <bits<8> op, string opName,
699 dag ins32, string asm32, list<dag> pat32,
700 dag out64, dag ins64, string asm64, list<dag> pat64,
701 bit HasMods, bit DefExec> {
702 def _e32 : VOPC <op, ins32, opName#asm32, pat32>, VOP <opName> {
703 let Defs = !if(DefExec, [EXEC], []);
706 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64, opName,
710 multiclass VOPCInst <bits<8> op, string opName,
711 VOPProfile P, PatLeaf cond = COND_NULL,
712 bit DefExec = 0> : VOPC_Helper <
714 P.Ins32, P.Asm32, [],
715 (outs SReg_64:$dst), P.Ins64, P.Asm64,
718 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
719 i32:$clamp, i32:$omod)),
720 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
722 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
723 P.HasModifiers, DefExec
726 multiclass VOPC_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
727 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
729 multiclass VOPC_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
730 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
732 multiclass VOPC_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
733 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
735 multiclass VOPC_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
736 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
739 multiclass VOPCX <bits<8> op, string opName, VOPProfile P,
740 PatLeaf cond = COND_NULL>
741 : VOPCInst <op, opName, P, cond, 1>;
743 multiclass VOPCX_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
744 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
746 multiclass VOPCX_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
747 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
749 multiclass VOPCX_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
750 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
752 multiclass VOPCX_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
753 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
755 multiclass VOP3_Helper <bits<9> op, string opName, dag outs, dag ins, string asm,
756 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
757 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
760 multiclass VOP3Inst <bits<9> op, string opName, VOPProfile P,
761 SDPatternOperator node = null_frag> : VOP3_Helper <
762 op, opName, P.Outs, P.Ins64, P.Asm64,
763 !if(!eq(P.NumSrcArgs, 3),
766 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
767 i32:$clamp, i32:$omod)),
768 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
769 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
770 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
772 !if(!eq(P.NumSrcArgs, 2),
775 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
776 i32:$clamp, i32:$omod)),
777 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
778 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
779 /* P.NumSrcArgs == 1 */,
782 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
783 i32:$clamp, i32:$omod))))],
784 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
785 P.NumSrcArgs, P.HasModifiers
788 multiclass VOP3b_Helper <bits<9> op, RegisterClass vrc, RegisterClass arc,
789 string opName, list<dag> pattern> :
791 op, (outs vrc:$dst0, SReg_64:$dst1),
792 (ins arc:$src0, arc:$src1, arc:$src2,
793 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
794 opName#" $dst0, $dst1, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern,
798 multiclass VOP3b_64 <bits<9> op, string opName, list<dag> pattern> :
799 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
801 multiclass VOP3b_32 <bits<9> op, string opName, list<dag> pattern> :
802 VOP3b_Helper <op, VReg_32, VSrc_32, opName, pattern>;
805 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
806 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i32:$clamp, i32:$omod)),
807 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
808 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
809 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
810 i32:$src1_modifiers, P.Src1VT:$src1,
811 i32:$src2_modifiers, P.Src2VT:$src2,
815 //===----------------------------------------------------------------------===//
816 // Vector I/O classes
817 //===----------------------------------------------------------------------===//
819 class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
820 DS <op, outs, ins, asm, pat> {
823 // Single load interpret the 2 i8imm operands as a single i16 offset.
824 let offset0 = offset{7-0};
825 let offset1 = offset{15-8};
828 class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
830 (outs regClass:$vdst),
831 (ins i1imm:$gds, VReg_32:$addr, u16imm:$offset),
832 asm#" $vdst, $addr, $offset, [M0]",
840 class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
842 (outs regClass:$vdst),
843 (ins i1imm:$gds, VReg_32:$addr, u8imm:$offset0, u8imm:$offset1),
844 asm#" $vdst, $addr, $offset0, $offset1, [M0]",
852 class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
855 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, u16imm:$offset),
856 asm#" $addr, $data0, $offset [M0]",
864 class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
867 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, regClass:$data1,
868 u8imm:$offset0, u8imm:$offset1),
869 asm#" $addr, $data0, $data1, $offset0, $offset1 [M0]",
876 // 1 address, 1 data.
877 class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
880 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
881 asm#" $vdst, $addr, $data0, $offset, [M0]", []>,
882 AtomicNoRet<noRetOp, 1> {
888 let hasPostISelHook = 1; // Adjusted to no return version.
891 // 1 address, 2 data.
892 class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
895 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
896 asm#" $vdst, $addr, $data0, $data1, $offset, [M0]",
898 AtomicNoRet<noRetOp, 1> {
902 let hasPostISelHook = 1; // Adjusted to no return version.
905 // 1 address, 2 data.
906 class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
909 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
910 asm#" $addr, $data0, $data1, $offset, [M0]",
912 AtomicNoRet<noRetOp, 0> {
917 // 1 address, 1 data.
918 class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
921 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
922 asm#" $addr, $data0, $offset, [M0]",
924 AtomicNoRet<noRetOp, 0> {
931 class MUBUFAddr64Table <bit is_addr64> {
933 bit IsAddr64 = is_addr64;
936 class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
939 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
940 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
941 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
942 asm#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
943 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
949 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
950 ValueType load_vt = i32,
951 SDPatternOperator ld = null_frag> {
953 let lds = 0, mayLoad = 1 in {
957 let offen = 0, idxen = 0, vaddr = 0 in {
958 def _OFFSET : MUBUF <op, (outs regClass:$vdata),
959 (ins SReg_128:$srsrc,
960 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
962 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
963 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
964 i32:$soffset, i16:$offset,
965 i1:$glc, i1:$slc, i1:$tfe)))]>,
969 let offen = 1, idxen = 0 in {
970 def _OFFEN : MUBUF <op, (outs regClass:$vdata),
971 (ins SReg_128:$srsrc, VReg_32:$vaddr,
972 SSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
974 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
977 let offen = 0, idxen = 1 in {
978 def _IDXEN : MUBUF <op, (outs regClass:$vdata),
979 (ins SReg_128:$srsrc, VReg_32:$vaddr,
980 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
982 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
985 let offen = 1, idxen = 1 in {
986 def _BOTHEN : MUBUF <op, (outs regClass:$vdata),
987 (ins SReg_128:$srsrc, VReg_64:$vaddr,
988 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
989 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
993 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
994 def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
995 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
996 asm#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
997 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
998 i64:$vaddr, i16:$offset)))]>, MUBUFAddr64Table<1>;
1003 multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
1004 ValueType store_vt, SDPatternOperator st> {
1006 let addr64 = 0, lds = 0 in {
1010 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1011 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1013 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1014 "$glc"#"$slc"#"$tfe",
1018 let offen = 0, idxen = 0, vaddr = 0 in {
1019 def _OFFSET : MUBUF <
1021 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1022 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1023 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1024 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1025 i16:$offset, i1:$glc, i1:$slc,
1027 >, MUBUFAddr64Table<0>;
1028 } // offen = 0, idxen = 0, vaddr = 0
1030 let offen = 1, idxen = 0 in {
1031 def _OFFEN : MUBUF <
1033 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1034 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1035 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1036 "$glc"#"$slc"#"$tfe",
1039 } // end offen = 1, idxen = 0
1041 } // End addr64 = 0, lds = 0
1043 def _ADDR64 : MUBUF <
1045 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1046 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1047 [(st store_vt:$vdata,
1048 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>, MUBUFAddr64Table<1>
1062 let soffset = 128; // ZERO
1066 class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
1068 (outs regClass:$dst),
1069 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1070 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
1071 i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1072 asm#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1073 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
1079 class MIMG_Mask <string op, int channels> {
1081 int Channels = channels;
1084 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1085 RegisterClass dst_rc,
1086 RegisterClass src_rc> : MIMG <
1088 (outs dst_rc:$vdata),
1089 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1090 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1092 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1093 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1098 let hasPostISelHook = 1;
1101 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1102 RegisterClass dst_rc,
1104 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_32>,
1105 MIMG_Mask<asm#"_V1", channels>;
1106 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1107 MIMG_Mask<asm#"_V2", channels>;
1108 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1109 MIMG_Mask<asm#"_V4", channels>;
1112 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1113 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VReg_32, 1>;
1114 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1115 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1116 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1119 class MIMG_Sampler_Helper <bits<7> op, string asm,
1120 RegisterClass dst_rc,
1121 RegisterClass src_rc> : MIMG <
1123 (outs dst_rc:$vdata),
1124 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1125 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1126 SReg_256:$srsrc, SReg_128:$ssamp),
1127 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1128 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1132 let hasPostISelHook = 1;
1135 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1136 RegisterClass dst_rc,
1138 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_32>,
1139 MIMG_Mask<asm#"_V1", channels>;
1140 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1141 MIMG_Mask<asm#"_V2", channels>;
1142 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1143 MIMG_Mask<asm#"_V4", channels>;
1144 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1145 MIMG_Mask<asm#"_V8", channels>;
1146 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1147 MIMG_Mask<asm#"_V16", channels>;
1150 multiclass MIMG_Sampler <bits<7> op, string asm> {
1151 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VReg_32, 1>;
1152 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1153 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1154 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1157 class MIMG_Gather_Helper <bits<7> op, string asm,
1158 RegisterClass dst_rc,
1159 RegisterClass src_rc> : MIMG <
1161 (outs dst_rc:$vdata),
1162 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1163 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1164 SReg_256:$srsrc, SReg_128:$ssamp),
1165 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1166 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1171 // DMASK was repurposed for GATHER4. 4 components are always
1172 // returned and DMASK works like a swizzle - it selects
1173 // the component to fetch. The only useful DMASK values are
1174 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1175 // (red,red,red,red) etc.) The ISA document doesn't mention
1177 // Therefore, disable all code which updates DMASK by setting these two:
1179 let hasPostISelHook = 0;
1182 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1183 RegisterClass dst_rc,
1185 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_32>,
1186 MIMG_Mask<asm#"_V1", channels>;
1187 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1188 MIMG_Mask<asm#"_V2", channels>;
1189 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1190 MIMG_Mask<asm#"_V4", channels>;
1191 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1192 MIMG_Mask<asm#"_V8", channels>;
1193 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1194 MIMG_Mask<asm#"_V16", channels>;
1197 multiclass MIMG_Gather <bits<7> op, string asm> {
1198 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VReg_32, 1>;
1199 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
1200 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
1201 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
1204 //===----------------------------------------------------------------------===//
1205 // Vector instruction mappings
1206 //===----------------------------------------------------------------------===//
1208 // Maps an opcode in e32 form to its e64 equivalent
1209 def getVOPe64 : InstrMapping {
1210 let FilterClass = "VOP";
1211 let RowFields = ["OpName"];
1212 let ColFields = ["Size"];
1214 let ValueCols = [["8"]];
1217 // Maps an opcode in e64 form to its e32 equivalent
1218 def getVOPe32 : InstrMapping {
1219 let FilterClass = "VOP";
1220 let RowFields = ["OpName"];
1221 let ColFields = ["Size"];
1223 let ValueCols = [["4"]];
1226 // Maps an original opcode to its commuted version
1227 def getCommuteRev : InstrMapping {
1228 let FilterClass = "VOP2_REV";
1229 let RowFields = ["RevOp"];
1230 let ColFields = ["IsOrig"];
1232 let ValueCols = [["0"]];
1235 def getMaskedMIMGOp : InstrMapping {
1236 let FilterClass = "MIMG_Mask";
1237 let RowFields = ["Op"];
1238 let ColFields = ["Channels"];
1240 let ValueCols = [["1"], ["2"], ["3"] ];
1243 // Maps an commuted opcode to its original version
1244 def getCommuteOrig : InstrMapping {
1245 let FilterClass = "VOP2_REV";
1246 let RowFields = ["RevOp"];
1247 let ColFields = ["IsOrig"];
1249 let ValueCols = [["1"]];
1252 def isDS : InstrMapping {
1253 let FilterClass = "DS";
1254 let RowFields = ["Inst"];
1255 let ColFields = ["Size"];
1257 let ValueCols = [["8"]];
1260 def getMCOpcode : InstrMapping {
1261 let FilterClass = "SIMCInstr";
1262 let RowFields = ["PseudoInstr"];
1263 let ColFields = ["Subtarget"];
1264 let KeyCol = [!cast<string>(SISubtarget.NONE)];
1265 let ValueCols = [[!cast<string>(SISubtarget.SI)]];
1268 def getAddr64Inst : InstrMapping {
1269 let FilterClass = "MUBUFAddr64Table";
1270 let RowFields = ["NAME"];
1271 let ColFields = ["IsAddr64"];
1273 let ValueCols = [["1"]];
1276 // Maps an atomic opcode to its version with a return value.
1277 def getAtomicRetOp : InstrMapping {
1278 let FilterClass = "AtomicNoRet";
1279 let RowFields = ["NoRetOp"];
1280 let ColFields = ["IsRet"];
1282 let ValueCols = [["1"]];
1285 // Maps an atomic opcode to its returnless version.
1286 def getAtomicNoRetOp : InstrMapping {
1287 let FilterClass = "AtomicNoRet";
1288 let RowFields = ["NoRetOp"];
1289 let ColFields = ["IsRet"];
1291 let ValueCols = [["0"]];
1294 include "SIInstructions.td"