1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
11 // in AMDGPUMCInstLower.h
17 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
21 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
22 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
23 [SDNPMayLoad, SDNPMemOperand]
26 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
28 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
29 SDTCisVT<1, iAny>, // vdata(VGPR)
30 SDTCisVT<2, i32>, // num_channels(imm)
31 SDTCisVT<3, i32>, // vaddr(VGPR)
32 SDTCisVT<4, i32>, // soffset(SGPR)
33 SDTCisVT<5, i32>, // inst_offset(imm)
34 SDTCisVT<6, i32>, // dfmt(imm)
35 SDTCisVT<7, i32>, // nfmt(imm)
36 SDTCisVT<8, i32>, // offen(imm)
37 SDTCisVT<9, i32>, // idxen(imm)
38 SDTCisVT<10, i32>, // glc(imm)
39 SDTCisVT<11, i32>, // slc(imm)
40 SDTCisVT<12, i32> // tfe(imm)
42 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
45 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
46 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
50 class SDSample<string opcode> : SDNode <opcode,
51 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
52 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
55 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
56 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
57 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
58 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
60 def SIconstdata_ptr : SDNode<
61 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
64 // Transformation function, extract the lower 32bit of a 64bit immediate
65 def LO32 : SDNodeXForm<imm, [{
66 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
69 def LO32f : SDNodeXForm<fpimm, [{
70 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
71 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
74 // Transformation function, extract the upper 32bit of a 64bit immediate
75 def HI32 : SDNodeXForm<imm, [{
76 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
79 def HI32f : SDNodeXForm<fpimm, [{
80 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
81 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
84 def IMM8bitDWORD : PatLeaf <(imm),
85 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
88 def as_dword_i32imm : SDNodeXForm<imm, [{
89 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
92 def as_i1imm : SDNodeXForm<imm, [{
93 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
96 def as_i8imm : SDNodeXForm<imm, [{
97 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
100 def as_i16imm : SDNodeXForm<imm, [{
101 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
104 def as_i32imm: SDNodeXForm<imm, [{
105 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
108 def IMM8bit : PatLeaf <(imm),
109 [{return isUInt<8>(N->getZExtValue());}]
112 def IMM12bit : PatLeaf <(imm),
113 [{return isUInt<12>(N->getZExtValue());}]
116 def IMM16bit : PatLeaf <(imm),
117 [{return isUInt<16>(N->getZExtValue());}]
120 def IMM32bit : PatLeaf <(imm),
121 [{return isUInt<32>(N->getZExtValue());}]
124 def mubuf_vaddr_offset : PatFrag<
125 (ops node:$ptr, node:$offset, node:$imm_offset),
126 (add (add node:$ptr, node:$offset), node:$imm_offset)
129 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
130 return isInlineImmediate(N);
133 class SGPRImm <dag frag> : PatLeaf<frag, [{
134 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
135 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
138 const SIRegisterInfo *SIRI =
139 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
140 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
142 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
149 //===----------------------------------------------------------------------===//
151 //===----------------------------------------------------------------------===//
153 def FRAMEri32 : Operand<iPTR> {
154 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
157 def sopp_brtarget : Operand<OtherVT> {
158 let EncoderMethod = "getSOPPBrEncoding";
159 let OperandType = "OPERAND_PCREL";
162 include "SIInstrFormats.td"
164 let OperandType = "OPERAND_IMMEDIATE" in {
166 def offen : Operand<i1> {
167 let PrintMethod = "printOffen";
169 def idxen : Operand<i1> {
170 let PrintMethod = "printIdxen";
172 def addr64 : Operand<i1> {
173 let PrintMethod = "printAddr64";
175 def mbuf_offset : Operand<i16> {
176 let PrintMethod = "printMBUFOffset";
178 def glc : Operand <i1> {
179 let PrintMethod = "printGLC";
181 def slc : Operand <i1> {
182 let PrintMethod = "printSLC";
184 def tfe : Operand <i1> {
185 let PrintMethod = "printTFE";
188 } // End OperandType = "OPERAND_IMMEDIATE"
190 //===----------------------------------------------------------------------===//
192 //===----------------------------------------------------------------------===//
194 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
195 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
196 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
198 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
199 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
201 //===----------------------------------------------------------------------===//
202 // SI assembler operands
203 //===----------------------------------------------------------------------===//
222 //===----------------------------------------------------------------------===//
224 // SI Instruction multiclass helpers.
226 // Instructions with _32 take 32-bit operands.
227 // Instructions with _64 take 64-bit operands.
229 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
230 // encoding is the standard encoding, but instruction that make use of
231 // any of the instruction modifiers must use the 64-bit encoding.
233 // Instructions with _e32 use the 32-bit encoding.
234 // Instructions with _e64 use the 64-bit encoding.
236 //===----------------------------------------------------------------------===//
238 //===----------------------------------------------------------------------===//
240 //===----------------------------------------------------------------------===//
242 class SOP1_32 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
243 op, (outs SReg_32:$dst), (ins SSrc_32:$src0),
244 opName#" $dst, $src0", pattern
247 class SOP1_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
248 op, (outs SReg_64:$dst), (ins SSrc_64:$src0),
249 opName#" $dst, $src0", pattern
252 // 64-bit input, 32-bit output.
253 class SOP1_32_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
254 op, (outs SReg_32:$dst), (ins SSrc_64:$src0),
255 opName#" $dst, $src0", pattern
258 class SOP2_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
259 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
260 opName#" $dst, $src0, $src1", pattern
263 class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
264 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
265 opName#" $dst, $src0, $src1", pattern
268 class SOP2_SHIFT_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
269 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
270 opName#" $dst, $src0, $src1", pattern
274 class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
275 string opName, PatLeaf cond> : SOPC <
276 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
277 opName#" $dst, $src0, $src1", []>;
279 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
280 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
282 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
283 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
285 class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
286 op, (outs SReg_32:$dst), (ins i16imm:$src0),
287 opName#" $dst, $src0", pattern
290 class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
291 op, (outs SReg_64:$dst), (ins i16imm:$src0),
292 opName#" $dst, $src0", pattern
295 multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass baseClass,
296 RegisterClass dstClass> {
298 op, 1, (outs dstClass:$dst),
299 (ins baseClass:$sbase, u32imm:$offset),
300 asm#" $dst, $sbase, $offset", []
304 op, 0, (outs dstClass:$dst),
305 (ins baseClass:$sbase, SReg_32:$soff),
306 asm#" $dst, $sbase, $soff", []
310 //===----------------------------------------------------------------------===//
311 // Vector ALU classes
312 //===----------------------------------------------------------------------===//
314 // This must always be right before the operand being input modified.
315 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
316 let PrintMethod = "printOperandAndMods";
318 def InputModsNoDefault : Operand <i32> {
319 let PrintMethod = "printOperandAndMods";
322 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
324 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
325 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
329 // Returns the register class to use for the destination of VOP[123C]
330 // instructions for the given VT.
331 class getVALUDstForVT<ValueType VT> {
332 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
335 // Returns the register class to use for source 0 of VOP[12C]
336 // instructions for the given VT.
337 class getVOPSrc0ForVT<ValueType VT> {
338 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
341 // Returns the register class to use for source 1 of VOP[12C] for the
343 class getVOPSrc1ForVT<ValueType VT> {
344 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
347 // Returns the register classes for the source arguments of a VOP[12C]
348 // instruction for the given SrcVTs.
349 class getInRC32 <list<ValueType> SrcVT> {
350 list<RegisterClass> ret = [
351 getVOPSrc0ForVT<SrcVT[0]>.ret,
352 getVOPSrc1ForVT<SrcVT[1]>.ret
356 // Returns the register class to use for sources of VOP3 instructions for the
358 class getVOP3SrcForVT<ValueType VT> {
359 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
362 // Returns the register classes for the source arguments of a VOP3
363 // instruction for the given SrcVTs.
364 class getInRC64 <list<ValueType> SrcVT> {
365 list<RegisterClass> ret = [
366 getVOP3SrcForVT<SrcVT[0]>.ret,
367 getVOP3SrcForVT<SrcVT[1]>.ret,
368 getVOP3SrcForVT<SrcVT[2]>.ret
372 // Returns 1 if the source arguments have modifiers, 0 if they do not.
373 class hasModifiers<ValueType SrcVT> {
374 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
375 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
378 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
379 class getIns32 <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
380 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
381 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
385 // Returns the input arguments for VOP3 instructions for the given SrcVT.
386 class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC,
387 RegisterClass Src2RC, int NumSrcArgs,
391 !if (!eq(NumSrcArgs, 1),
392 !if (!eq(HasModifiers, 1),
393 // VOP1 with modifiers
394 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
395 i32imm:$clamp, i32imm:$omod)
397 // VOP1 without modifiers
400 !if (!eq(NumSrcArgs, 2),
401 !if (!eq(HasModifiers, 1),
402 // VOP 2 with modifiers
403 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
404 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
405 i32imm:$clamp, i32imm:$omod)
407 // VOP2 without modifiers
408 (ins Src0RC:$src0, Src1RC:$src1)
410 /* NumSrcArgs == 3 */,
411 !if (!eq(HasModifiers, 1),
412 // VOP3 with modifiers
413 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
414 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
415 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
416 i32imm:$clamp, i32imm:$omod)
418 // VOP3 without modifiers
419 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
423 // Returns the assembly string for the inputs and outputs of a VOP[12C]
424 // instruction. This does not add the _e32 suffix, so it can be reused
426 class getAsm32 <int NumSrcArgs> {
427 string src1 = ", $src1";
428 string src2 = ", $src2";
429 string ret = " $dst, $src0"#
430 !if(!eq(NumSrcArgs, 1), "", src1)#
431 !if(!eq(NumSrcArgs, 3), src2, "");
434 // Returns the assembly string for the inputs and outputs of a VOP3
436 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
437 string src0 = "$src0_modifiers,";
438 string src1 = !if(!eq(NumSrcArgs, 1), "", " $src1_modifiers,");
439 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers,", "");
441 !if(!eq(HasModifiers, 0),
442 getAsm32<NumSrcArgs>.ret,
443 " $dst, "#src0#src1#src2#" $clamp, $omod");
447 class VOPProfile <list<ValueType> _ArgVT> {
449 field list<ValueType> ArgVT = _ArgVT;
451 field ValueType DstVT = ArgVT[0];
452 field ValueType Src0VT = ArgVT[1];
453 field ValueType Src1VT = ArgVT[2];
454 field ValueType Src2VT = ArgVT[3];
455 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
456 field RegisterClass Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
457 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
458 field RegisterClass Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
459 field RegisterClass Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
460 field RegisterClass Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
462 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
463 field bit HasModifiers = hasModifiers<Src0VT>.ret;
465 field dag Outs = (outs DstRC:$dst);
467 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
468 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
471 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
472 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
475 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
476 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
477 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
478 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
479 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
480 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
481 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
482 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
483 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
485 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
486 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
487 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
488 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
489 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
490 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
491 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
492 let Src0RC32 = VReg_32;
494 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
495 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
497 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
498 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
499 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
500 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
503 class VOP <string opName> {
504 string OpName = opName;
507 class VOP2_REV <string revOp, bit isOrig> {
508 string RevOp = revOp;
512 class SIMCInstr <string pseudo, int subtarget> {
513 string PseudoInstr = pseudo;
514 int Subtarget = subtarget;
517 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
519 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
520 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
521 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
522 bits<2> omod = !if(HasModifiers, ?, 0);
523 bits<1> clamp = !if(HasModifiers, ?, 0);
524 bits<9> src1 = !if(HasSrc1, ?, 0);
525 bits<9> src2 = !if(HasSrc2, ?, 0);
528 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
529 VOP3Common <outs, ins, "", pattern>,
531 SIMCInstr<opName, SISubtarget.NONE> {
535 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
536 VOP3 <op, outs, ins, asm, []>,
537 SIMCInstr<opName, SISubtarget.SI>;
539 multiclass VOP3_m <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern,
540 string opName, int NumSrcArgs, bit HasMods = 1> {
542 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
544 def _si : VOP3_Real_si <op, outs, ins, asm, opName>,
545 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
546 !if(!eq(NumSrcArgs, 2), 0, 1),
551 multiclass VOP3_1_m <bits<8> op, dag outs, dag ins, string asm,
552 list<dag> pattern, string opName, bit HasMods = 1> {
554 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
556 def _si : VOP3_Real_si <
557 {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
558 outs, ins, asm, opName>,
559 VOP3DisableFields<0, 0, HasMods>;
562 multiclass VOP3_2_m <bits<9> op, dag outs, dag ins, string asm,
563 list<dag> pattern, string opName, string revOp,
564 bit HasMods = 1, bit UseFullOp = 0> {
566 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
567 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
569 def _si : VOP3_Real_si <op,
570 outs, ins, asm, opName>,
571 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>,
572 VOP3DisableFields<1, 0, HasMods>;
575 multiclass VOP3b_2_m <bits<9> op, dag outs, dag ins, string asm,
576 list<dag> pattern, string opName, string revOp,
577 bit HasMods = 1, bit UseFullOp = 0> {
578 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
579 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
581 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
582 // can write it into any SGPR. We currently don't use the carry out,
583 // so for now hardcode it to VCC as well.
584 let sdst = SIOperand.VCC, Defs = [VCC] in {
585 def _si : VOP3b <op, outs, ins, asm, pattern>,
586 VOP3DisableFields<1, 0, HasMods>,
587 SIMCInstr<opName, SISubtarget.SI>,
588 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
589 } // End sdst = SIOperand.VCC, Defs = [VCC]
592 multiclass VOP3_C_m <bits<8> op, dag outs, dag ins, string asm,
593 list<dag> pattern, string opName,
594 bit HasMods, bit defExec> {
596 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
598 def _si : VOP3_Real_si <
599 {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
600 outs, ins, asm, opName>,
601 VOP3DisableFields<1, 0, HasMods> {
602 let Defs = !if(defExec, [EXEC], []);
606 multiclass VOP1_Helper <bits<8> op, string opName, dag outs,
607 dag ins32, string asm32, list<dag> pat32,
608 dag ins64, string asm64, list<dag> pat64,
611 def _e32 : VOP1 <op, outs, ins32, opName#asm32, pat32>, VOP<opName>;
613 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
616 multiclass VOP1Inst <bits<8> op, string opName, VOPProfile P,
617 SDPatternOperator node = null_frag> : VOP1_Helper <
619 P.Ins32, P.Asm32, [],
622 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
623 i32:$src0_modifiers, i32:$clamp, i32:$omod))))],
624 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
628 class VOP2_e32 <bits<6> op, string opName, dag outs, dag ins, string asm,
629 list<dag> pattern, string revOp> :
630 VOP2 <op, outs, ins, opName#asm, pattern>,
632 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
634 multiclass VOP2_Helper <bits<6> op, string opName, dag outs,
635 dag ins32, string asm32, list<dag> pat32,
636 dag ins64, string asm64, list<dag> pat64,
637 string revOp, bit HasMods> {
638 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
640 defm _e64 : VOP3_2_m <
641 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
642 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
646 multiclass VOP2Inst <bits<6> op, string opName, VOPProfile P,
647 SDPatternOperator node = null_frag,
648 string revOp = opName> : VOP2_Helper <
650 P.Ins32, P.Asm32, [],
654 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
655 i32:$clamp, i32:$omod)),
656 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
657 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
658 revOp, P.HasModifiers
661 multiclass VOP2b_Helper <bits<6> op, string opName, dag outs,
662 dag ins32, string asm32, list<dag> pat32,
663 dag ins64, string asm64, list<dag> pat64,
664 string revOp, bit HasMods> {
666 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
668 defm _e64 : VOP3b_2_m <
669 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
670 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
674 multiclass VOP2bInst <bits<6> op, string opName, VOPProfile P,
675 SDPatternOperator node = null_frag,
676 string revOp = opName> : VOP2b_Helper <
678 P.Ins32, P.Asm32, [],
682 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
683 i32:$clamp, i32:$omod)),
684 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
685 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
686 revOp, P.HasModifiers
689 multiclass VOPC_Helper <bits<8> op, string opName,
690 dag ins32, string asm32, list<dag> pat32,
691 dag out64, dag ins64, string asm64, list<dag> pat64,
692 bit HasMods, bit DefExec> {
693 def _e32 : VOPC <op, ins32, opName#asm32, pat32>, VOP <opName> {
694 let Defs = !if(DefExec, [EXEC], []);
697 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64, opName,
701 multiclass VOPCInst <bits<8> op, string opName,
702 VOPProfile P, PatLeaf cond = COND_NULL,
703 bit DefExec = 0> : VOPC_Helper <
705 P.Ins32, P.Asm32, [],
706 (outs SReg_64:$dst), P.Ins64, P.Asm64,
709 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
710 i32:$clamp, i32:$omod)),
711 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
713 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
714 P.HasModifiers, DefExec
717 multiclass VOPC_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
718 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
720 multiclass VOPC_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
721 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
723 multiclass VOPC_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
724 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
726 multiclass VOPC_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
727 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
730 multiclass VOPCX <bits<8> op, string opName, VOPProfile P,
731 PatLeaf cond = COND_NULL>
732 : VOPCInst <op, opName, P, cond, 1>;
734 multiclass VOPCX_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
735 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
737 multiclass VOPCX_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
738 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
740 multiclass VOPCX_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
741 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
743 multiclass VOPCX_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
744 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
746 multiclass VOP3_Helper <bits<9> op, string opName, dag outs, dag ins, string asm,
747 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
748 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
751 multiclass VOP3Inst <bits<9> op, string opName, VOPProfile P,
752 SDPatternOperator node = null_frag> : VOP3_Helper <
753 op, opName, P.Outs, P.Ins64, P.Asm64,
754 !if(!eq(P.NumSrcArgs, 3),
757 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
758 i32:$clamp, i32:$omod)),
759 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
760 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
761 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
763 !if(!eq(P.NumSrcArgs, 2),
766 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
767 i32:$clamp, i32:$omod)),
768 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
769 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
770 /* P.NumSrcArgs == 1 */,
773 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
774 i32:$clamp, i32:$omod))))],
775 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
776 P.NumSrcArgs, P.HasModifiers
779 multiclass VOP3b_Helper <bits<9> op, RegisterClass vrc, RegisterClass arc,
780 string opName, list<dag> pattern> :
782 op, (outs vrc:$dst0, SReg_64:$dst1),
783 (ins arc:$src0, arc:$src1, arc:$src2,
784 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
785 opName#" $dst0, $dst1, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern,
789 multiclass VOP3b_64 <bits<9> op, string opName, list<dag> pattern> :
790 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
792 multiclass VOP3b_32 <bits<9> op, string opName, list<dag> pattern> :
793 VOP3b_Helper <op, VReg_32, VSrc_32, opName, pattern>;
795 //===----------------------------------------------------------------------===//
796 // Vector I/O classes
797 //===----------------------------------------------------------------------===//
799 class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
800 DS <op, outs, ins, asm, pat> {
803 // Single load interpret the 2 i8imm operands as a single i16 offset.
804 let offset0 = offset{7-0};
805 let offset1 = offset{15-8};
808 class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
810 (outs regClass:$vdst),
811 (ins i1imm:$gds, VReg_32:$addr, u16imm:$offset),
812 asm#" $vdst, $addr, $offset, [M0]",
820 class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
822 (outs regClass:$vdst),
823 (ins i1imm:$gds, VReg_32:$addr, u8imm:$offset0, u8imm:$offset1),
824 asm#" $vdst, $addr, $offset0, $offset1, [M0]",
832 class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
835 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, u16imm:$offset),
836 asm#" $addr, $data0, $offset [M0]",
844 class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
847 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, regClass:$data1,
848 u8imm:$offset0, u8imm:$offset1),
849 asm#" $addr, $data0, $data1, $offset0, $offset1 [M0]",
856 // 1 address, 1 data.
857 class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
860 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
861 asm#" $vdst, $addr, $data0, $offset, [M0]",
869 // 1 address, 2 data.
870 class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
873 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
874 asm#" $vdst, $addr, $data0, $data1, $offset, [M0]",
880 // 1 address, 2 data.
881 class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
884 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
885 asm#" $addr, $data0, $data1, $offset, [M0]",
891 // 1 address, 1 data.
892 class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
895 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
896 asm#" $addr, $data0, $offset, [M0]",
904 class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
907 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
908 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
909 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
910 asm#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
911 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
917 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
918 ValueType load_vt = i32,
919 SDPatternOperator ld = null_frag> {
921 let lds = 0, mayLoad = 1 in {
925 let offen = 0, idxen = 0, vaddr = 0 in {
926 def _OFFSET : MUBUF <op, (outs regClass:$vdata),
927 (ins SReg_128:$srsrc,
928 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
930 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
933 let offen = 1, idxen = 0 in {
934 def _OFFEN : MUBUF <op, (outs regClass:$vdata),
935 (ins SReg_128:$srsrc, VReg_32:$vaddr,
936 SSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
938 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
941 let offen = 0, idxen = 1 in {
942 def _IDXEN : MUBUF <op, (outs regClass:$vdata),
943 (ins SReg_128:$srsrc, VReg_32:$vaddr,
944 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
946 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
949 let offen = 1, idxen = 1 in {
950 def _BOTHEN : MUBUF <op, (outs regClass:$vdata),
951 (ins SReg_128:$srsrc, VReg_64:$vaddr,
952 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
953 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
957 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
958 def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
959 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
960 asm#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
961 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
962 i64:$vaddr, i16:$offset)))]>;
967 multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
968 ValueType store_vt, SDPatternOperator st> {
970 let addr64 = 0, lds = 0 in {
974 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
975 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
977 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
978 "$glc"#"$slc"#"$tfe",
982 let offen = 1, idxen = 0 in {
985 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
986 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
987 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
988 "$glc"#"$slc"#"$tfe",
991 } // end offen = 1, idxen = 0
993 } // End addr64 = 0, lds = 0
995 def _ADDR64 : MUBUF <
997 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
998 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
999 [(st store_vt:$vdata,
1000 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]> {
1013 let soffset = 128; // ZERO
1017 class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
1019 (outs regClass:$dst),
1020 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1021 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
1022 i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1023 asm#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1024 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
1030 class MIMG_Mask <string op, int channels> {
1032 int Channels = channels;
1035 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1036 RegisterClass dst_rc,
1037 RegisterClass src_rc> : MIMG <
1039 (outs dst_rc:$vdata),
1040 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1041 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1043 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1044 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1049 let hasPostISelHook = 1;
1052 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1053 RegisterClass dst_rc,
1055 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_32>,
1056 MIMG_Mask<asm#"_V1", channels>;
1057 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1058 MIMG_Mask<asm#"_V2", channels>;
1059 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1060 MIMG_Mask<asm#"_V4", channels>;
1063 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1064 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VReg_32, 1>;
1065 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1066 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1067 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1070 class MIMG_Sampler_Helper <bits<7> op, string asm,
1071 RegisterClass dst_rc,
1072 RegisterClass src_rc> : MIMG <
1074 (outs dst_rc:$vdata),
1075 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1076 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1077 SReg_256:$srsrc, SReg_128:$ssamp),
1078 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1079 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1083 let hasPostISelHook = 1;
1086 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1087 RegisterClass dst_rc,
1089 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_32>,
1090 MIMG_Mask<asm#"_V1", channels>;
1091 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1092 MIMG_Mask<asm#"_V2", channels>;
1093 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1094 MIMG_Mask<asm#"_V4", channels>;
1095 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1096 MIMG_Mask<asm#"_V8", channels>;
1097 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1098 MIMG_Mask<asm#"_V16", channels>;
1101 multiclass MIMG_Sampler <bits<7> op, string asm> {
1102 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VReg_32, 1>;
1103 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1104 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1105 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1108 class MIMG_Gather_Helper <bits<7> op, string asm,
1109 RegisterClass dst_rc,
1110 RegisterClass src_rc> : MIMG <
1112 (outs dst_rc:$vdata),
1113 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1114 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1115 SReg_256:$srsrc, SReg_128:$ssamp),
1116 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1117 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1122 // DMASK was repurposed for GATHER4. 4 components are always
1123 // returned and DMASK works like a swizzle - it selects
1124 // the component to fetch. The only useful DMASK values are
1125 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1126 // (red,red,red,red) etc.) The ISA document doesn't mention
1128 // Therefore, disable all code which updates DMASK by setting these two:
1130 let hasPostISelHook = 0;
1133 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1134 RegisterClass dst_rc,
1136 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_32>,
1137 MIMG_Mask<asm#"_V1", channels>;
1138 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1139 MIMG_Mask<asm#"_V2", channels>;
1140 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1141 MIMG_Mask<asm#"_V4", channels>;
1142 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1143 MIMG_Mask<asm#"_V8", channels>;
1144 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1145 MIMG_Mask<asm#"_V16", channels>;
1148 multiclass MIMG_Gather <bits<7> op, string asm> {
1149 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VReg_32, 1>;
1150 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
1151 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
1152 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
1155 //===----------------------------------------------------------------------===//
1156 // Vector instruction mappings
1157 //===----------------------------------------------------------------------===//
1159 // Maps an opcode in e32 form to its e64 equivalent
1160 def getVOPe64 : InstrMapping {
1161 let FilterClass = "VOP";
1162 let RowFields = ["OpName"];
1163 let ColFields = ["Size"];
1165 let ValueCols = [["8"]];
1168 // Maps an opcode in e64 form to its e32 equivalent
1169 def getVOPe32 : InstrMapping {
1170 let FilterClass = "VOP";
1171 let RowFields = ["OpName"];
1172 let ColFields = ["Size"];
1174 let ValueCols = [["4"]];
1177 // Maps an original opcode to its commuted version
1178 def getCommuteRev : InstrMapping {
1179 let FilterClass = "VOP2_REV";
1180 let RowFields = ["RevOp"];
1181 let ColFields = ["IsOrig"];
1183 let ValueCols = [["0"]];
1186 def getMaskedMIMGOp : InstrMapping {
1187 let FilterClass = "MIMG_Mask";
1188 let RowFields = ["Op"];
1189 let ColFields = ["Channels"];
1191 let ValueCols = [["1"], ["2"], ["3"] ];
1194 // Maps an commuted opcode to its original version
1195 def getCommuteOrig : InstrMapping {
1196 let FilterClass = "VOP2_REV";
1197 let RowFields = ["RevOp"];
1198 let ColFields = ["IsOrig"];
1200 let ValueCols = [["1"]];
1203 def isDS : InstrMapping {
1204 let FilterClass = "DS";
1205 let RowFields = ["Inst"];
1206 let ColFields = ["Size"];
1208 let ValueCols = [["8"]];
1211 def getMCOpcode : InstrMapping {
1212 let FilterClass = "SIMCInstr";
1213 let RowFields = ["PseudoInstr"];
1214 let ColFields = ["Subtarget"];
1215 let KeyCol = [!cast<string>(SISubtarget.NONE)];
1216 let ValueCols = [[!cast<string>(SISubtarget.SI)]];
1219 include "SIInstructions.td"