1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
15 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
16 field bits<8> SI = si;
17 field bits<8> VI = vi;
19 field bits<9> SI3 = {0, si{7-0}};
20 field bits<10> VI3 = {0, 0, vi{7-0}};
23 class vop1 <bits<8> si, bits<8> vi = si> : vop {
24 field bits<8> SI = si;
25 field bits<8> VI = vi;
27 field bits<9> SI3 = {1, 1, si{6-0}};
28 field bits<10> VI3 = !add(0x140, vi);
31 class vop2 <bits<6> si, bits<6> vi = si> : vop {
32 field bits<6> SI = si;
33 field bits<6> VI = vi;
35 field bits<9> SI3 = {1, 0, 0, si{5-0}};
36 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
39 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
40 // that doesn't have VOP2 encoding on VI
41 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
45 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
50 class sop1 <bits<8> si, bits<8> vi = si> {
51 field bits<8> SI = si;
52 field bits<8> VI = vi;
55 class sop2 <bits<7> si, bits<7> vi = si> {
56 field bits<7> SI = si;
57 field bits<7> VI = vi;
60 class sopk <bits<5> si, bits<5> vi = si> {
61 field bits<5> SI = si;
62 field bits<5> VI = vi;
65 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
66 // in AMDGPUInstrInfo.cpp
73 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
77 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
78 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
79 [SDNPMayLoad, SDNPMemOperand]
82 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
84 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
85 SDTCisVT<1, iAny>, // vdata(VGPR)
86 SDTCisVT<2, i32>, // num_channels(imm)
87 SDTCisVT<3, i32>, // vaddr(VGPR)
88 SDTCisVT<4, i32>, // soffset(SGPR)
89 SDTCisVT<5, i32>, // inst_offset(imm)
90 SDTCisVT<6, i32>, // dfmt(imm)
91 SDTCisVT<7, i32>, // nfmt(imm)
92 SDTCisVT<8, i32>, // offen(imm)
93 SDTCisVT<9, i32>, // idxen(imm)
94 SDTCisVT<10, i32>, // glc(imm)
95 SDTCisVT<11, i32>, // slc(imm)
96 SDTCisVT<12, i32> // tfe(imm)
98 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
101 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
102 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
106 class SDSample<string opcode> : SDNode <opcode,
107 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
108 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
111 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
112 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
113 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
114 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
116 def SIconstdata_ptr : SDNode<
117 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
120 // Transformation function, extract the lower 32bit of a 64bit immediate
121 def LO32 : SDNodeXForm<imm, [{
122 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
125 def LO32f : SDNodeXForm<fpimm, [{
126 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
127 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
130 // Transformation function, extract the upper 32bit of a 64bit immediate
131 def HI32 : SDNodeXForm<imm, [{
132 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
135 def HI32f : SDNodeXForm<fpimm, [{
136 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
137 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
140 def IMM8bitDWORD : PatLeaf <(imm),
141 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
144 def as_dword_i32imm : SDNodeXForm<imm, [{
145 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
148 def as_i1imm : SDNodeXForm<imm, [{
149 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
152 def as_i8imm : SDNodeXForm<imm, [{
153 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
156 def as_i16imm : SDNodeXForm<imm, [{
157 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
160 def as_i32imm: SDNodeXForm<imm, [{
161 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
164 def as_i64imm: SDNodeXForm<imm, [{
165 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
168 // Copied from the AArch64 backend:
169 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
170 return CurDAG->getTargetConstant(
171 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
174 // Copied from the AArch64 backend:
175 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
176 return CurDAG->getTargetConstant(
177 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
180 def IMM8bit : PatLeaf <(imm),
181 [{return isUInt<8>(N->getZExtValue());}]
184 def IMM12bit : PatLeaf <(imm),
185 [{return isUInt<12>(N->getZExtValue());}]
188 def IMM16bit : PatLeaf <(imm),
189 [{return isUInt<16>(N->getZExtValue());}]
192 def IMM20bit : PatLeaf <(imm),
193 [{return isUInt<20>(N->getZExtValue());}]
196 def IMM32bit : PatLeaf <(imm),
197 [{return isUInt<32>(N->getZExtValue());}]
200 def mubuf_vaddr_offset : PatFrag<
201 (ops node:$ptr, node:$offset, node:$imm_offset),
202 (add (add node:$ptr, node:$offset), node:$imm_offset)
205 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
206 return isInlineImmediate(N);
209 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
210 return isInlineImmediate(N);
213 class SGPRImm <dag frag> : PatLeaf<frag, [{
214 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
217 const SIRegisterInfo *SIRI =
218 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
219 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
221 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
228 //===----------------------------------------------------------------------===//
230 //===----------------------------------------------------------------------===//
232 def FRAMEri32 : Operand<iPTR> {
233 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
236 def sopp_brtarget : Operand<OtherVT> {
237 let EncoderMethod = "getSOPPBrEncoding";
238 let OperandType = "OPERAND_PCREL";
241 include "SIInstrFormats.td"
242 include "VIInstrFormats.td"
244 let OperandType = "OPERAND_IMMEDIATE" in {
246 def offen : Operand<i1> {
247 let PrintMethod = "printOffen";
249 def idxen : Operand<i1> {
250 let PrintMethod = "printIdxen";
252 def addr64 : Operand<i1> {
253 let PrintMethod = "printAddr64";
255 def mbuf_offset : Operand<i16> {
256 let PrintMethod = "printMBUFOffset";
258 def ds_offset : Operand<i16> {
259 let PrintMethod = "printDSOffset";
261 def ds_offset0 : Operand<i8> {
262 let PrintMethod = "printDSOffset0";
264 def ds_offset1 : Operand<i8> {
265 let PrintMethod = "printDSOffset1";
267 def glc : Operand <i1> {
268 let PrintMethod = "printGLC";
270 def slc : Operand <i1> {
271 let PrintMethod = "printSLC";
273 def tfe : Operand <i1> {
274 let PrintMethod = "printTFE";
277 def omod : Operand <i32> {
278 let PrintMethod = "printOModSI";
281 def ClampMod : Operand <i1> {
282 let PrintMethod = "printClampSI";
285 } // End OperandType = "OPERAND_IMMEDIATE"
287 //===----------------------------------------------------------------------===//
289 //===----------------------------------------------------------------------===//
291 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
292 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
294 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
295 def MUBUFAddr64 : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
296 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
297 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
298 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
299 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
301 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
302 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
303 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
304 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
306 //===----------------------------------------------------------------------===//
307 // SI assembler operands
308 //===----------------------------------------------------------------------===//
328 //===----------------------------------------------------------------------===//
330 // SI Instruction multiclass helpers.
332 // Instructions with _32 take 32-bit operands.
333 // Instructions with _64 take 64-bit operands.
335 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
336 // encoding is the standard encoding, but instruction that make use of
337 // any of the instruction modifiers must use the 64-bit encoding.
339 // Instructions with _e32 use the 32-bit encoding.
340 // Instructions with _e64 use the 64-bit encoding.
342 //===----------------------------------------------------------------------===//
344 class SIMCInstr <string pseudo, int subtarget> {
345 string PseudoInstr = pseudo;
346 int Subtarget = subtarget;
349 //===----------------------------------------------------------------------===//
351 //===----------------------------------------------------------------------===//
353 class EXPCommon : InstSI<
355 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
356 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
357 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
366 let isPseudo = 1 in {
367 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
370 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
372 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
375 //===----------------------------------------------------------------------===//
377 //===----------------------------------------------------------------------===//
379 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
380 SOP1 <outs, ins, "", pattern>,
381 SIMCInstr<opName, SISubtarget.NONE> {
385 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
386 SOP1 <outs, ins, asm, []>,
388 SIMCInstr<opName, SISubtarget.SI>;
390 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
391 SOP1 <outs, ins, asm, []>,
393 SIMCInstr<opName, SISubtarget.VI>;
395 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
398 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
400 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
402 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
406 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
407 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
408 opName#" $dst, $src0", pattern
411 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
412 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
413 opName#" $dst, $src0", pattern
416 // no input, 64-bit output.
417 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
418 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
420 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
425 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
431 // 64-bit input, no output
432 multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
433 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
435 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
440 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
446 // 64-bit input, 32-bit output.
447 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
448 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
449 opName#" $dst, $src0", pattern
452 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
453 SOP2<outs, ins, "", pattern>,
454 SIMCInstr<opName, SISubtarget.NONE> {
459 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
460 SOP2<outs, ins, asm, []>,
462 SIMCInstr<opName, SISubtarget.SI>;
464 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
465 SOP2<outs, ins, asm, []>,
467 SIMCInstr<opName, SISubtarget.VI>;
469 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
470 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
471 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
473 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
474 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
475 opName#" $dst, $src0, $src1 [$scc]">;
477 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
478 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
479 opName#" $dst, $src0, $src1 [$scc]">;
482 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
485 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
487 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
489 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
493 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
494 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
495 opName#" $dst, $src0, $src1", pattern
498 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
499 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
500 opName#" $dst, $src0, $src1", pattern
503 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
504 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
505 opName#" $dst, $src0, $src1", pattern
508 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
509 string opName, PatLeaf cond> : SOPC <
510 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
511 opName#" $dst, $src0, $src1", []>;
513 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
514 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
516 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
517 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
519 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
520 SOPK <outs, ins, "", pattern>,
521 SIMCInstr<opName, SISubtarget.NONE> {
525 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
526 SOPK <outs, ins, asm, []>,
528 SIMCInstr<opName, SISubtarget.SI>;
530 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
531 SOPK <outs, ins, asm, []>,
533 SIMCInstr<opName, SISubtarget.VI>;
535 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
536 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
539 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
540 opName#" $dst, $src0">;
542 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
543 opName#" $dst, $src0">;
546 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
547 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
548 (ins SReg_32:$src0, u16imm:$src1), pattern>;
550 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
551 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
553 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
554 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
557 //===----------------------------------------------------------------------===//
559 //===----------------------------------------------------------------------===//
561 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
562 SMRD <outs, ins, "", pattern>,
563 SIMCInstr<opName, SISubtarget.NONE> {
567 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
569 SMRD <outs, ins, asm, []>,
571 SIMCInstr<opName, SISubtarget.SI>;
573 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
575 SMRD <outs, ins, asm, []>,
577 SIMCInstr<opName, SISubtarget.VI>;
579 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
580 string asm, list<dag> pattern> {
582 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
584 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
586 // glc is only applicable to scalar stores, which are not yet
589 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
593 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
594 RegisterClass dstClass> {
596 op, opName#"_IMM", 1, (outs dstClass:$dst),
597 (ins baseClass:$sbase, u32imm:$offset),
598 opName#" $dst, $sbase, $offset", []
601 defm _SGPR : SMRD_m <
602 op, opName#"_SGPR", 0, (outs dstClass:$dst),
603 (ins baseClass:$sbase, SReg_32:$soff),
604 opName#" $dst, $sbase, $soff", []
608 //===----------------------------------------------------------------------===//
609 // Vector ALU classes
610 //===----------------------------------------------------------------------===//
612 // This must always be right before the operand being input modified.
613 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
614 let PrintMethod = "printOperandAndMods";
616 def InputModsNoDefault : Operand <i32> {
617 let PrintMethod = "printOperandAndMods";
620 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
622 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
623 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
627 // Returns the register class to use for the destination of VOP[123C]
628 // instructions for the given VT.
629 class getVALUDstForVT<ValueType VT> {
630 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32,
631 !if(!eq(VT.Size, 64), VReg_64,
632 SReg_64)); // else VT == i1
635 // Returns the register class to use for source 0 of VOP[12C]
636 // instructions for the given VT.
637 class getVOPSrc0ForVT<ValueType VT> {
638 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
641 // Returns the register class to use for source 1 of VOP[12C] for the
643 class getVOPSrc1ForVT<ValueType VT> {
644 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
647 // Returns the register class to use for sources of VOP3 instructions for the
649 class getVOP3SrcForVT<ValueType VT> {
650 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
653 // Returns 1 if the source arguments have modifiers, 0 if they do not.
654 class hasModifiers<ValueType SrcVT> {
655 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
656 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
659 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
660 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
661 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
662 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
666 // Returns the input arguments for VOP3 instructions for the given SrcVT.
667 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
668 RegisterOperand Src2RC, int NumSrcArgs,
672 !if (!eq(NumSrcArgs, 1),
673 !if (!eq(HasModifiers, 1),
674 // VOP1 with modifiers
675 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
676 ClampMod:$clamp, omod:$omod)
678 // VOP1 without modifiers
681 !if (!eq(NumSrcArgs, 2),
682 !if (!eq(HasModifiers, 1),
683 // VOP 2 with modifiers
684 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
685 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
686 ClampMod:$clamp, omod:$omod)
688 // VOP2 without modifiers
689 (ins Src0RC:$src0, Src1RC:$src1)
691 /* NumSrcArgs == 3 */,
692 !if (!eq(HasModifiers, 1),
693 // VOP3 with modifiers
694 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
695 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
696 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
697 ClampMod:$clamp, omod:$omod)
699 // VOP3 without modifiers
700 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
704 // Returns the assembly string for the inputs and outputs of a VOP[12C]
705 // instruction. This does not add the _e32 suffix, so it can be reused
707 class getAsm32 <int NumSrcArgs> {
708 string src1 = ", $src1";
709 string src2 = ", $src2";
710 string ret = " $dst, $src0"#
711 !if(!eq(NumSrcArgs, 1), "", src1)#
712 !if(!eq(NumSrcArgs, 3), src2, "");
715 // Returns the assembly string for the inputs and outputs of a VOP3
717 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
718 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
719 string src1 = !if(!eq(NumSrcArgs, 1), "",
720 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
721 " $src1_modifiers,"));
722 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
724 !if(!eq(HasModifiers, 0),
725 getAsm32<NumSrcArgs>.ret,
726 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
730 class VOPProfile <list<ValueType> _ArgVT> {
732 field list<ValueType> ArgVT = _ArgVT;
734 field ValueType DstVT = ArgVT[0];
735 field ValueType Src0VT = ArgVT[1];
736 field ValueType Src1VT = ArgVT[2];
737 field ValueType Src2VT = ArgVT[3];
738 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
739 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
740 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
741 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
742 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
743 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
745 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
746 field bit HasModifiers = hasModifiers<Src0VT>.ret;
748 field dag Outs = (outs DstRC:$dst);
750 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
751 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
754 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
755 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
758 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
759 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
760 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
761 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
762 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
763 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
764 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
765 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
766 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
768 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
769 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
770 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
771 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
772 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
773 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
774 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
775 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
776 let Src0RC32 = VCSrc_32;
779 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
780 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
781 let Asm64 = " $dst, $src0_modifiers, $src1";
784 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
785 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
786 let Asm64 = " $dst, $src0_modifiers, $src1";
789 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
790 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
791 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
793 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
794 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
795 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
796 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
799 class VOP <string opName> {
800 string OpName = opName;
803 class VOP2_REV <string revOp, bit isOrig> {
804 string RevOp = revOp;
808 class AtomicNoRet <string noRetOp, bit isRet> {
809 string NoRetOp = noRetOp;
813 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
814 VOP1Common <outs, ins, "", pattern>,
816 SIMCInstr <opName#"_e32", SISubtarget.NONE> {
820 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
822 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
824 def _si : VOP1<op.SI, outs, ins, asm, []>,
825 SIMCInstr <opName#"_e32", SISubtarget.SI>;
826 def _vi : VOP1<op.VI, outs, ins, asm, []>,
827 SIMCInstr <opName#"_e32", SISubtarget.VI>;
830 multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
832 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
834 def _si : VOP1<op.SI, outs, ins, asm, []>,
835 SIMCInstr <opName#"_e32", SISubtarget.SI>;
836 // No VI instruction. This class is for SI only.
839 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
840 VOP2Common <outs, ins, "", pattern>,
842 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
846 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
847 string opName, string revOp> {
848 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
849 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
851 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
852 SIMCInstr <opName#"_e32", SISubtarget.SI>;
855 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
856 string opName, string revOp> {
857 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
858 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
860 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
861 SIMCInstr <opName#"_e32", SISubtarget.SI>;
862 def _vi : VOP2 <op.VI, outs, ins, opName#asm, []>,
863 SIMCInstr <opName#"_e32", SISubtarget.VI>;
866 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
868 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
869 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
870 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
871 bits<2> omod = !if(HasModifiers, ?, 0);
872 bits<1> clamp = !if(HasModifiers, ?, 0);
873 bits<9> src1 = !if(HasSrc1, ?, 0);
874 bits<9> src2 = !if(HasSrc2, ?, 0);
877 class VOP3DisableModFields <bit HasSrc0Mods,
880 bit HasOutputMods = 0> {
881 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
882 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
883 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
884 bits<2> omod = !if(HasOutputMods, ?, 0);
885 bits<1> clamp = !if(HasOutputMods, ?, 0);
888 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
889 VOP3Common <outs, ins, "", pattern>,
891 SIMCInstr<opName#"_e64", SISubtarget.NONE> {
895 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
896 VOP3Common <outs, ins, asm, []>,
898 SIMCInstr<opName#"_e64", SISubtarget.SI>;
900 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
901 VOP3Common <outs, ins, asm, []>,
903 SIMCInstr <opName#"_e64", SISubtarget.VI>;
905 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
906 VOP3Common <outs, ins, asm, []>,
908 SIMCInstr<opName#"_e64", SISubtarget.SI>;
910 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
911 VOP3Common <outs, ins, asm, []>,
913 SIMCInstr <opName#"_e64", SISubtarget.VI>;
915 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
916 string opName, int NumSrcArgs, bit HasMods = 1> {
918 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
920 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
921 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
922 !if(!eq(NumSrcArgs, 2), 0, 1),
924 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
925 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
926 !if(!eq(NumSrcArgs, 2), 0, 1),
930 // VOP3_m without source modifiers
931 multiclass VOP3_m_nomods <vop op, dag outs, dag ins, string asm, list<dag> pattern,
932 string opName, int NumSrcArgs, bit HasMods = 1> {
934 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
936 let src0_modifiers = 0,
941 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
942 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
946 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
947 list<dag> pattern, string opName, bit HasMods = 1> {
949 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
951 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
952 VOP3DisableFields<0, 0, HasMods>;
954 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
955 VOP3DisableFields<0, 0, HasMods>;
958 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
959 list<dag> pattern, string opName, bit HasMods = 1> {
961 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
963 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
964 VOP3DisableFields<0, 0, HasMods>;
965 // No VI instruction. This class is for SI only.
968 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
969 list<dag> pattern, string opName, string revOp,
970 bit HasMods = 1, bit UseFullOp = 0> {
972 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
973 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
975 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
976 VOP3DisableFields<1, 0, HasMods>;
978 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
979 VOP3DisableFields<1, 0, HasMods>;
982 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
983 list<dag> pattern, string opName, string revOp,
984 bit HasMods = 1, bit UseFullOp = 0> {
986 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
987 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
989 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
990 VOP3DisableFields<1, 0, HasMods>;
992 // No VI instruction. This class is for SI only.
995 // XXX - Is v_div_scale_{f32|f64} only available in vop3b without
996 // option of implicit vcc use?
997 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
998 list<dag> pattern, string opName, string revOp,
999 bit HasMods = 1, bit UseFullOp = 0> {
1000 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1001 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1003 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
1004 // can write it into any SGPR. We currently don't use the carry out,
1005 // so for now hardcode it to VCC as well.
1006 let sdst = SIOperand.VCC, Defs = [VCC] in {
1007 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1008 VOP3DisableFields<1, 0, HasMods>;
1010 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1011 VOP3DisableFields<1, 0, HasMods>;
1012 } // End sdst = SIOperand.VCC, Defs = [VCC]
1015 multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
1016 list<dag> pattern, string opName, string revOp,
1017 bit HasMods = 1, bit UseFullOp = 0> {
1018 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1021 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1022 VOP3DisableFields<1, 1, HasMods>;
1024 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1025 VOP3DisableFields<1, 1, HasMods>;
1028 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1029 list<dag> pattern, string opName,
1030 bit HasMods, bit defExec> {
1032 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1034 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1035 VOP3DisableFields<1, 0, HasMods> {
1036 let Defs = !if(defExec, [EXEC], []);
1039 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1040 VOP3DisableFields<1, 0, HasMods> {
1041 let Defs = !if(defExec, [EXEC], []);
1045 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1046 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1047 string asm, list<dag> pattern = []> {
1048 let isPseudo = 1 in {
1049 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1050 SIMCInstr<opName, SISubtarget.NONE>;
1053 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1054 SIMCInstr <opName, SISubtarget.SI>;
1056 def _vi : VOP3Common <outs, ins, asm, []>,
1058 VOP3DisableFields <1, 0, 0>,
1059 SIMCInstr <opName, SISubtarget.VI>;
1062 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1063 dag ins32, string asm32, list<dag> pat32,
1064 dag ins64, string asm64, list<dag> pat64,
1067 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1069 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
1072 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1073 SDPatternOperator node = null_frag> : VOP1_Helper <
1075 P.Ins32, P.Asm32, [],
1078 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1079 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1080 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1084 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1085 SDPatternOperator node = null_frag> {
1087 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
1089 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1091 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1092 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1093 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1094 opName, P.HasModifiers>;
1097 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1098 dag ins32, string asm32, list<dag> pat32,
1099 dag ins64, string asm64, list<dag> pat64,
1100 string revOp, bit HasMods> {
1101 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1103 defm _e64 : VOP3_2_m <op,
1104 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1108 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1109 SDPatternOperator node = null_frag,
1110 string revOp = opName> : VOP2_Helper <
1112 P.Ins32, P.Asm32, [],
1116 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1117 i1:$clamp, i32:$omod)),
1118 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1119 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1120 revOp, P.HasModifiers
1123 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1124 SDPatternOperator node = null_frag,
1125 string revOp = opName> {
1126 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1128 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#"_e64"#P.Asm64,
1131 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1132 i1:$clamp, i32:$omod)),
1133 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1134 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1135 opName, revOp, P.HasModifiers>;
1138 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1139 dag ins32, string asm32, list<dag> pat32,
1140 dag ins64, string asm64, list<dag> pat64,
1141 string revOp, bit HasMods> {
1143 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1145 defm _e64 : VOP3b_2_m <op,
1146 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1150 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1151 SDPatternOperator node = null_frag,
1152 string revOp = opName> : VOP2b_Helper <
1154 P.Ins32, P.Asm32, [],
1158 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1159 i1:$clamp, i32:$omod)),
1160 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1161 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1162 revOp, P.HasModifiers
1165 // A VOP2 instruction that is VOP3-only on VI.
1166 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1167 dag ins32, string asm32, list<dag> pat32,
1168 dag ins64, string asm64, list<dag> pat64,
1169 string revOp, bit HasMods> {
1170 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1172 defm _e64 : VOP3_2_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName,
1176 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1177 SDPatternOperator node = null_frag,
1178 string revOp = opName>
1181 P.Ins32, P.Asm32, [],
1185 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1186 i1:$clamp, i32:$omod)),
1187 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1188 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1189 revOp, P.HasModifiers
1192 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1193 VOPCCommon <ins, "", pattern>,
1195 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1199 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1200 string opName, bit DefExec> {
1201 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1203 def _si : VOPC<op.SI, ins, asm, []>,
1204 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1205 let Defs = !if(DefExec, [EXEC], []);
1208 def _vi : VOPC<op.VI, ins, asm, []>,
1209 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1210 let Defs = !if(DefExec, [EXEC], []);
1214 multiclass VOPC_Helper <vopc op, string opName,
1215 dag ins32, string asm32, list<dag> pat32,
1216 dag out64, dag ins64, string asm64, list<dag> pat64,
1217 bit HasMods, bit DefExec> {
1218 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1220 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1221 opName, HasMods, DefExec>;
1224 // Special case for class instructions which only have modifiers on
1225 // the 1st source operand.
1226 multiclass VOPC_Class_Helper <vopc op, string opName,
1227 dag ins32, string asm32, list<dag> pat32,
1228 dag out64, dag ins64, string asm64, list<dag> pat64,
1229 bit HasMods, bit DefExec> {
1230 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1232 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1233 opName, HasMods, DefExec>,
1234 VOP3DisableModFields<1, 0, 0>;
1237 multiclass VOPCInst <vopc op, string opName,
1238 VOPProfile P, PatLeaf cond = COND_NULL,
1239 bit DefExec = 0> : VOPC_Helper <
1241 P.Ins32, P.Asm32, [],
1242 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1245 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1246 i1:$clamp, i32:$omod)),
1247 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1249 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1250 P.HasModifiers, DefExec
1253 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1254 bit DefExec = 0> : VOPC_Class_Helper <
1256 P.Ins32, P.Asm32, [],
1257 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1260 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1261 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1262 P.HasModifiers, DefExec
1266 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1267 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
1269 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1270 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
1272 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1273 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
1275 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1276 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
1279 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1280 PatLeaf cond = COND_NULL>
1281 : VOPCInst <op, opName, P, cond, 1>;
1283 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1284 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
1286 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1287 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
1289 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1290 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
1292 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1293 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
1295 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1296 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1297 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
1300 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1301 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1303 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1304 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1306 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1307 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1309 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1310 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1312 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1313 SDPatternOperator node = null_frag> : VOP3_Helper <
1314 op, opName, P.Outs, P.Ins64, P.Asm64,
1315 !if(!eq(P.NumSrcArgs, 3),
1318 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1319 i1:$clamp, i32:$omod)),
1320 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1321 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1322 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1324 !if(!eq(P.NumSrcArgs, 2),
1327 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1328 i1:$clamp, i32:$omod)),
1329 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1330 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1331 /* P.NumSrcArgs == 1 */,
1334 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1335 i1:$clamp, i32:$omod))))],
1336 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1337 P.NumSrcArgs, P.HasModifiers
1340 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1341 // only VOP instruction that implicitly reads VCC.
1342 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1344 SDPatternOperator node = null_frag> : VOP3_Helper <
1347 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1348 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1349 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1352 " $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1354 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1355 i1:$clamp, i32:$omod)),
1356 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1357 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1362 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1363 string opName, list<dag> pattern> :
1365 op, (outs vrc:$vdst, SReg_64:$sdst),
1366 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1367 InputModsNoDefault:$src1_modifiers, arc:$src1,
1368 InputModsNoDefault:$src2_modifiers, arc:$src2,
1369 ClampMod:$clamp, omod:$omod),
1370 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1371 opName, opName, 1, 1
1374 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1375 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1377 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1378 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1381 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1382 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1383 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1384 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1385 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1386 i32:$src1_modifiers, P.Src1VT:$src1,
1387 i32:$src2_modifiers, P.Src2VT:$src2,
1391 //===----------------------------------------------------------------------===//
1392 // Interpolation opcodes
1393 //===----------------------------------------------------------------------===//
1395 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1396 VINTRPCommon <outs, ins, "", pattern>,
1397 SIMCInstr<opName, SISubtarget.NONE> {
1401 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1403 VINTRPCommon <outs, ins, asm, []>,
1405 SIMCInstr<opName, SISubtarget.SI>;
1407 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1409 VINTRPCommon <outs, ins, asm, []>,
1411 SIMCInstr<opName, SISubtarget.VI>;
1413 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1414 string disableEncoding = "", string constraints = "",
1415 list<dag> pattern = []> {
1416 let DisableEncoding = disableEncoding,
1417 Constraints = constraints in {
1418 def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
1420 def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
1422 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
1426 //===----------------------------------------------------------------------===//
1427 // Vector I/O classes
1428 //===----------------------------------------------------------------------===//
1430 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1431 DS <outs, ins, "", pattern>,
1432 SIMCInstr <opName, SISubtarget.NONE> {
1436 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1437 DS <outs, ins, asm, []>,
1439 SIMCInstr <opName, SISubtarget.SI>;
1441 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1442 DS <outs, ins, asm, []>,
1444 SIMCInstr <opName, SISubtarget.VI>;
1446 class DS_1A_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1447 DS <outs, ins, asm, []>,
1449 SIMCInstr <opName, SISubtarget.SI> {
1451 // Single load interpret the 2 i8imm operands as a single i16 offset.
1453 let offset0 = offset{7-0};
1454 let offset1 = offset{15-8};
1457 class DS_1A_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1458 DS <outs, ins, asm, []>,
1460 SIMCInstr <opName, SISubtarget.VI> {
1462 // Single load interpret the 2 i8imm operands as a single i16 offset.
1464 let offset0 = offset{7-0};
1465 let offset1 = offset{15-8};
1468 multiclass DS_1A_Load_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1470 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1471 def "" : DS_Pseudo <opName, outs, ins, pat>;
1473 let data0 = 0, data1 = 0 in {
1474 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1475 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1480 multiclass DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass>
1484 (outs regClass:$vdst),
1485 (ins i1imm:$gds, VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
1486 asm#" $vdst, $addr"#"$offset"#" [M0]",
1489 multiclass DS_Load2_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1491 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1492 def "" : DS_Pseudo <opName, outs, ins, pat>;
1494 let data0 = 0, data1 = 0 in {
1495 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1496 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1501 multiclass DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass>
1505 (outs regClass:$vdst),
1506 (ins i1imm:$gds, VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1508 asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]",
1511 multiclass DS_1A_Store_m <bits<8> op, string opName, dag outs, dag ins,
1512 string asm, list<dag> pat> {
1513 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1514 def "" : DS_Pseudo <opName, outs, ins, pat>;
1516 let data1 = 0, vdst = 0 in {
1517 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1518 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1523 multiclass DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass>
1528 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, ds_offset:$offset, M0Reg:$m0),
1529 asm#" $addr, $data0"#"$offset"#" [M0]",
1532 multiclass DS_Store_m <bits<8> op, string opName, dag outs, dag ins,
1533 string asm, list<dag> pat> {
1534 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1535 def "" : DS_Pseudo <opName, outs, ins, pat>;
1538 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1539 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1544 multiclass DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass>
1549 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, regClass:$data1,
1550 ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0),
1551 asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]",
1554 // 1 address, 1 data.
1555 multiclass DS_1A1D_RET_m <bits<8> op, string opName, dag outs, dag ins,
1556 string asm, list<dag> pat, string noRetOp> {
1557 let mayLoad = 1, mayStore = 1,
1558 hasPostISelHook = 1 // Adjusted to no return version.
1560 def "" : DS_Pseudo <opName, outs, ins, pat>,
1561 AtomicNoRet<noRetOp, 1>;
1564 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1565 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1570 multiclass DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc,
1571 string noRetOp = ""> : DS_1A1D_RET_m <
1574 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1575 asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", [], noRetOp>;
1577 // 1 address, 2 data.
1578 multiclass DS_1A2D_RET_m <bits<8> op, string opName, dag outs, dag ins,
1579 string asm, list<dag> pat, string noRetOp> {
1580 let mayLoad = 1, mayStore = 1,
1581 hasPostISelHook = 1 // Adjusted to no return version.
1583 def "" : DS_Pseudo <opName, outs, ins, pat>,
1584 AtomicNoRet<noRetOp, 1>;
1586 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1587 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1591 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1592 string noRetOp = ""> : DS_1A2D_RET_m <
1595 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1596 asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]",
1599 // 1 address, 2 data.
1600 multiclass DS_1A2D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
1601 string asm, list<dag> pat, string noRetOp> {
1602 let mayLoad = 1, mayStore = 1 in {
1603 def "" : DS_Pseudo <opName, outs, ins, pat>,
1604 AtomicNoRet<noRetOp, 0>;
1607 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1608 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1613 multiclass DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc,
1614 string noRetOp = asm> : DS_1A2D_NORET_m <
1617 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1618 asm#" $addr, $data0, $data1"#"$offset"#" [M0]",
1621 // 1 address, 1 data.
1622 multiclass DS_1A1D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
1623 string asm, list<dag> pat, string noRetOp> {
1624 let mayLoad = 1, mayStore = 1 in {
1625 def "" : DS_Pseudo <opName, outs, ins, pat>,
1626 AtomicNoRet<noRetOp, 0>;
1628 let data1 = 0, vdst = 0 in {
1629 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1630 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1635 multiclass DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc,
1636 string noRetOp = asm> : DS_1A1D_NORET_m <
1639 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1640 asm#" $addr, $data0"#"$offset"#" [M0]",
1643 //===----------------------------------------------------------------------===//
1645 //===----------------------------------------------------------------------===//
1647 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1648 MTBUF <outs, ins, "", pattern>,
1649 SIMCInstr<opName, SISubtarget.NONE> {
1653 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1655 MTBUF <outs, ins, asm, []>,
1657 SIMCInstr<opName, SISubtarget.SI>;
1659 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1660 MTBUF <outs, ins, asm, []>,
1662 SIMCInstr <opName, SISubtarget.VI>;
1664 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1665 list<dag> pattern> {
1667 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1669 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1671 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1675 let mayStore = 1, mayLoad = 0 in {
1677 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1678 RegisterClass regClass> : MTBUF_m <
1680 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1681 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
1682 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1683 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1684 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1687 } // mayStore = 1, mayLoad = 0
1689 let mayLoad = 1, mayStore = 0 in {
1691 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1692 RegisterClass regClass> : MTBUF_m <
1693 op, opName, (outs regClass:$dst),
1694 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1695 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
1696 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1697 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1698 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1701 } // mayLoad = 1, mayStore = 0
1703 //===----------------------------------------------------------------------===//
1705 //===----------------------------------------------------------------------===//
1707 class mubuf <bits<7> si, bits<7> vi = si> {
1708 field bits<7> SI = si;
1709 field bits<7> VI = vi;
1712 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1713 bit IsAddr64 = is_addr64;
1714 string OpName = NAME # suffix;
1717 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1718 MUBUF <outs, ins, "", pattern>,
1719 SIMCInstr<opName, SISubtarget.NONE> {
1722 // dummy fields, so that we can use let statements around multiclasses
1732 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
1734 MUBUF <outs, ins, asm, []>,
1736 SIMCInstr<opName, SISubtarget.SI> {
1740 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
1742 MUBUF <outs, ins, asm, []>,
1744 SIMCInstr<opName, SISubtarget.VI> {
1748 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
1749 list<dag> pattern> {
1751 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1752 MUBUFAddr64Table <0>;
1755 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1758 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1761 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
1762 dag ins, string asm, list<dag> pattern> {
1764 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1765 MUBUFAddr64Table <1>;
1768 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1771 // There is no VI version. If the pseudo is selected, it should be lowered
1772 // for VI appropriately.
1775 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1776 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1780 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
1781 string asm, list<dag> pattern, bit is_return> {
1783 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1784 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
1785 AtomicNoRet<NAME#"_OFFSET", is_return>;
1787 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
1789 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1792 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1796 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
1797 string asm, list<dag> pattern, bit is_return> {
1799 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1800 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
1801 AtomicNoRet<NAME#"_ADDR64", is_return>;
1803 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
1804 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1807 // There is no VI version. If the pseudo is selected, it should be lowered
1808 // for VI appropriately.
1811 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
1812 ValueType vt, SDPatternOperator atomic> {
1814 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1816 // No return variants
1819 defm _ADDR64 : MUBUFAtomicAddr64_m <
1820 op, name#"_addr64", (outs),
1821 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1822 mbuf_offset:$offset, SCSrc_32:$soffset, slc:$slc),
1823 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
1826 defm _OFFSET : MUBUFAtomicOffset_m <
1827 op, name#"_offset", (outs),
1828 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1829 SCSrc_32:$soffset, slc:$slc),
1830 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
1834 // Variant that return values
1835 let glc = 1, Constraints = "$vdata = $vdata_in",
1836 DisableEncoding = "$vdata_in" in {
1838 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
1839 op, name#"_rtn_addr64", (outs rc:$vdata),
1840 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1841 mbuf_offset:$offset, SSrc_32:$soffset, slc:$slc),
1842 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
1844 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
1845 i16:$offset, i1:$slc), vt:$vdata_in))], 1
1848 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
1849 op, name#"_rtn_offset", (outs rc:$vdata),
1850 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1851 SCSrc_32:$soffset, slc:$slc),
1852 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1854 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1855 i1:$slc), vt:$vdata_in))], 1
1860 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1863 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
1864 ValueType load_vt = i32,
1865 SDPatternOperator ld = null_frag> {
1867 let mayLoad = 1, mayStore = 0 in {
1868 let offen = 0, idxen = 0, vaddr = 0 in {
1869 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
1870 (ins SReg_128:$srsrc,
1871 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1872 slc:$slc, tfe:$tfe),
1873 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1874 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1875 i32:$soffset, i16:$offset,
1876 i1:$glc, i1:$slc, i1:$tfe)))]>;
1879 let offen = 1, idxen = 0 in {
1880 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
1881 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1882 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1884 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1887 let offen = 0, idxen = 1 in {
1888 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
1889 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1890 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1891 slc:$slc, tfe:$tfe),
1892 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1895 let offen = 1, idxen = 1 in {
1896 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
1897 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1898 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1899 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1902 let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0 in {
1903 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
1904 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1905 SCSrc_32:$soffset, mbuf_offset:$offset),
1906 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset",
1907 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1908 i64:$vaddr, i32:$soffset,
1914 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
1915 ValueType store_vt, SDPatternOperator st> {
1916 let mayLoad = 0, mayStore = 1 in {
1917 defm : MUBUF_m <op, name, (outs),
1918 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1919 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1921 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1922 "$glc"#"$slc"#"$tfe", []>;
1924 let offen = 0, idxen = 0, vaddr = 0 in {
1925 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
1926 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1927 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1928 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1929 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1930 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
1931 } // offen = 0, idxen = 0, vaddr = 0
1933 let offen = 1, idxen = 0 in {
1934 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
1935 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1936 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1937 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1938 "$glc"#"$slc"#"$tfe", []>;
1939 } // end offen = 1, idxen = 0
1941 let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0 in {
1942 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
1943 (ins vdataClass:$vdata, SReg_128:$srsrc,
1944 VReg_64:$vaddr, SCSrc_32:$soffset,
1945 mbuf_offset:$offset),
1946 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset",
1947 [(st store_vt:$vdata,
1948 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
1949 i32:$soffset, i16:$offset))]>;
1951 } // End mayLoad = 0, mayStore = 1
1954 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1955 FLAT <op, (outs regClass:$vdst),
1956 (ins VReg_64:$addr),
1957 asm#" $vdst, $addr, [M0, FLAT_SCRATCH]", []> {
1965 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1966 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1967 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1980 class MIMG_Mask <string op, int channels> {
1982 int Channels = channels;
1985 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1986 RegisterClass dst_rc,
1987 RegisterClass src_rc> : MIMG <
1989 (outs dst_rc:$vdata),
1990 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1991 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1993 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1994 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1999 let hasPostISelHook = 1;
2002 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
2003 RegisterClass dst_rc,
2005 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
2006 MIMG_Mask<asm#"_V1", channels>;
2007 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
2008 MIMG_Mask<asm#"_V2", channels>;
2009 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
2010 MIMG_Mask<asm#"_V4", channels>;
2013 multiclass MIMG_NoSampler <bits<7> op, string asm> {
2014 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
2015 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2016 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2017 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
2020 class MIMG_Sampler_Helper <bits<7> op, string asm,
2021 RegisterClass dst_rc,
2022 RegisterClass src_rc, int wqm> : MIMG <
2024 (outs dst_rc:$vdata),
2025 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2026 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2027 SReg_256:$srsrc, SReg_128:$ssamp),
2028 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2029 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2033 let hasPostISelHook = 1;
2037 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2038 RegisterClass dst_rc,
2039 int channels, int wqm> {
2040 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2041 MIMG_Mask<asm#"_V1", channels>;
2042 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2043 MIMG_Mask<asm#"_V2", channels>;
2044 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2045 MIMG_Mask<asm#"_V4", channels>;
2046 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2047 MIMG_Mask<asm#"_V8", channels>;
2048 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2049 MIMG_Mask<asm#"_V16", channels>;
2052 multiclass MIMG_Sampler <bits<7> op, string asm> {
2053 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2054 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2055 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2056 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2059 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2060 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2061 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2062 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2063 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2066 class MIMG_Gather_Helper <bits<7> op, string asm,
2067 RegisterClass dst_rc,
2068 RegisterClass src_rc, int wqm> : MIMG <
2070 (outs dst_rc:$vdata),
2071 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2072 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2073 SReg_256:$srsrc, SReg_128:$ssamp),
2074 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2075 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2080 // DMASK was repurposed for GATHER4. 4 components are always
2081 // returned and DMASK works like a swizzle - it selects
2082 // the component to fetch. The only useful DMASK values are
2083 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2084 // (red,red,red,red) etc.) The ISA document doesn't mention
2086 // Therefore, disable all code which updates DMASK by setting these two:
2088 let hasPostISelHook = 0;
2092 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2093 RegisterClass dst_rc,
2094 int channels, int wqm> {
2095 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2096 MIMG_Mask<asm#"_V1", channels>;
2097 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2098 MIMG_Mask<asm#"_V2", channels>;
2099 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2100 MIMG_Mask<asm#"_V4", channels>;
2101 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2102 MIMG_Mask<asm#"_V8", channels>;
2103 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2104 MIMG_Mask<asm#"_V16", channels>;
2107 multiclass MIMG_Gather <bits<7> op, string asm> {
2108 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2109 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2110 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2111 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2114 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2115 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2116 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2117 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2118 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2121 //===----------------------------------------------------------------------===//
2122 // Vector instruction mappings
2123 //===----------------------------------------------------------------------===//
2125 // Maps an opcode in e32 form to its e64 equivalent
2126 def getVOPe64 : InstrMapping {
2127 let FilterClass = "VOP";
2128 let RowFields = ["OpName"];
2129 let ColFields = ["Size"];
2131 let ValueCols = [["8"]];
2134 // Maps an opcode in e64 form to its e32 equivalent
2135 def getVOPe32 : InstrMapping {
2136 let FilterClass = "VOP";
2137 let RowFields = ["OpName"];
2138 let ColFields = ["Size"];
2140 let ValueCols = [["4"]];
2143 // Maps an original opcode to its commuted version
2144 def getCommuteRev : InstrMapping {
2145 let FilterClass = "VOP2_REV";
2146 let RowFields = ["RevOp"];
2147 let ColFields = ["IsOrig"];
2149 let ValueCols = [["0"]];
2152 def getMaskedMIMGOp : InstrMapping {
2153 let FilterClass = "MIMG_Mask";
2154 let RowFields = ["Op"];
2155 let ColFields = ["Channels"];
2157 let ValueCols = [["1"], ["2"], ["3"] ];
2160 // Maps an commuted opcode to its original version
2161 def getCommuteOrig : InstrMapping {
2162 let FilterClass = "VOP2_REV";
2163 let RowFields = ["RevOp"];
2164 let ColFields = ["IsOrig"];
2166 let ValueCols = [["1"]];
2169 def getMCOpcodeGen : InstrMapping {
2170 let FilterClass = "SIMCInstr";
2171 let RowFields = ["PseudoInstr"];
2172 let ColFields = ["Subtarget"];
2173 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2174 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2177 def getAddr64Inst : InstrMapping {
2178 let FilterClass = "MUBUFAddr64Table";
2179 let RowFields = ["OpName"];
2180 let ColFields = ["IsAddr64"];
2182 let ValueCols = [["1"]];
2185 // Maps an atomic opcode to its version with a return value.
2186 def getAtomicRetOp : InstrMapping {
2187 let FilterClass = "AtomicNoRet";
2188 let RowFields = ["NoRetOp"];
2189 let ColFields = ["IsRet"];
2191 let ValueCols = [["1"]];
2194 // Maps an atomic opcode to its returnless version.
2195 def getAtomicNoRetOp : InstrMapping {
2196 let FilterClass = "AtomicNoRet";
2197 let RowFields = ["NoRetOp"];
2198 let ColFields = ["IsRet"];
2200 let ValueCols = [["0"]];
2203 include "SIInstructions.td"
2204 include "CIInstructions.td"
2205 include "VIInstructions.td"