1 //===-- SIInstructions.td - SI Instruction Defintions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This file was originally auto-generated from a GPU register header file and
10 // all the instruction definitions were originally commented out. Instructions
11 // that are not yet supported remain commented out.
12 //===----------------------------------------------------------------------===//
19 def INTERP : InterpSlots;
21 def InterpSlot : Operand<i32> {
22 let PrintMethod = "printInterpSlot";
25 def SendMsgImm : Operand<i32> {
26 let PrintMethod = "printSendMsg";
29 def isSI : Predicate<"Subtarget.getGeneration() "
30 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">;
32 def WAIT_FLAG : InstFlag<"printWaitFlag">;
34 let Predicates = [isSI] in {
36 let neverHasSideEffects = 1 in {
38 let isMoveImm = 1 in {
39 def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>;
40 def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>;
41 def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>;
42 def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>;
43 } // End isMoveImm = 1
45 def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32", []>;
46 def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", []>;
47 def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>;
48 def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>;
49 def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>;
50 def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>;
51 } // End neverHasSideEffects = 1
53 ////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>;
54 ////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>;
55 ////def S_BCNT1_I32_B32 : SOP1_BCNT1 <0x0000000f, "S_BCNT1_I32_B32", []>;
56 ////def S_BCNT1_I32_B64 : SOP1_BCNT1 <0x00000010, "S_BCNT1_I32_B64", []>;
57 ////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>;
58 ////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>;
59 ////def S_FF1_I32_B32 : SOP1_FF1 <0x00000013, "S_FF1_I32_B32", []>;
60 ////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>;
61 //def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", []>;
62 //def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>;
63 def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>;
64 //def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>;
65 //def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8", []>;
66 //def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16", []>;
67 ////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>;
68 ////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>;
69 ////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>;
70 ////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>;
71 def S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>;
72 def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>;
73 def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>;
74 def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>;
76 let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in {
78 def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>;
79 def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>;
80 def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>;
81 def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>;
82 def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>;
83 def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>;
84 def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>;
85 def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>;
87 } // End hasSideEffects = 1
89 def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>;
90 def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>;
91 def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>;
92 def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>;
93 def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>;
94 def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>;
95 //def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>;
96 def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>;
97 def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>;
98 def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>;
99 def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>;
100 def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>;
103 This instruction is disabled for now until we can figure out how to teach
104 the instruction selector to correctly use the S_CMP* vs V_CMP*
107 When this instruction is enabled the code generator sometimes produces this
110 SCC = S_CMPK_EQ_I32 SGPR0, imm
112 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
114 def S_CMPK_EQ_I32 : SOPK <
115 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1),
117 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))]
121 let isCompare = 1 in {
122 def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>;
123 def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>;
124 def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>;
125 def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>;
126 def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>;
127 def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>;
128 def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>;
129 def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>;
130 def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>;
131 def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>;
132 def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>;
133 } // End isCompare = 1
135 let Defs = [SCC], isCommutable = 1 in {
136 def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>;
137 def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>;
140 //def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>;
141 def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>;
142 def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>;
143 def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>;
144 //def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>;
145 //def EXP : EXP_ <0x00000000, "EXP", []>;
147 let isCompare = 1 in {
149 defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">;
150 defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_OLT>;
151 defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", f32, COND_OEQ>;
152 defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", f32, COND_OLE>;
153 defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", f32, COND_OGT>;
154 defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32">;
155 defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", f32, COND_OGE>;
156 defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32", f32, COND_O>;
157 defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32", f32, COND_UO>;
158 defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32">;
159 defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32">;
160 defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32">;
161 defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32">;
162 defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", f32, COND_UNE>;
163 defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">;
164 defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">;
166 let hasSideEffects = 1, Defs = [EXEC] in {
168 defm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32">;
169 defm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32">;
170 defm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32">;
171 defm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32">;
172 defm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32">;
173 defm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32">;
174 defm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32">;
175 defm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32">;
176 defm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32">;
177 defm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32">;
178 defm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32">;
179 defm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32">;
180 defm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32">;
181 defm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32">;
182 defm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32">;
183 defm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32">;
185 } // End hasSideEffects = 1, Defs = [EXEC]
187 defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">;
188 defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64", f64, COND_OLT>;
189 defm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64", f64, COND_OEQ>;
190 defm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64", f64, COND_OLE>;
191 defm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64", f64, COND_OGT>;
192 defm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64">;
193 defm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64", f64, COND_OGE>;
194 defm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64", f64, COND_O>;
195 defm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64", f64, COND_UO>;
196 defm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64">;
197 defm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64">;
198 defm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64">;
199 defm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64">;
200 defm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64", f64, COND_UNE>;
201 defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">;
202 defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">;
204 let hasSideEffects = 1, Defs = [EXEC] in {
206 defm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64">;
207 defm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64">;
208 defm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64">;
209 defm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64">;
210 defm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64">;
211 defm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64">;
212 defm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64">;
213 defm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64">;
214 defm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64">;
215 defm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64">;
216 defm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64">;
217 defm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64">;
218 defm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64">;
219 defm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64">;
220 defm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64">;
221 defm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64">;
223 } // End hasSideEffects = 1, Defs = [EXEC]
225 defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">;
226 defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">;
227 defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32">;
228 defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32">;
229 defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32">;
230 defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32">;
231 defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32">;
232 defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32">;
233 defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32">;
234 defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32">;
235 defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32">;
236 defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32">;
237 defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32">;
238 defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">;
239 defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">;
240 defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">;
242 let hasSideEffects = 1, Defs = [EXEC] in {
244 defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32">;
245 defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32">;
246 defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32">;
247 defm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32">;
248 defm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32">;
249 defm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32">;
250 defm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32">;
251 defm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32">;
252 defm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32">;
253 defm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32">;
254 defm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32">;
255 defm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32">;
256 defm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32">;
257 defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32">;
258 defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32">;
259 defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32">;
261 } // End hasSideEffects = 1, Defs = [EXEC]
263 defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">;
264 defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">;
265 defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">;
266 defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64">;
267 defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64">;
268 defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64">;
269 defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64">;
270 defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64">;
271 defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64">;
272 defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64">;
273 defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64">;
274 defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64">;
275 defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64">;
276 defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">;
277 defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">;
278 defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">;
280 let hasSideEffects = 1, Defs = [EXEC] in {
282 defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">;
283 defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">;
284 defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">;
285 defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64">;
286 defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64">;
287 defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64">;
288 defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64">;
289 defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64">;
290 defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64">;
291 defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64">;
292 defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64">;
293 defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64">;
294 defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64">;
295 defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">;
296 defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">;
297 defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">;
299 } // End hasSideEffects = 1, Defs = [EXEC]
301 defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">;
302 defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_SLT>;
303 defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>;
304 defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", i32, COND_SLE>;
305 defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", i32, COND_SGT>;
306 defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", i32, COND_NE>;
307 defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_SGE>;
308 defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">;
310 let hasSideEffects = 1, Defs = [EXEC] in {
312 defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32">;
313 defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32">;
314 defm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32">;
315 defm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32">;
316 defm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32">;
317 defm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32">;
318 defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32">;
319 defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32">;
321 } // End hasSideEffects = 1, Defs = [EXEC]
323 defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">;
324 defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64", i64, COND_SLT>;
325 defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64", i64, COND_EQ>;
326 defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64", i64, COND_SLE>;
327 defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64", i64, COND_SGT>;
328 defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64", i64, COND_NE>;
329 defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64", i64, COND_SGE>;
330 defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">;
332 let hasSideEffects = 1, Defs = [EXEC] in {
334 defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64">;
335 defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64">;
336 defm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64">;
337 defm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64">;
338 defm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64">;
339 defm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64">;
340 defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64">;
341 defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64">;
343 } // End hasSideEffects = 1, Defs = [EXEC]
345 defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">;
346 defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32", i32, COND_ULT>;
347 defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32", i32, COND_EQ>;
348 defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32", i32, COND_ULE>;
349 defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32", i32, COND_UGT>;
350 defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32", i32, COND_NE>;
351 defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32", i32, COND_UGE>;
352 defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">;
354 let hasSideEffects = 1, Defs = [EXEC] in {
356 defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32">;
357 defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32">;
358 defm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32">;
359 defm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32">;
360 defm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32">;
361 defm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32">;
362 defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32">;
363 defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32">;
365 } // End hasSideEffects = 1, Defs = [EXEC]
367 defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">;
368 defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64", i64, COND_ULT>;
369 defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64", i64, COND_EQ>;
370 defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64", i64, COND_ULE>;
371 defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64", i64, COND_UGT>;
372 defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64", i64, COND_NE>;
373 defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64", i64, COND_UGE>;
374 defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">;
376 let hasSideEffects = 1, Defs = [EXEC] in {
378 defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64">;
379 defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64">;
380 defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64">;
381 defm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64">;
382 defm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64">;
383 defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64">;
384 defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64">;
385 defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64">;
387 } // End hasSideEffects = 1, Defs = [EXEC]
389 defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">;
391 let hasSideEffects = 1, Defs = [EXEC] in {
392 defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">;
393 } // End hasSideEffects = 1, Defs = [EXEC]
395 defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">;
397 let hasSideEffects = 1, Defs = [EXEC] in {
398 defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">;
399 } // End hasSideEffects = 1, Defs = [EXEC]
401 } // End isCompare = 1
403 def DS_ADD_U32_RTN : DS_1A1D_RET <0x20, "DS_ADD_U32_RTN", VReg_32>;
404 def DS_SUB_U32_RTN : DS_1A1D_RET <0x21, "DS_SUB_U32_RTN", VReg_32>;
405 def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>;
406 def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "DS_WRITE_B8", VReg_32>;
407 def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "DS_WRITE_B16", VReg_32>;
408 def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>;
409 def DS_READ_I8 : DS_Load_Helper <0x00000039, "DS_READ_I8", VReg_32>;
410 def DS_READ_U8 : DS_Load_Helper <0x0000003a, "DS_READ_U8", VReg_32>;
411 def DS_READ_I16 : DS_Load_Helper <0x0000003b, "DS_READ_I16", VReg_32>;
412 def DS_READ_U16 : DS_Load_Helper <0x0000003c, "DS_READ_U16", VReg_32>;
414 //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>;
415 //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>;
416 //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>;
417 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>;
418 //def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>;
419 //def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>;
420 //def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>;
421 //def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>;
422 defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <0x00000008, "BUFFER_LOAD_UBYTE", VReg_32>;
423 defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <0x00000009, "BUFFER_LOAD_SBYTE", VReg_32>;
424 defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <0x0000000a, "BUFFER_LOAD_USHORT", VReg_32>;
425 defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32>;
426 defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <0x0000000c, "BUFFER_LOAD_DWORD", VReg_32>;
427 defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64>;
428 defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128>;
430 def BUFFER_STORE_BYTE : MUBUF_Store_Helper <
431 0x00000018, "BUFFER_STORE_BYTE", VReg_32
434 def BUFFER_STORE_SHORT : MUBUF_Store_Helper <
435 0x0000001a, "BUFFER_STORE_SHORT", VReg_32
438 def BUFFER_STORE_DWORD : MUBUF_Store_Helper <
439 0x0000001c, "BUFFER_STORE_DWORD", VReg_32
442 def BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper <
443 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64
446 def BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper <
447 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128
449 //def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>;
450 //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>;
451 //def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>;
452 //def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>;
453 //def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>;
454 //def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>;
455 //def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>;
456 //def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>;
457 //def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>;
458 //def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>;
459 //def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>;
460 //def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>;
461 //def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>;
462 //def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>;
463 //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>;
464 //def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>;
465 //def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>;
466 //def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>;
467 //def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>;
468 //def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>;
469 //def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>;
470 //def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>;
471 //def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>;
472 //def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>;
473 //def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>;
474 //def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>;
475 //def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>;
476 //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>;
477 //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>;
478 //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>;
479 //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>;
480 //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>;
481 //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>;
482 //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>;
483 //def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>;
484 //def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>;
485 //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>;
486 //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>;
487 //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>;
488 def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>;
489 def TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "TBUFFER_STORE_FORMAT_X", VReg_32>;
490 def TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FORMAT_XY", VReg_64>;
491 def TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>;
492 def TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>;
496 // We are using the SGPR_32 and not the SReg_32 register class for 32-bit
497 // SMRD instructions, because the SGPR_32 register class does not include M0
498 // and writing to M0 from an SMRD instruction will hang the GPU.
499 defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SGPR_32>;
500 defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>;
501 defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>;
502 defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>;
503 defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>;
505 defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
506 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SGPR_32
509 defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
510 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64
513 defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper <
514 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128
517 defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <
518 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256
521 defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
522 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512
527 //def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>;
528 //def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>;
529 defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "IMAGE_LOAD">;
530 defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "IMAGE_LOAD_MIP">;
531 //def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>;
532 //def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>;
533 //def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>;
534 //def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>;
535 //def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>;
536 //def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>;
537 //def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>;
538 //def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>;
539 defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "IMAGE_GET_RESINFO">;
540 //def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>;
541 //def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>;
542 //def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>;
543 //def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>;
544 //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>;
545 //def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>;
546 //def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>;
547 //def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>;
548 //def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>;
549 //def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>;
550 //def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>;
551 //def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>;
552 //def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>;
553 //def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>;
554 //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>;
555 //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>;
556 //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>;
557 defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">;
558 //def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>;
559 defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">;
560 //def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>;
561 defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">;
562 defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">;
563 //def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>;
564 //def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>;
565 defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">;
566 //def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>;
567 defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">;
568 //def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>;
569 defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">;
570 defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">;
571 //def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>;
572 //def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>;
573 //def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>;
574 //def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>;
575 //def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>;
576 //def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>;
577 //def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>;
578 //def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>;
579 //def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>;
580 //def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>;
581 //def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>;
582 //def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>;
583 //def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>;
584 //def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>;
585 //def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>;
586 //def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>;
587 //def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>;
588 //def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>;
589 //def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>;
590 //def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>;
591 //def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>;
592 //def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>;
593 //def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>;
594 //def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>;
595 //def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>;
596 //def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>;
597 //def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>;
598 //def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>;
599 //def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>;
600 //def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>;
601 //def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>;
602 //def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>;
603 //def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>;
604 //def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>;
605 //def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>;
606 //def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>;
607 //def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>;
608 //def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>;
609 //def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>;
610 //def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>;
611 //def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>;
612 //def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>;
613 //def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>;
614 //def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>;
615 //def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>;
616 //def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>;
617 //def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>;
618 //def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>;
619 //def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>;
620 //def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>;
621 //def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>;
622 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>;
623 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>;
624 //def V_NOP : VOP1_ <0x00000000, "V_NOP", []>;
627 let neverHasSideEffects = 1, isMoveImm = 1 in {
628 defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>;
629 } // End neverHasSideEffects = 1, isMoveImm = 1
631 defm V_READFIRSTLANE_B32 : VOP1_32 <0x00000002, "V_READFIRSTLANE_B32", []>;
632 defm V_CVT_I32_F64 : VOP1_32_64 <0x00000003, "V_CVT_I32_F64",
633 [(set i32:$dst, (fp_to_sint f64:$src0))]
635 defm V_CVT_F64_I32 : VOP1_64_32 <0x00000004, "V_CVT_F64_I32",
636 [(set f64:$dst, (sint_to_fp i32:$src0))]
638 defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32",
639 [(set f32:$dst, (sint_to_fp i32:$src0))]
641 defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32",
642 [(set f32:$dst, (uint_to_fp i32:$src0))]
644 defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32",
645 [(set i32:$dst, (fp_to_uint f32:$src0))]
647 defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32",
648 [(set i32:$dst, (fp_to_sint f32:$src0))]
650 defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>;
651 ////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>;
652 //defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>;
653 //defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>;
654 //defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>;
655 //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>;
656 defm V_CVT_F32_F64 : VOP1_32_64 <0x0000000f, "V_CVT_F32_F64",
657 [(set f32:$dst, (fround f64:$src0))]
659 defm V_CVT_F64_F32 : VOP1_64_32 <0x00000010, "V_CVT_F64_F32",
660 [(set f64:$dst, (fextend f32:$src0))]
662 //defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0", []>;
663 //defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1", []>;
664 //defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2", []>;
665 //defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", []>;
666 //defm V_CVT_U32_F64 : VOP1_32 <0x00000015, "V_CVT_U32_F64", []>;
667 //defm V_CVT_F64_U32 : VOP1_64 <0x00000016, "V_CVT_F64_U32", []>;
668 defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32",
669 [(set f32:$dst, (AMDGPUfract f32:$src0))]
671 defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32",
672 [(set f32:$dst, (int_AMDGPU_trunc f32:$src0))]
674 defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32",
675 [(set f32:$dst, (fceil f32:$src0))]
677 defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32",
678 [(set f32:$dst, (frint f32:$src0))]
680 defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32",
681 [(set f32:$dst, (ffloor f32:$src0))]
683 defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32",
684 [(set f32:$dst, (fexp2 f32:$src0))]
686 defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>;
687 defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32",
688 [(set f32:$dst, (flog2 f32:$src0))]
690 defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>;
691 defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>;
692 defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32",
693 [(set f32:$dst, (fdiv FP_ONE, f32:$src0))]
695 defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>;
696 defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>;
697 defm V_RSQ_LEGACY_F32 : VOP1_32 <
698 0x0000002d, "V_RSQ_LEGACY_F32",
699 [(set f32:$dst, (int_AMDGPU_rsq f32:$src0))]
701 defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32", []>;
702 defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64",
703 [(set f64:$dst, (fdiv FP_ONE, f64:$src0))]
705 defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>;
706 defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64", []>;
707 defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>;
708 defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32",
709 [(set f32:$dst, (fsqrt f32:$src0))]
711 defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64",
712 [(set f64:$dst, (fsqrt f64:$src0))]
714 defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>;
715 defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>;
716 defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>;
717 defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>;
718 defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>;
719 defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>;
720 defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>;
721 //defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>;
722 defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>;
723 defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>;
724 //defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>;
725 defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>;
726 //def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>;
727 defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>;
728 defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>;
729 defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>;
731 def V_INTERP_P1_F32 : VINTRP <
734 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
735 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]",
737 let DisableEncoding = "$m0";
740 def V_INTERP_P2_F32 : VINTRP <
743 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
744 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]",
747 let Constraints = "$src0 = $dst";
748 let DisableEncoding = "$src0,$m0";
752 def V_INTERP_MOV_F32 : VINTRP <
755 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
756 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]",
758 let DisableEncoding = "$m0";
761 //def S_NOP : SOPP_ <0x00000000, "S_NOP", []>;
763 let isTerminator = 1 in {
765 def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM",
772 let isBranch = 1 in {
773 def S_BRANCH : SOPP <
774 0x00000002, (ins brtarget:$target), "S_BRANCH $target",
779 let DisableEncoding = "$scc" in {
780 def S_CBRANCH_SCC0 : SOPP <
781 0x00000004, (ins brtarget:$target, SCCReg:$scc),
782 "S_CBRANCH_SCC0 $target", []
784 def S_CBRANCH_SCC1 : SOPP <
785 0x00000005, (ins brtarget:$target, SCCReg:$scc),
786 "S_CBRANCH_SCC1 $target",
789 } // End DisableEncoding = "$scc"
791 def S_CBRANCH_VCCZ : SOPP <
792 0x00000006, (ins brtarget:$target, VCCReg:$vcc),
793 "S_CBRANCH_VCCZ $target",
796 def S_CBRANCH_VCCNZ : SOPP <
797 0x00000007, (ins brtarget:$target, VCCReg:$vcc),
798 "S_CBRANCH_VCCNZ $target",
802 let DisableEncoding = "$exec" in {
803 def S_CBRANCH_EXECZ : SOPP <
804 0x00000008, (ins brtarget:$target, EXECReg:$exec),
805 "S_CBRANCH_EXECZ $target",
808 def S_CBRANCH_EXECNZ : SOPP <
809 0x00000009, (ins brtarget:$target, EXECReg:$exec),
810 "S_CBRANCH_EXECNZ $target",
813 } // End DisableEncoding = "$exec"
816 } // End isBranch = 1
817 } // End isTerminator = 1
819 let hasSideEffects = 1 in {
820 def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER",
821 [(int_AMDGPU_barrier_local)]
830 def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16",
833 //def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>;
834 //def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>;
835 //def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>;
837 let Uses = [EXEC] in {
838 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "S_SENDMSG $simm16",
839 [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)]
841 let DisableEncoding = "$m0";
843 } // End Uses = [EXEC]
845 //def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>;
846 //def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>;
847 //def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>;
848 //def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>;
849 //def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>;
850 //def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
851 } // End hasSideEffects
853 def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
854 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc),
855 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]",
858 let DisableEncoding = "$vcc";
861 def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst),
862 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2,
863 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
864 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg",
865 [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))]
868 //f32 pattern for V_CNDMASK_B32_e64
870 (f32 (select i1:$src2, f32:$src1, f32:$src0)),
871 (V_CNDMASK_B32_e64 $src0, $src1, $src2)
875 (i32 (trunc i64:$val)),
876 (EXTRACT_SUBREG $val, sub0)
879 //use two V_CNDMASK_B32_e64 instructions for f64
881 (f64 (select i1:$src2, f64:$src1, f64:$src0)),
882 (INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
883 (V_CNDMASK_B32_e64 (EXTRACT_SUBREG $src0, sub0),
884 (EXTRACT_SUBREG $src1, sub0),
886 (V_CNDMASK_B32_e64 (EXTRACT_SUBREG $src0, sub1),
887 (EXTRACT_SUBREG $src1, sub1),
891 def V_READLANE_B32 : VOP2 <
893 (outs SReg_32:$vdst),
894 (ins VReg_32:$src0, SSrc_32:$vsrc1),
895 "V_READLANE_B32 $vdst, $src0, $vsrc1",
899 def V_WRITELANE_B32 : VOP2 <
901 (outs VReg_32:$vdst),
902 (ins SReg_32:$src0, SSrc_32:$vsrc1),
903 "V_WRITELANE_B32 $vdst, $src0, $vsrc1",
907 let isCommutable = 1 in {
908 defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32",
909 [(set f32:$dst, (fadd f32:$src0, f32:$src1))]
912 defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32",
913 [(set f32:$dst, (fsub f32:$src0, f32:$src1))]
915 defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", [], "V_SUB_F32">;
916 } // End isCommutable = 1
918 defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>;
920 let isCommutable = 1 in {
922 defm V_MUL_LEGACY_F32 : VOP2_32 <
923 0x00000007, "V_MUL_LEGACY_F32",
924 [(set f32:$dst, (int_AMDGPU_mul f32:$src0, f32:$src1))]
927 defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32",
928 [(set f32:$dst, (fmul f32:$src0, f32:$src1))]
932 defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24",
933 [(set i32:$dst, (mul I24:$src0, I24:$src1))]
935 //defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>;
936 defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24",
937 [(set i32:$dst, (mul U24:$src0, U24:$src1))]
939 //defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>;
942 defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32",
943 [(set f32:$dst, (AMDGPUfmin f32:$src0, f32:$src1))]
946 defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32",
947 [(set f32:$dst, (AMDGPUfmax f32:$src0, f32:$src1))]
950 defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>;
951 defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>;
952 defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32",
953 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]
955 defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32",
956 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]
958 defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32",
959 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]
961 defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32",
962 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]
965 defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32",
966 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
968 defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">;
970 defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32",
971 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
973 defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">;
975 let hasPostISelHook = 1 in {
977 defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32",
978 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
982 defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">;
984 defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32",
985 [(set i32:$dst, (and i32:$src0, i32:$src1))]
987 defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32",
988 [(set i32:$dst, (or i32:$src0, i32:$src1))]
990 defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32",
991 [(set i32:$dst, (xor i32:$src0, i32:$src1))]
994 } // End isCommutable = 1
996 defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32", []>;
997 defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>;
998 defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>;
999 defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>;
1000 //defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>;
1001 defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>;
1002 defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>;
1004 let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC
1005 // No patterns so that the scalar instructions are always selected.
1006 // The scalar versions will be replaced with vector when needed later.
1007 defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", []>;
1008 defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", []>;
1009 defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], "V_SUB_I32">;
1011 let Uses = [VCC] in { // Carry-in comes from VCC
1012 defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", []>;
1013 defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", []>;
1014 defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], "V_SUBB_U32">;
1015 } // End Uses = [VCC]
1016 } // End isCommutable = 1, Defs = [VCC]
1018 defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>;
1019 ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>;
1020 ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>;
1021 ////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>;
1022 defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32",
1023 [(set i32:$dst, (int_SI_packf16 f32:$src0, f32:$src1))]
1025 ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>;
1026 ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>;
1027 def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32", []>;
1028 def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32", []>;
1029 def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32", []>;
1030 def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32", []>;
1031 def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32", []>;
1032 def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32", []>;
1033 def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32", []>;
1034 def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32", []>;
1035 def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32", []>;
1036 def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32", []>;
1037 def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32", []>;
1038 def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32", []>;
1039 ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>;
1040 ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>;
1041 ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>;
1042 ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>;
1043 //def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>;
1045 let neverHasSideEffects = 1 in {
1047 def V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>;
1048 def V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", []>;
1049 def V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24",
1050 [(set i32:$dst, (add (mul I24:$src0, I24:$src1), i32:$src2))]
1052 def V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24",
1053 [(set i32:$dst, (add (mul U24:$src0, U24:$src1), i32:$src2))]
1056 } // End neverHasSideEffects
1057 def V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>;
1058 def V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>;
1059 def V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>;
1060 def V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>;
1061 def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", []>;
1062 def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", []>;
1063 def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", []>;
1064 defm : BFIPatterns <V_BFI_B32>;
1065 def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32",
1066 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))]
1068 def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64",
1069 [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
1071 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>;
1072 def V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>;
1073 def : ROTRPattern <V_ALIGNBIT_B32>;
1075 def V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>;
1076 def V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>;
1077 ////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>;
1078 ////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>;
1079 ////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>;
1080 ////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>;
1081 ////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>;
1082 ////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>;
1083 ////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>;
1084 ////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>;
1085 ////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>;
1086 //def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>;
1087 //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>;
1088 //def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>;
1089 def V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>;
1090 ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>;
1091 def V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>;
1092 def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>;
1094 def V_LSHL_B64 : VOP3_64_Shift <0x00000161, "V_LSHL_B64",
1095 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
1097 def V_LSHR_B64 : VOP3_64_Shift <0x00000162, "V_LSHR_B64",
1098 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
1100 def V_ASHR_I64 : VOP3_64_Shift <0x00000163, "V_ASHR_I64",
1101 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
1104 let isCommutable = 1 in {
1106 def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>;
1107 def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>;
1108 def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>;
1109 def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>;
1111 } // isCommutable = 1
1114 (fadd f64:$src0, f64:$src1),
1115 (V_ADD_F64 $src0, $src1, (i64 0))
1119 (fmul f64:$src0, f64:$src1),
1120 (V_MUL_F64 $src0, $src1, (i64 0))
1123 def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>;
1125 let isCommutable = 1 in {
1127 def V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>;
1128 def V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>;
1129 def V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>;
1130 def V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>;
1132 } // isCommutable = 1
1135 (mul i32:$src0, i32:$src1),
1136 (V_MUL_LO_I32 $src0, $src1, (i32 0))
1140 (mulhu i32:$src0, i32:$src1),
1141 (V_MUL_HI_U32 $src0, $src1, (i32 0))
1145 (mulhs i32:$src0, i32:$src1),
1146 (V_MUL_HI_I32 $src0, $src1, (i32 0))
1149 def V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>;
1150 def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>;
1151 def V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>;
1152 def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>;
1153 //def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>;
1154 //def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>;
1155 //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>;
1156 def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>;
1158 let Defs = [SCC] in { // Carry out goes to SCC
1159 let isCommutable = 1 in {
1160 def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>;
1161 def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32",
1162 [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))]
1164 } // End isCommutable = 1
1166 def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>;
1167 def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32",
1168 [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))]
1171 let Uses = [SCC] in { // Carry in comes from SCC
1172 let isCommutable = 1 in {
1173 def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32",
1174 [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
1175 } // End isCommutable = 1
1177 def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32",
1178 [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
1179 } // End Uses = [SCC]
1180 } // End Defs = [SCC]
1182 def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32", []>;
1183 def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32", []>;
1184 def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32", []>;
1185 def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32", []>;
1187 def S_CSELECT_B32 : SOP2 <
1188 0x0000000a, (outs SReg_32:$dst),
1189 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32",
1193 def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>;
1195 def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32", []>;
1197 def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64",
1198 [(set i64:$dst, (and i64:$src0, i64:$src1))]
1202 (i1 (and i1:$src0, i1:$src1)),
1203 (S_AND_B64 $src0, $src1)
1206 def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32", []>;
1207 def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64", []>;
1209 (i1 (or i1:$src0, i1:$src1)),
1210 (S_OR_B64 $src0, $src1)
1212 def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32", []>;
1213 def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64",
1214 [(set i1:$dst, (xor i1:$src0, i1:$src1))]
1216 def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>;
1217 def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>;
1218 def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>;
1219 def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>;
1220 def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>;
1221 def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>;
1222 def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>;
1223 def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>;
1224 def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>;
1225 def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>;
1227 // Use added complexity so these patterns are preferred to the VALU patterns.
1228 let AddedComplexity = 1 in {
1230 def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32",
1231 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
1233 def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "S_LSHL_B64",
1234 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
1236 def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32",
1237 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
1239 def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "S_LSHR_B64",
1240 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
1242 def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32",
1243 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
1245 def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64",
1246 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
1249 } // End AddedComplexity = 1
1251 def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>;
1252 def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>;
1253 def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>;
1254 def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>;
1255 def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>;
1256 def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>;
1257 def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>;
1258 //def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>;
1259 def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>;
1261 let isCodeGenOnly = 1, isPseudo = 1 in {
1263 def LOAD_CONST : AMDGPUShaderInst <
1266 "LOAD_CONST $dst, $src",
1267 [(set GPRF32:$dst, (int_AMDGPU_load_const imm:$src))]
1270 // SI pseudo instructions. These are used by the CFG structurizer pass
1271 // and should be lowered to ISA instructions prior to codegen.
1273 let mayLoad = 1, mayStore = 1, hasSideEffects = 1,
1274 Uses = [EXEC], Defs = [EXEC] in {
1276 let isBranch = 1, isTerminator = 1 in {
1278 def SI_IF : InstSI <
1279 (outs SReg_64:$dst),
1280 (ins SReg_64:$vcc, brtarget:$target),
1281 "SI_IF $dst, $vcc, $target",
1282 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))]
1285 def SI_ELSE : InstSI <
1286 (outs SReg_64:$dst),
1287 (ins SReg_64:$src, brtarget:$target),
1288 "SI_ELSE $dst, $src, $target",
1289 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]> {
1291 let Constraints = "$src = $dst";
1294 def SI_LOOP : InstSI <
1296 (ins SReg_64:$saved, brtarget:$target),
1297 "SI_LOOP $saved, $target",
1298 [(int_SI_loop i64:$saved, bb:$target)]
1301 } // end isBranch = 1, isTerminator = 1
1303 def SI_BREAK : InstSI <
1304 (outs SReg_64:$dst),
1306 "SI_ELSE $dst, $src",
1307 [(set i64:$dst, (int_SI_break i64:$src))]
1310 def SI_IF_BREAK : InstSI <
1311 (outs SReg_64:$dst),
1312 (ins SReg_64:$vcc, SReg_64:$src),
1313 "SI_IF_BREAK $dst, $vcc, $src",
1314 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))]
1317 def SI_ELSE_BREAK : InstSI <
1318 (outs SReg_64:$dst),
1319 (ins SReg_64:$src0, SReg_64:$src1),
1320 "SI_ELSE_BREAK $dst, $src0, $src1",
1321 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))]
1324 def SI_END_CF : InstSI <
1326 (ins SReg_64:$saved),
1328 [(int_SI_end_cf i64:$saved)]
1331 def SI_KILL : InstSI <
1335 [(int_AMDGPU_kill f32:$src)]
1338 } // end mayLoad = 1, mayStore = 1, hasSideEffects = 1
1339 // Uses = [EXEC], Defs = [EXEC]
1341 let Uses = [EXEC], Defs = [EXEC,VCC,M0] in {
1343 //defm SI_ : RegisterLoadStore <VReg_32, FRAMEri, ADDRIndirect>;
1345 let UseNamedOperandTable = 1 in {
1347 def SI_RegisterLoad : AMDGPUShaderInst <
1348 (outs VReg_32:$dst, SReg_64:$temp),
1349 (ins FRAMEri32:$addr, i32imm:$chan),
1352 let isRegisterLoad = 1;
1356 class SIRegStore<dag outs> : AMDGPUShaderInst <
1358 (ins VReg_32:$val, FRAMEri32:$addr, i32imm:$chan),
1361 let isRegisterStore = 1;
1365 let usesCustomInserter = 1 in {
1366 def SI_RegisterStorePseudo : SIRegStore<(outs)>;
1367 } // End usesCustomInserter = 1
1368 def SI_RegisterStore : SIRegStore<(outs SReg_64:$temp)>;
1371 } // End UseNamedOperandTable = 1
1373 def SI_INDIRECT_SRC : InstSI <
1374 (outs VReg_32:$dst, SReg_64:$temp),
1375 (ins unknown:$src, VSrc_32:$idx, i32imm:$off),
1376 "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off",
1380 class SI_INDIRECT_DST<RegisterClass rc> : InstSI <
1381 (outs rc:$dst, SReg_64:$temp),
1382 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val),
1383 "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val",
1386 let Constraints = "$src = $dst";
1389 def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VReg_32>;
1390 def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
1391 def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
1392 def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
1393 def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
1395 } // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0]
1397 let usesCustomInserter = 1 in {
1399 // This pseudo instruction takes a pointer as input and outputs a resource
1400 // constant that can be used with the ADDR64 MUBUF instructions.
1401 def SI_ADDR64_RSRC : InstSI <
1402 (outs SReg_128:$srsrc),
1407 def V_SUB_F64 : InstSI <
1408 (outs VReg_64:$dst),
1409 (ins VReg_64:$src0, VReg_64:$src1),
1410 "V_SUB_F64 $dst, $src0, $src1",
1414 } // end usesCustomInserter
1416 } // end IsCodeGenOnly, isPseudo
1419 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2),
1420 (V_CNDMASK_B32_e64 $src2, $src1, (V_CMP_GT_F32_e64 0, $src0))
1425 (SI_KILL (V_MOV_B32_e32 0xbf800000))
1428 /* int_SI_vs_load_input */
1430 (SIload_input i128:$tlst, IMM12bit:$attr_offset, i32:$buf_idx_vgpr),
1431 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0)
1436 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
1437 f32:$src0, f32:$src1, f32:$src2, f32:$src3),
1438 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
1439 $src0, $src1, $src2, $src3)
1443 (f64 (fsub f64:$src0, f64:$src1)),
1444 (V_SUB_F64 $src0, $src1)
1447 /********** ======================= **********/
1448 /********** Image sampling patterns **********/
1449 /********** ======================= **********/
1451 /* SIsample for simple 1D texture lookup */
1453 (SIsample i32:$addr, v32i8:$rsrc, i128:$sampler, imm),
1454 (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1457 class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1458 (name vt:$addr, v32i8:$rsrc, i128:$sampler, imm),
1459 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1462 class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1463 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_RECT),
1464 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1467 class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1468 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_ARRAY),
1469 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1472 class SampleShadowPattern<SDNode name, MIMG opcode,
1473 ValueType vt> : Pat <
1474 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_SHADOW),
1475 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1478 class SampleShadowArrayPattern<SDNode name, MIMG opcode,
1479 ValueType vt> : Pat <
1480 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_SHADOW_ARRAY),
1481 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1484 /* SIsample* for texture lookups consuming more address parameters */
1485 multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l,
1486 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b,
1487 MIMG sample_d, MIMG sample_c_d, ValueType addr_type> {
1488 def : SamplePattern <SIsample, sample, addr_type>;
1489 def : SampleRectPattern <SIsample, sample, addr_type>;
1490 def : SampleArrayPattern <SIsample, sample, addr_type>;
1491 def : SampleShadowPattern <SIsample, sample_c, addr_type>;
1492 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>;
1494 def : SamplePattern <SIsamplel, sample_l, addr_type>;
1495 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>;
1496 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>;
1497 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>;
1499 def : SamplePattern <SIsampleb, sample_b, addr_type>;
1500 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>;
1501 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>;
1502 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>;
1504 def : SamplePattern <SIsampled, sample_d, addr_type>;
1505 def : SampleArrayPattern <SIsampled, sample_d, addr_type>;
1506 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>;
1507 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>;
1510 defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2,
1511 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2,
1512 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2,
1513 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2,
1515 defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4,
1516 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4,
1517 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4,
1518 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4,
1520 defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8,
1521 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8,
1522 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8,
1523 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8,
1525 defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16,
1526 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16,
1527 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16,
1528 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16,
1531 /* int_SI_imageload for texture fetches consuming varying address parameters */
1532 class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1533 (name addr_type:$addr, v32i8:$rsrc, imm),
1534 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
1537 class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1538 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY),
1539 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
1542 class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1543 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA),
1544 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
1547 class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1548 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA),
1549 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
1552 multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> {
1553 def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>;
1554 def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>;
1557 multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> {
1558 def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>;
1559 def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>;
1562 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V2, v2i32>;
1563 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V4, v4i32>;
1565 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V2, v2i32>;
1566 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V4, v4i32>;
1568 /* Image resource information */
1570 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm),
1571 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1575 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY),
1576 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1580 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA),
1581 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1584 /********** ============================================ **********/
1585 /********** Extraction, Insertion, Building and Casting **********/
1586 /********** ============================================ **********/
1588 foreach Index = 0-2 in {
1589 def Extract_Element_v2i32_#Index : Extract_Element <
1590 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
1592 def Insert_Element_v2i32_#Index : Insert_Element <
1593 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
1596 def Extract_Element_v2f32_#Index : Extract_Element <
1597 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
1599 def Insert_Element_v2f32_#Index : Insert_Element <
1600 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
1604 foreach Index = 0-3 in {
1605 def Extract_Element_v4i32_#Index : Extract_Element <
1606 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
1608 def Insert_Element_v4i32_#Index : Insert_Element <
1609 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
1612 def Extract_Element_v4f32_#Index : Extract_Element <
1613 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
1615 def Insert_Element_v4f32_#Index : Insert_Element <
1616 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
1620 foreach Index = 0-7 in {
1621 def Extract_Element_v8i32_#Index : Extract_Element <
1622 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
1624 def Insert_Element_v8i32_#Index : Insert_Element <
1625 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
1628 def Extract_Element_v8f32_#Index : Extract_Element <
1629 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
1631 def Insert_Element_v8f32_#Index : Insert_Element <
1632 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
1636 foreach Index = 0-15 in {
1637 def Extract_Element_v16i32_#Index : Extract_Element <
1638 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
1640 def Insert_Element_v16i32_#Index : Insert_Element <
1641 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
1644 def Extract_Element_v16f32_#Index : Extract_Element <
1645 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
1647 def Insert_Element_v16f32_#Index : Insert_Element <
1648 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
1652 def : BitConvert <i32, f32, SReg_32>;
1653 def : BitConvert <i32, f32, VReg_32>;
1655 def : BitConvert <f32, i32, SReg_32>;
1656 def : BitConvert <f32, i32, VReg_32>;
1658 def : BitConvert <i64, f64, VReg_64>;
1660 def : BitConvert <f64, i64, VReg_64>;
1662 def : BitConvert <v2f32, v2i32, VReg_64>;
1663 def : BitConvert <v2i32, v2f32, VReg_64>;
1664 def : BitConvert <v2i32, i64, VReg_64>;
1666 def : BitConvert <v4f32, v4i32, VReg_128>;
1667 def : BitConvert <v4i32, v4f32, VReg_128>;
1668 def : BitConvert <v4i32, i128, VReg_128>;
1669 def : BitConvert <i128, v4i32, VReg_128>;
1671 def : BitConvert <v8i32, v32i8, SReg_256>;
1672 def : BitConvert <v32i8, v8i32, SReg_256>;
1673 def : BitConvert <v8i32, v32i8, VReg_256>;
1674 def : BitConvert <v8i32, v8f32, VReg_256>;
1675 def : BitConvert <v8f32, v8i32, VReg_256>;
1676 def : BitConvert <v32i8, v8i32, VReg_256>;
1678 def : BitConvert <v16i32, v16f32, VReg_512>;
1679 def : BitConvert <v16f32, v16i32, VReg_512>;
1681 /********** =================== **********/
1682 /********** Src & Dst modifiers **********/
1683 /********** =================== **********/
1686 (int_AMDIL_clamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)),
1687 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
1688 0 /* ABS */, 1 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */)
1691 /********** ================================ **********/
1692 /********** Floating point absolute/negative **********/
1693 /********** ================================ **********/
1695 // Manipulate the sign bit directly, as e.g. using the source negation modifier
1696 // in V_ADD_F32_e64 $src, 0, [...] does not result in -0.0 for $src == +0.0,
1697 // breaking the piglit *s-floatBitsToInt-neg* tests
1699 // TODO: Look into not implementing isFNegFree/isFAbsFree for SI, and possibly
1700 // removing these patterns
1703 (fneg (fabs f32:$src)),
1704 (V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
1709 (V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff)) /* Clear sign bit */
1714 (V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Toggle sign bit */
1717 /********** ================== **********/
1718 /********** Immediate Patterns **********/
1719 /********** ================== **********/
1722 (SGPRImm<(i32 imm)>:$imm),
1723 (S_MOV_B32 imm:$imm)
1727 (SGPRImm<(f32 fpimm)>:$imm),
1728 (S_MOV_B32 fpimm:$imm)
1733 (V_MOV_B32_e32 imm:$imm)
1738 (V_MOV_B32_e32 fpimm:$imm)
1743 (S_MOV_B64 imm:$imm)
1747 (i64 InlineImm<i64>:$imm),
1748 (S_MOV_B64 InlineImm<i64>:$imm)
1751 // i64 immediates aren't supported in hardware, split it into two 32bit values
1754 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1755 (S_MOV_B32 (i32 (LO32 imm:$imm))), sub0),
1756 (S_MOV_B32 (i32 (HI32 imm:$imm))), sub1)
1761 (INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
1762 (V_MOV_B32_e32 (f32 (LO32f fpimm:$imm))), sub0),
1763 (V_MOV_B32_e32 (f32 (HI32f fpimm:$imm))), sub1)
1766 /********** ===================== **********/
1767 /********** Interpolation Paterns **********/
1768 /********** ===================== **********/
1771 (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params),
1772 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, $params)
1776 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, v2i32:$ij),
1777 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0),
1778 imm:$attr_chan, imm:$attr, i32:$params),
1779 (EXTRACT_SUBREG $ij, sub1),
1780 imm:$attr_chan, imm:$attr, $params)
1783 /********** ================== **********/
1784 /********** Intrinsic Patterns **********/
1785 /********** ================== **********/
1787 /* llvm.AMDGPU.pow */
1788 def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>;
1791 (int_AMDGPU_div f32:$src0, f32:$src1),
1792 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1))
1796 (fdiv f32:$src0, f32:$src1),
1797 (V_MUL_F32_e32 $src0, (V_RCP_F32_e32 $src1))
1801 (fdiv f64:$src0, f64:$src1),
1802 (V_MUL_F64 $src0, (V_RCP_F64_e32 $src1), (i64 0))
1807 (V_COS_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
1812 (V_SIN_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
1816 (int_AMDGPU_cube v4f32:$src),
1817 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
1818 (V_CUBETC_F32 (EXTRACT_SUBREG $src, sub0),
1819 (EXTRACT_SUBREG $src, sub1),
1820 (EXTRACT_SUBREG $src, sub2)),
1822 (V_CUBESC_F32 (EXTRACT_SUBREG $src, sub0),
1823 (EXTRACT_SUBREG $src, sub1),
1824 (EXTRACT_SUBREG $src, sub2)),
1826 (V_CUBEMA_F32 (EXTRACT_SUBREG $src, sub0),
1827 (EXTRACT_SUBREG $src, sub1),
1828 (EXTRACT_SUBREG $src, sub2)),
1830 (V_CUBEID_F32 (EXTRACT_SUBREG $src, sub0),
1831 (EXTRACT_SUBREG $src, sub1),
1832 (EXTRACT_SUBREG $src, sub2)),
1837 (i32 (sext i1:$src0)),
1838 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
1842 (i32 (zext i1:$src0)),
1843 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0)
1846 // 1. Offset as 8bit DWORD immediate
1848 (SIload_constant i128:$sbase, IMM8bitDWORD:$offset),
1849 (S_BUFFER_LOAD_DWORD_IMM $sbase, (as_dword_i32imm $offset))
1852 // 2. Offset loaded in an 32bit SGPR
1854 (SIload_constant i128:$sbase, imm:$offset),
1855 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset))
1858 // 3. Offset in an 32Bit VGPR
1860 (SIload_constant i128:$sbase, i32:$voff),
1861 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0)
1864 // The multiplication scales from [0,1] to the unsigned integer range
1866 (AMDGPUurecip i32:$src0),
1868 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1,
1869 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
1874 (V_MBCNT_HI_U32_B32_e32 0xffffffff,
1875 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0, 0, 0, 0, 0))
1878 /********** ================== **********/
1879 /********** VOP3 Patterns **********/
1880 /********** ================== **********/
1883 (f32 (fadd (fmul f32:$src0, f32:$src1), f32:$src2)),
1884 (V_MAD_F32 $src0, $src1, $src2)
1887 /********** ======================= **********/
1888 /********** Load/Store Patterns **********/
1889 /********** ======================= **********/
1891 class DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat <
1893 (vt (inst 0, $src0, $src0, $src0, 0, 0))
1896 def : DSReadPat <DS_READ_I8, i32, sextloadi8_local>;
1897 def : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>;
1898 def : DSReadPat <DS_READ_I16, i32, sextloadi16_local>;
1899 def : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>;
1900 def : DSReadPat <DS_READ_B32, i32, local_load>;
1902 (local_load i32:$src0),
1903 (i32 (DS_READ_B32 0, $src0, $src0, $src0, 0, 0))
1906 class DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat <
1907 (frag i32:$src1, i32:$src0),
1908 (inst 0, $src0, $src1, $src1, 0, 0)
1911 def : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>;
1912 def : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>;
1913 def : DSWritePat <DS_WRITE_B32, i32, local_store>;
1915 def : Pat <(atomic_load_add_local i32:$ptr, i32:$val),
1916 (DS_ADD_U32_RTN 0, $ptr, $val, 0, 0)>;
1918 def : Pat <(atomic_load_sub_local i32:$ptr, i32:$val),
1919 (DS_SUB_U32_RTN 0, $ptr, $val, 0, 0)>;
1921 /********** ================== **********/
1922 /********** SMRD Patterns **********/
1923 /********** ================== **********/
1925 multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
1927 // 1. Offset as 8bit DWORD immediate
1929 (constant_load (add i64:$sbase, (i64 IMM8bitDWORD:$offset))),
1930 (vt (Instr_IMM $sbase, (as_dword_i32imm $offset)))
1933 // 2. Offset loaded in an 32bit SGPR
1935 (constant_load (SIadd64bit32bit i64:$sbase, imm:$offset)),
1936 (vt (Instr_SGPR $sbase, (S_MOV_B32 imm:$offset)))
1939 // 3. No offset at all
1941 (constant_load i64:$sbase),
1942 (vt (Instr_IMM $sbase, 0))
1946 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>;
1947 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
1948 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, i64>;
1949 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>;
1950 defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, i128>;
1951 defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>;
1952 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
1953 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>;
1954 defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
1956 //===----------------------------------------------------------------------===//
1958 //===----------------------------------------------------------------------===//
1960 multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
1961 PatFrag global_ld, PatFrag constant_ld> {
1963 (vt (global_ld (mubuf_vaddr_offset i64:$ptr, i64:$offset, IMM12bit:$imm_offset))),
1964 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, (as_i16imm $imm_offset))
1968 (vt (global_ld (add i64:$ptr, (i64 IMM12bit:$offset)))),
1969 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset))
1973 (vt (global_ld i64:$ptr)),
1974 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, 0)
1978 (vt (global_ld (add i64:$ptr, i64:$offset))),
1979 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0)
1983 (vt (constant_ld (add i64:$ptr, i64:$offset))),
1984 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0)
1988 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32,
1989 sextloadi8_global, sextloadi8_constant>;
1990 defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32,
1991 az_extloadi8_global, az_extloadi8_constant>;
1992 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32,
1993 sextloadi16_global, sextloadi16_constant>;
1994 defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32,
1995 az_extloadi16_global, az_extloadi16_constant>;
1996 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32,
1997 global_load, constant_load>;
1998 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64,
1999 global_load, constant_load>;
2000 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64,
2001 az_extloadi32_global, az_extloadi32_constant>;
2002 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32,
2003 global_load, constant_load>;
2004 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32,
2005 global_load, constant_load>;
2007 multiclass MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> {
2010 (st vt:$value, (mubuf_vaddr_offset i64:$ptr, i64:$offset, IMM12bit:$imm_offset)),
2011 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, (as_i16imm $imm_offset))
2015 (st vt:$value, (add i64:$ptr, IMM12bit:$offset)),
2016 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset))
2020 (st vt:$value, i64:$ptr),
2021 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, 0)
2025 (st vt:$value, (add i64:$ptr, i64:$offset)),
2026 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, 0)
2030 defm : MUBUFStore_Pattern <BUFFER_STORE_BYTE, i32, truncstorei8_global>;
2031 defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT, i32, truncstorei16_global>;
2032 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORD, i32, global_store>;
2033 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, i64, global_store>;
2034 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, v2i32, global_store>;
2035 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4, v4i32, global_store>;
2037 // BUFFER_LOAD_DWORD*, addr64=0
2038 multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen,
2042 (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset,
2043 imm:$offset, 0, 0, imm:$glc, imm:$slc,
2045 (offset $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2046 (as_i1imm $slc), (as_i1imm $tfe))
2050 (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset,
2051 imm, 1, 0, imm:$glc, imm:$slc,
2053 (offen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
2058 (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset,
2059 imm:$offset, 0, 1, imm:$glc, imm:$slc,
2061 (idxen $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2062 (as_i1imm $slc), (as_i1imm $tfe))
2066 (vt (int_SI_buffer_load_dword i128:$rsrc, v2i32:$vaddr, i32:$soffset,
2067 imm, 1, 1, imm:$glc, imm:$slc,
2069 (bothen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
2074 defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN,
2075 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
2076 defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN,
2077 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>;
2078 defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN,
2079 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
2081 //===----------------------------------------------------------------------===//
2083 //===----------------------------------------------------------------------===//
2085 // TBUFFER_STORE_FORMAT_*, addr64=0
2086 class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat<
2087 (SItbuffer_store i128:$rsrc, vt:$vdata, num_channels, i32:$vaddr,
2088 i32:$soffset, imm:$inst_offset, imm:$dfmt,
2089 imm:$nfmt, imm:$offen, imm:$idxen,
2090 imm:$glc, imm:$slc, imm:$tfe),
2092 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen),
2093 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc,
2094 (as_i1imm $slc), (as_i1imm $tfe), $soffset)
2097 def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>;
2098 def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>;
2099 def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>;
2100 def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>;
2102 /********** ====================== **********/
2103 /********** Indirect adressing **********/
2104 /********** ====================== **********/
2106 multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, SI_INDIRECT_DST IndDst> {
2108 // 1. Extract with offset
2110 (vector_extract vt:$vec, (add i32:$idx, imm:$off)),
2111 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off))
2114 // 2. Extract without offset
2116 (vector_extract vt:$vec, i32:$idx),
2117 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0))
2120 // 3. Insert with offset
2122 (vector_insert vt:$vec, eltvt:$val, (add i32:$idx, imm:$off)),
2123 (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val)
2126 // 4. Insert without offset
2128 (vector_insert vt:$vec, eltvt:$val, i32:$idx),
2129 (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val)
2133 defm : SI_INDIRECT_Pattern <v2f32, f32, SI_INDIRECT_DST_V2>;
2134 defm : SI_INDIRECT_Pattern <v4f32, f32, SI_INDIRECT_DST_V4>;
2135 defm : SI_INDIRECT_Pattern <v8f32, f32, SI_INDIRECT_DST_V8>;
2136 defm : SI_INDIRECT_Pattern <v16f32, f32, SI_INDIRECT_DST_V16>;
2138 defm : SI_INDIRECT_Pattern <v2i32, i32, SI_INDIRECT_DST_V2>;
2139 defm : SI_INDIRECT_Pattern <v4i32, i32, SI_INDIRECT_DST_V4>;
2140 defm : SI_INDIRECT_Pattern <v8i32, i32, SI_INDIRECT_DST_V8>;
2141 defm : SI_INDIRECT_Pattern <v16i32, i32, SI_INDIRECT_DST_V16>;
2143 /********** =============== **********/
2144 /********** Conditions **********/
2145 /********** =============== **********/
2148 (i1 (setcc f32:$src0, f32:$src1, SETO)),
2149 (V_CMP_O_F32_e64 $src0, $src1)
2153 (i1 (setcc f32:$src0, f32:$src1, SETUO)),
2154 (V_CMP_U_F32_e64 $src0, $src1)
2157 //===----------------------------------------------------------------------===//
2158 // Miscellaneous Patterns
2159 //===----------------------------------------------------------------------===//
2162 (i64 (trunc i128:$x)),
2163 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2164 (i32 (EXTRACT_SUBREG $x, sub0)), sub0),
2165 (i32 (EXTRACT_SUBREG $x, sub1)), sub1)
2169 (i32 (trunc i64:$a)),
2170 (EXTRACT_SUBREG $a, sub0)
2174 (i1 (trunc i32:$a)),
2175 (V_CMP_EQ_I32_e64 (V_AND_B32_e32 (i32 1), $a), 1)
2178 // V_ADD_I32_e32/S_ADD_I32 produces carry in VCC/SCC. For the vector
2179 // case, the sgpr-copies pass will fix this to use the vector version.
2181 (i32 (addc i32:$src0, i32:$src1)),
2182 (S_ADD_I32 $src0, $src1)
2186 (or i64:$a, i64:$b),
2188 (INSERT_SUBREG (IMPLICIT_DEF),
2189 (V_OR_B32_e32 (EXTRACT_SUBREG $a, sub0), (EXTRACT_SUBREG $b, sub0)), sub0),
2190 (V_OR_B32_e32 (EXTRACT_SUBREG $a, sub1), (EXTRACT_SUBREG $b, sub1)), sub1)
2193 //============================================================================//
2194 // Miscellaneous Optimization Patterns
2195 //============================================================================//
2197 def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e32>;
2199 } // End isSI predicate