1 //===-- SIInstructions.td - SI Instruction Defintions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This file was originally auto-generated from a GPU register header file and
10 // all the instruction definitions were originally commented out. Instructions
11 // that are not yet supported remain commented out.
12 //===----------------------------------------------------------------------===//
19 def INTERP : InterpSlots;
21 def InterpSlot : Operand<i32> {
22 let PrintMethod = "printInterpSlot";
25 def SendMsgImm : Operand<i32> {
26 let PrintMethod = "printSendMsg";
29 def isSI : Predicate<"Subtarget.getGeneration() "
30 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">;
32 def isCI : Predicate<"Subtarget.getGeneration() "
33 ">= AMDGPUSubtarget::SEA_ISLANDS">;
34 def HasFlatAddressSpace : Predicate<"Subtarget.hasFlatAddressSpace()">;
36 def WAIT_FLAG : InstFlag<"printWaitFlag">;
38 let SubtargetPredicate = isSI in {
40 //===----------------------------------------------------------------------===//
42 //===----------------------------------------------------------------------===//
46 //===----------------------------------------------------------------------===//
48 //===----------------------------------------------------------------------===//
52 // We are using the SGPR_32 and not the SReg_32 register class for 32-bit
53 // SMRD instructions, because the SGPR_32 register class does not include M0
54 // and writing to M0 from an SMRD instruction will hang the GPU.
55 defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SGPR_32>;
56 defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>;
57 defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>;
58 defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>;
59 defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>;
61 defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
62 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SGPR_32
65 defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
66 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64
69 defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper <
70 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128
73 defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <
74 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256
77 defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
78 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512
83 //def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>;
84 //def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>;
86 //===----------------------------------------------------------------------===//
88 //===----------------------------------------------------------------------===//
90 let isMoveImm = 1 in {
91 def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>;
92 def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>;
93 def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>;
94 def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>;
95 } // End isMoveImm = 1
97 def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32",
98 [(set i32:$dst, (not i32:$src0))]
101 def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64",
102 [(set i64:$dst, (not i64:$src0))]
104 def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>;
105 def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>;
106 def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32",
107 [(set i32:$dst, (AMDGPUbrev i32:$src0))]
109 def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>;
111 ////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>;
112 ////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>;
113 def S_BCNT1_I32_B32 : SOP1_32 <0x0000000f, "S_BCNT1_I32_B32",
114 [(set i32:$dst, (ctpop i32:$src0))]
116 def S_BCNT1_I32_B64 : SOP1_32_64 <0x00000010, "S_BCNT1_I32_B64", []>;
118 ////def S_FF0_I32_B32 : SOP1_32 <0x00000011, "S_FF0_I32_B32", []>;
119 ////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>;
120 def S_FF1_I32_B32 : SOP1_32 <0x00000013, "S_FF1_I32_B32",
121 [(set i32:$dst, (cttz_zero_undef i32:$src0))]
123 ////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>;
125 def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32",
126 [(set i32:$dst, (ctlz_zero_undef i32:$src0))]
129 //def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>;
130 def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>;
131 //def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>;
132 def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8",
133 [(set i32:$dst, (sext_inreg i32:$src0, i8))]
135 def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16",
136 [(set i32:$dst, (sext_inreg i32:$src0, i16))]
139 ////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>;
140 ////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>;
141 ////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>;
142 ////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>;
143 def S_GETPC_B64 : SOP1 <
144 0x0000001f, (outs SReg_64:$dst), (ins), "S_GETPC_B64 $dst", []
148 def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>;
149 def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>;
150 def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>;
152 let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in {
154 def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>;
155 def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>;
156 def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>;
157 def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>;
158 def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>;
159 def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>;
160 def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>;
161 def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>;
163 } // End hasSideEffects = 1
165 def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>;
166 def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>;
167 def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>;
168 def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>;
169 def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>;
170 def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>;
171 //def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>;
172 def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>;
173 def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>;
174 def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>;
176 //===----------------------------------------------------------------------===//
178 //===----------------------------------------------------------------------===//
180 let Defs = [SCC] in { // Carry out goes to SCC
181 let isCommutable = 1 in {
182 def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>;
183 def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32",
184 [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))]
186 } // End isCommutable = 1
188 def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>;
189 def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32",
190 [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))]
193 let Uses = [SCC] in { // Carry in comes from SCC
194 let isCommutable = 1 in {
195 def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32",
196 [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
197 } // End isCommutable = 1
199 def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32",
200 [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
201 } // End Uses = [SCC]
202 } // End Defs = [SCC]
204 def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32",
205 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]
207 def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32",
208 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]
210 def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32",
211 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]
213 def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32",
214 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]
217 def S_CSELECT_B32 : SOP2 <
218 0x0000000a, (outs SReg_32:$dst),
219 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32",
223 def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>;
225 def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32",
226 [(set i32:$dst, (and i32:$src0, i32:$src1))]
229 def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64",
230 [(set i64:$dst, (and i64:$src0, i64:$src1))]
233 def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32",
234 [(set i32:$dst, (or i32:$src0, i32:$src1))]
237 def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64",
238 [(set i64:$dst, (or i64:$src0, i64:$src1))]
241 def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32",
242 [(set i32:$dst, (xor i32:$src0, i32:$src1))]
245 def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64",
246 [(set i64:$dst, (xor i64:$src0, i64:$src1))]
248 def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>;
249 def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>;
250 def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>;
251 def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>;
252 def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>;
253 def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>;
254 def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>;
255 def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>;
256 def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>;
257 def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>;
259 // Use added complexity so these patterns are preferred to the VALU patterns.
260 let AddedComplexity = 1 in {
262 def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32",
263 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
265 def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "S_LSHL_B64",
266 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
268 def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32",
269 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
271 def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "S_LSHR_B64",
272 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
274 def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32",
275 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
277 def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64",
278 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
282 def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>;
283 def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>;
284 def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32",
285 [(set i32:$dst, (mul i32:$src0, i32:$src1))]
288 } // End AddedComplexity = 1
290 def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>;
291 def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>;
292 def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>;
293 def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>;
294 //def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>;
295 def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>;
297 //===----------------------------------------------------------------------===//
299 //===----------------------------------------------------------------------===//
301 def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32">;
302 def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32">;
303 def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32">;
304 def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32">;
305 def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32">;
306 def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32">;
307 def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32">;
308 def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32">;
309 def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32">;
310 def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32">;
311 def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32">;
312 def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32">;
313 ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>;
314 ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>;
315 ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>;
316 ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>;
317 //def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>;
319 //===----------------------------------------------------------------------===//
321 //===----------------------------------------------------------------------===//
323 def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>;
324 def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>;
327 This instruction is disabled for now until we can figure out how to teach
328 the instruction selector to correctly use the S_CMP* vs V_CMP*
331 When this instruction is enabled the code generator sometimes produces this
334 SCC = S_CMPK_EQ_I32 SGPR0, imm
336 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
338 def S_CMPK_EQ_I32 : SOPK <
339 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1),
341 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))]
345 let isCompare = 1, Defs = [SCC] in {
346 def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>;
347 def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>;
348 def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>;
349 def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>;
350 def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>;
351 def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>;
352 def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>;
353 def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>;
354 def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>;
355 def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>;
356 def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>;
357 } // End isCompare = 1, Defs = [SCC]
359 let Defs = [SCC], isCommutable = 1 in {
360 def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>;
361 def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>;
364 //def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>;
365 def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>;
366 def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>;
367 def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>;
368 //def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>;
369 //def EXP : EXP_ <0x00000000, "EXP", []>;
371 //===----------------------------------------------------------------------===//
373 //===----------------------------------------------------------------------===//
375 def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "S_NOP $simm16", []>;
377 let isTerminator = 1 in {
379 def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM",
386 let isBranch = 1 in {
387 def S_BRANCH : SOPP <
388 0x00000002, (ins sopp_brtarget:$simm16), "S_BRANCH $simm16",
393 let DisableEncoding = "$scc" in {
394 def S_CBRANCH_SCC0 : SOPP <
395 0x00000004, (ins sopp_brtarget:$simm16, SCCReg:$scc),
396 "S_CBRANCH_SCC0 $simm16", []
398 def S_CBRANCH_SCC1 : SOPP <
399 0x00000005, (ins sopp_brtarget:$simm16, SCCReg:$scc),
400 "S_CBRANCH_SCC1 $simm16",
403 } // End DisableEncoding = "$scc"
405 def S_CBRANCH_VCCZ : SOPP <
406 0x00000006, (ins sopp_brtarget:$simm16, VCCReg:$vcc),
407 "S_CBRANCH_VCCZ $simm16",
410 def S_CBRANCH_VCCNZ : SOPP <
411 0x00000007, (ins sopp_brtarget:$simm16, VCCReg:$vcc),
412 "S_CBRANCH_VCCNZ $simm16",
416 let DisableEncoding = "$exec" in {
417 def S_CBRANCH_EXECZ : SOPP <
418 0x00000008, (ins sopp_brtarget:$simm16, EXECReg:$exec),
419 "S_CBRANCH_EXECZ $simm16",
422 def S_CBRANCH_EXECNZ : SOPP <
423 0x00000009, (ins sopp_brtarget:$simm16, EXECReg:$exec),
424 "S_CBRANCH_EXECNZ $simm16",
427 } // End DisableEncoding = "$exec"
430 } // End isBranch = 1
431 } // End isTerminator = 1
433 let hasSideEffects = 1 in {
434 def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER",
435 [(int_AMDGPU_barrier_local)]
444 def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16",
447 //def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>;
448 //def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>;
449 //def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>;
451 let Uses = [EXEC] in {
452 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "S_SENDMSG $simm16",
453 [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)]
455 let DisableEncoding = "$m0";
457 } // End Uses = [EXEC]
459 //def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>;
460 //def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>;
461 //def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>;
462 //def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>;
463 //def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>;
464 //def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
465 } // End hasSideEffects
467 //===----------------------------------------------------------------------===//
469 //===----------------------------------------------------------------------===//
471 let isCompare = 1 in {
473 defm V_CMP_F_F32 : VOPC_F32 <vopc<0x0>, "V_CMP_F_F32">;
474 defm V_CMP_LT_F32 : VOPC_F32 <vopc<0x1>, "V_CMP_LT_F32", COND_OLT>;
475 defm V_CMP_EQ_F32 : VOPC_F32 <vopc<0x2>, "V_CMP_EQ_F32", COND_OEQ>;
476 defm V_CMP_LE_F32 : VOPC_F32 <vopc<0x3>, "V_CMP_LE_F32", COND_OLE>;
477 defm V_CMP_GT_F32 : VOPC_F32 <vopc<0x4>, "V_CMP_GT_F32", COND_OGT>;
478 defm V_CMP_LG_F32 : VOPC_F32 <vopc<0x5>, "V_CMP_LG_F32">;
479 defm V_CMP_GE_F32 : VOPC_F32 <vopc<0x6>, "V_CMP_GE_F32", COND_OGE>;
480 defm V_CMP_O_F32 : VOPC_F32 <vopc<0x7>, "V_CMP_O_F32", COND_O>;
481 defm V_CMP_U_F32 : VOPC_F32 <vopc<0x8>, "V_CMP_U_F32", COND_UO>;
482 defm V_CMP_NGE_F32 : VOPC_F32 <vopc<0x9>, "V_CMP_NGE_F32">;
483 defm V_CMP_NLG_F32 : VOPC_F32 <vopc<0xa>, "V_CMP_NLG_F32">;
484 defm V_CMP_NGT_F32 : VOPC_F32 <vopc<0xb>, "V_CMP_NGT_F32">;
485 defm V_CMP_NLE_F32 : VOPC_F32 <vopc<0xc>, "V_CMP_NLE_F32">;
486 defm V_CMP_NEQ_F32 : VOPC_F32 <vopc<0xd>, "V_CMP_NEQ_F32", COND_UNE>;
487 defm V_CMP_NLT_F32 : VOPC_F32 <vopc<0xe>, "V_CMP_NLT_F32">;
488 defm V_CMP_TRU_F32 : VOPC_F32 <vopc<0xf>, "V_CMP_TRU_F32">;
490 let hasSideEffects = 1 in {
492 defm V_CMPX_F_F32 : VOPCX_F32 <vopc<0x10>, "V_CMPX_F_F32">;
493 defm V_CMPX_LT_F32 : VOPCX_F32 <vopc<0x11>, "V_CMPX_LT_F32">;
494 defm V_CMPX_EQ_F32 : VOPCX_F32 <vopc<0x12>, "V_CMPX_EQ_F32">;
495 defm V_CMPX_LE_F32 : VOPCX_F32 <vopc<0x13>, "V_CMPX_LE_F32">;
496 defm V_CMPX_GT_F32 : VOPCX_F32 <vopc<0x14>, "V_CMPX_GT_F32">;
497 defm V_CMPX_LG_F32 : VOPCX_F32 <vopc<0x15>, "V_CMPX_LG_F32">;
498 defm V_CMPX_GE_F32 : VOPCX_F32 <vopc<0x16>, "V_CMPX_GE_F32">;
499 defm V_CMPX_O_F32 : VOPCX_F32 <vopc<0x17>, "V_CMPX_O_F32">;
500 defm V_CMPX_U_F32 : VOPCX_F32 <vopc<0x18>, "V_CMPX_U_F32">;
501 defm V_CMPX_NGE_F32 : VOPCX_F32 <vopc<0x19>, "V_CMPX_NGE_F32">;
502 defm V_CMPX_NLG_F32 : VOPCX_F32 <vopc<0x1a>, "V_CMPX_NLG_F32">;
503 defm V_CMPX_NGT_F32 : VOPCX_F32 <vopc<0x1b>, "V_CMPX_NGT_F32">;
504 defm V_CMPX_NLE_F32 : VOPCX_F32 <vopc<0x1c>, "V_CMPX_NLE_F32">;
505 defm V_CMPX_NEQ_F32 : VOPCX_F32 <vopc<0x1d>, "V_CMPX_NEQ_F32">;
506 defm V_CMPX_NLT_F32 : VOPCX_F32 <vopc<0x1e>, "V_CMPX_NLT_F32">;
507 defm V_CMPX_TRU_F32 : VOPCX_F32 <vopc<0x1f>, "V_CMPX_TRU_F32">;
509 } // End hasSideEffects = 1
511 defm V_CMP_F_F64 : VOPC_F64 <vopc<0x20>, "V_CMP_F_F64">;
512 defm V_CMP_LT_F64 : VOPC_F64 <vopc<0x21>, "V_CMP_LT_F64", COND_OLT>;
513 defm V_CMP_EQ_F64 : VOPC_F64 <vopc<0x22>, "V_CMP_EQ_F64", COND_OEQ>;
514 defm V_CMP_LE_F64 : VOPC_F64 <vopc<0x23>, "V_CMP_LE_F64", COND_OLE>;
515 defm V_CMP_GT_F64 : VOPC_F64 <vopc<0x24>, "V_CMP_GT_F64", COND_OGT>;
516 defm V_CMP_LG_F64 : VOPC_F64 <vopc<0x25>, "V_CMP_LG_F64">;
517 defm V_CMP_GE_F64 : VOPC_F64 <vopc<0x26>, "V_CMP_GE_F64", COND_OGE>;
518 defm V_CMP_O_F64 : VOPC_F64 <vopc<0x27>, "V_CMP_O_F64", COND_O>;
519 defm V_CMP_U_F64 : VOPC_F64 <vopc<0x28>, "V_CMP_U_F64", COND_UO>;
520 defm V_CMP_NGE_F64 : VOPC_F64 <vopc<0x29>, "V_CMP_NGE_F64">;
521 defm V_CMP_NLG_F64 : VOPC_F64 <vopc<0x2a>, "V_CMP_NLG_F64">;
522 defm V_CMP_NGT_F64 : VOPC_F64 <vopc<0x2b>, "V_CMP_NGT_F64">;
523 defm V_CMP_NLE_F64 : VOPC_F64 <vopc<0x2c>, "V_CMP_NLE_F64">;
524 defm V_CMP_NEQ_F64 : VOPC_F64 <vopc<0x2d>, "V_CMP_NEQ_F64", COND_UNE>;
525 defm V_CMP_NLT_F64 : VOPC_F64 <vopc<0x2e>, "V_CMP_NLT_F64">;
526 defm V_CMP_TRU_F64 : VOPC_F64 <vopc<0x2f>, "V_CMP_TRU_F64">;
528 let hasSideEffects = 1 in {
530 defm V_CMPX_F_F64 : VOPCX_F64 <vopc<0x30>, "V_CMPX_F_F64">;
531 defm V_CMPX_LT_F64 : VOPCX_F64 <vopc<0x31>, "V_CMPX_LT_F64">;
532 defm V_CMPX_EQ_F64 : VOPCX_F64 <vopc<0x32>, "V_CMPX_EQ_F64">;
533 defm V_CMPX_LE_F64 : VOPCX_F64 <vopc<0x33>, "V_CMPX_LE_F64">;
534 defm V_CMPX_GT_F64 : VOPCX_F64 <vopc<0x34>, "V_CMPX_GT_F64">;
535 defm V_CMPX_LG_F64 : VOPCX_F64 <vopc<0x35>, "V_CMPX_LG_F64">;
536 defm V_CMPX_GE_F64 : VOPCX_F64 <vopc<0x36>, "V_CMPX_GE_F64">;
537 defm V_CMPX_O_F64 : VOPCX_F64 <vopc<0x37>, "V_CMPX_O_F64">;
538 defm V_CMPX_U_F64 : VOPCX_F64 <vopc<0x38>, "V_CMPX_U_F64">;
539 defm V_CMPX_NGE_F64 : VOPCX_F64 <vopc<0x39>, "V_CMPX_NGE_F64">;
540 defm V_CMPX_NLG_F64 : VOPCX_F64 <vopc<0x3a>, "V_CMPX_NLG_F64">;
541 defm V_CMPX_NGT_F64 : VOPCX_F64 <vopc<0x3b>, "V_CMPX_NGT_F64">;
542 defm V_CMPX_NLE_F64 : VOPCX_F64 <vopc<0x3c>, "V_CMPX_NLE_F64">;
543 defm V_CMPX_NEQ_F64 : VOPCX_F64 <vopc<0x3d>, "V_CMPX_NEQ_F64">;
544 defm V_CMPX_NLT_F64 : VOPCX_F64 <vopc<0x3e>, "V_CMPX_NLT_F64">;
545 defm V_CMPX_TRU_F64 : VOPCX_F64 <vopc<0x3f>, "V_CMPX_TRU_F64">;
547 } // End hasSideEffects = 1
549 defm V_CMPS_F_F32 : VOPC_F32 <vopc<0x40>, "V_CMPS_F_F32">;
550 defm V_CMPS_LT_F32 : VOPC_F32 <vopc<0x41>, "V_CMPS_LT_F32">;
551 defm V_CMPS_EQ_F32 : VOPC_F32 <vopc<0x42>, "V_CMPS_EQ_F32">;
552 defm V_CMPS_LE_F32 : VOPC_F32 <vopc<0x43>, "V_CMPS_LE_F32">;
553 defm V_CMPS_GT_F32 : VOPC_F32 <vopc<0x44>, "V_CMPS_GT_F32">;
554 defm V_CMPS_LG_F32 : VOPC_F32 <vopc<0x45>, "V_CMPS_LG_F32">;
555 defm V_CMPS_GE_F32 : VOPC_F32 <vopc<0x46>, "V_CMPS_GE_F32">;
556 defm V_CMPS_O_F32 : VOPC_F32 <vopc<0x47>, "V_CMPS_O_F32">;
557 defm V_CMPS_U_F32 : VOPC_F32 <vopc<0x48>, "V_CMPS_U_F32">;
558 defm V_CMPS_NGE_F32 : VOPC_F32 <vopc<0x49>, "V_CMPS_NGE_F32">;
559 defm V_CMPS_NLG_F32 : VOPC_F32 <vopc<0x4a>, "V_CMPS_NLG_F32">;
560 defm V_CMPS_NGT_F32 : VOPC_F32 <vopc<0x4b>, "V_CMPS_NGT_F32">;
561 defm V_CMPS_NLE_F32 : VOPC_F32 <vopc<0x4c>, "V_CMPS_NLE_F32">;
562 defm V_CMPS_NEQ_F32 : VOPC_F32 <vopc<0x4d>, "V_CMPS_NEQ_F32">;
563 defm V_CMPS_NLT_F32 : VOPC_F32 <vopc<0x4e>, "V_CMPS_NLT_F32">;
564 defm V_CMPS_TRU_F32 : VOPC_F32 <vopc<0x4f>, "V_CMPS_TRU_F32">;
566 let hasSideEffects = 1 in {
568 defm V_CMPSX_F_F32 : VOPCX_F32 <vopc<0x50>, "V_CMPSX_F_F32">;
569 defm V_CMPSX_LT_F32 : VOPCX_F32 <vopc<0x51>, "V_CMPSX_LT_F32">;
570 defm V_CMPSX_EQ_F32 : VOPCX_F32 <vopc<0x52>, "V_CMPSX_EQ_F32">;
571 defm V_CMPSX_LE_F32 : VOPCX_F32 <vopc<0x53>, "V_CMPSX_LE_F32">;
572 defm V_CMPSX_GT_F32 : VOPCX_F32 <vopc<0x54>, "V_CMPSX_GT_F32">;
573 defm V_CMPSX_LG_F32 : VOPCX_F32 <vopc<0x55>, "V_CMPSX_LG_F32">;
574 defm V_CMPSX_GE_F32 : VOPCX_F32 <vopc<0x56>, "V_CMPSX_GE_F32">;
575 defm V_CMPSX_O_F32 : VOPCX_F32 <vopc<0x57>, "V_CMPSX_O_F32">;
576 defm V_CMPSX_U_F32 : VOPCX_F32 <vopc<0x58>, "V_CMPSX_U_F32">;
577 defm V_CMPSX_NGE_F32 : VOPCX_F32 <vopc<0x59>, "V_CMPSX_NGE_F32">;
578 defm V_CMPSX_NLG_F32 : VOPCX_F32 <vopc<0x5a>, "V_CMPSX_NLG_F32">;
579 defm V_CMPSX_NGT_F32 : VOPCX_F32 <vopc<0x5b>, "V_CMPSX_NGT_F32">;
580 defm V_CMPSX_NLE_F32 : VOPCX_F32 <vopc<0x5c>, "V_CMPSX_NLE_F32">;
581 defm V_CMPSX_NEQ_F32 : VOPCX_F32 <vopc<0x5d>, "V_CMPSX_NEQ_F32">;
582 defm V_CMPSX_NLT_F32 : VOPCX_F32 <vopc<0x5e>, "V_CMPSX_NLT_F32">;
583 defm V_CMPSX_TRU_F32 : VOPCX_F32 <vopc<0x5f>, "V_CMPSX_TRU_F32">;
585 } // End hasSideEffects = 1
587 defm V_CMPS_F_F64 : VOPC_F64 <vopc<0x60>, "V_CMPS_F_F64">;
588 defm V_CMPS_LT_F64 : VOPC_F64 <vopc<0x61>, "V_CMPS_LT_F64">;
589 defm V_CMPS_EQ_F64 : VOPC_F64 <vopc<0x62>, "V_CMPS_EQ_F64">;
590 defm V_CMPS_LE_F64 : VOPC_F64 <vopc<0x63>, "V_CMPS_LE_F64">;
591 defm V_CMPS_GT_F64 : VOPC_F64 <vopc<0x64>, "V_CMPS_GT_F64">;
592 defm V_CMPS_LG_F64 : VOPC_F64 <vopc<0x65>, "V_CMPS_LG_F64">;
593 defm V_CMPS_GE_F64 : VOPC_F64 <vopc<0x66>, "V_CMPS_GE_F64">;
594 defm V_CMPS_O_F64 : VOPC_F64 <vopc<0x67>, "V_CMPS_O_F64">;
595 defm V_CMPS_U_F64 : VOPC_F64 <vopc<0x68>, "V_CMPS_U_F64">;
596 defm V_CMPS_NGE_F64 : VOPC_F64 <vopc<0x69>, "V_CMPS_NGE_F64">;
597 defm V_CMPS_NLG_F64 : VOPC_F64 <vopc<0x6a>, "V_CMPS_NLG_F64">;
598 defm V_CMPS_NGT_F64 : VOPC_F64 <vopc<0x6b>, "V_CMPS_NGT_F64">;
599 defm V_CMPS_NLE_F64 : VOPC_F64 <vopc<0x6c>, "V_CMPS_NLE_F64">;
600 defm V_CMPS_NEQ_F64 : VOPC_F64 <vopc<0x6d>, "V_CMPS_NEQ_F64">;
601 defm V_CMPS_NLT_F64 : VOPC_F64 <vopc<0x6e>, "V_CMPS_NLT_F64">;
602 defm V_CMPS_TRU_F64 : VOPC_F64 <vopc<0x6f>, "V_CMPS_TRU_F64">;
604 let hasSideEffects = 1, Defs = [EXEC] in {
606 defm V_CMPSX_F_F64 : VOPC_F64 <vopc<0x70>, "V_CMPSX_F_F64">;
607 defm V_CMPSX_LT_F64 : VOPC_F64 <vopc<0x71>, "V_CMPSX_LT_F64">;
608 defm V_CMPSX_EQ_F64 : VOPC_F64 <vopc<0x72>, "V_CMPSX_EQ_F64">;
609 defm V_CMPSX_LE_F64 : VOPC_F64 <vopc<0x73>, "V_CMPSX_LE_F64">;
610 defm V_CMPSX_GT_F64 : VOPC_F64 <vopc<0x74>, "V_CMPSX_GT_F64">;
611 defm V_CMPSX_LG_F64 : VOPC_F64 <vopc<0x75>, "V_CMPSX_LG_F64">;
612 defm V_CMPSX_GE_F64 : VOPC_F64 <vopc<0x76>, "V_CMPSX_GE_F64">;
613 defm V_CMPSX_O_F64 : VOPC_F64 <vopc<0x77>, "V_CMPSX_O_F64">;
614 defm V_CMPSX_U_F64 : VOPC_F64 <vopc<0x78>, "V_CMPSX_U_F64">;
615 defm V_CMPSX_NGE_F64 : VOPC_F64 <vopc<0x79>, "V_CMPSX_NGE_F64">;
616 defm V_CMPSX_NLG_F64 : VOPC_F64 <vopc<0x7a>, "V_CMPSX_NLG_F64">;
617 defm V_CMPSX_NGT_F64 : VOPC_F64 <vopc<0x7b>, "V_CMPSX_NGT_F64">;
618 defm V_CMPSX_NLE_F64 : VOPC_F64 <vopc<0x7c>, "V_CMPSX_NLE_F64">;
619 defm V_CMPSX_NEQ_F64 : VOPC_F64 <vopc<0x7d>, "V_CMPSX_NEQ_F64">;
620 defm V_CMPSX_NLT_F64 : VOPC_F64 <vopc<0x7e>, "V_CMPSX_NLT_F64">;
621 defm V_CMPSX_TRU_F64 : VOPC_F64 <vopc<0x7f>, "V_CMPSX_TRU_F64">;
623 } // End hasSideEffects = 1, Defs = [EXEC]
625 defm V_CMP_F_I32 : VOPC_I32 <vopc<0x80>, "V_CMP_F_I32">;
626 defm V_CMP_LT_I32 : VOPC_I32 <vopc<0x81>, "V_CMP_LT_I32", COND_SLT>;
627 defm V_CMP_EQ_I32 : VOPC_I32 <vopc<0x82>, "V_CMP_EQ_I32", COND_EQ>;
628 defm V_CMP_LE_I32 : VOPC_I32 <vopc<0x83>, "V_CMP_LE_I32", COND_SLE>;
629 defm V_CMP_GT_I32 : VOPC_I32 <vopc<0x84>, "V_CMP_GT_I32", COND_SGT>;
630 defm V_CMP_NE_I32 : VOPC_I32 <vopc<0x85>, "V_CMP_NE_I32", COND_NE>;
631 defm V_CMP_GE_I32 : VOPC_I32 <vopc<0x86>, "V_CMP_GE_I32", COND_SGE>;
632 defm V_CMP_T_I32 : VOPC_I32 <vopc<0x87>, "V_CMP_T_I32">;
634 let hasSideEffects = 1 in {
636 defm V_CMPX_F_I32 : VOPCX_I32 <vopc<0x90>, "V_CMPX_F_I32">;
637 defm V_CMPX_LT_I32 : VOPCX_I32 <vopc<0x91>, "V_CMPX_LT_I32">;
638 defm V_CMPX_EQ_I32 : VOPCX_I32 <vopc<0x92>, "V_CMPX_EQ_I32">;
639 defm V_CMPX_LE_I32 : VOPCX_I32 <vopc<0x93>, "V_CMPX_LE_I32">;
640 defm V_CMPX_GT_I32 : VOPCX_I32 <vopc<0x94>, "V_CMPX_GT_I32">;
641 defm V_CMPX_NE_I32 : VOPCX_I32 <vopc<0x95>, "V_CMPX_NE_I32">;
642 defm V_CMPX_GE_I32 : VOPCX_I32 <vopc<0x96>, "V_CMPX_GE_I32">;
643 defm V_CMPX_T_I32 : VOPCX_I32 <vopc<0x97>, "V_CMPX_T_I32">;
645 } // End hasSideEffects = 1
647 defm V_CMP_F_I64 : VOPC_I64 <vopc<0xa0>, "V_CMP_F_I64">;
648 defm V_CMP_LT_I64 : VOPC_I64 <vopc<0xa1>, "V_CMP_LT_I64", COND_SLT>;
649 defm V_CMP_EQ_I64 : VOPC_I64 <vopc<0xa2>, "V_CMP_EQ_I64", COND_EQ>;
650 defm V_CMP_LE_I64 : VOPC_I64 <vopc<0xa3>, "V_CMP_LE_I64", COND_SLE>;
651 defm V_CMP_GT_I64 : VOPC_I64 <vopc<0xa4>, "V_CMP_GT_I64", COND_SGT>;
652 defm V_CMP_NE_I64 : VOPC_I64 <vopc<0xa5>, "V_CMP_NE_I64", COND_NE>;
653 defm V_CMP_GE_I64 : VOPC_I64 <vopc<0xa6>, "V_CMP_GE_I64", COND_SGE>;
654 defm V_CMP_T_I64 : VOPC_I64 <vopc<0xa7>, "V_CMP_T_I64">;
656 let hasSideEffects = 1 in {
658 defm V_CMPX_F_I64 : VOPCX_I64 <vopc<0xb0>, "V_CMPX_F_I64">;
659 defm V_CMPX_LT_I64 : VOPCX_I64 <vopc<0xb1>, "V_CMPX_LT_I64">;
660 defm V_CMPX_EQ_I64 : VOPCX_I64 <vopc<0xb2>, "V_CMPX_EQ_I64">;
661 defm V_CMPX_LE_I64 : VOPCX_I64 <vopc<0xb3>, "V_CMPX_LE_I64">;
662 defm V_CMPX_GT_I64 : VOPCX_I64 <vopc<0xb4>, "V_CMPX_GT_I64">;
663 defm V_CMPX_NE_I64 : VOPCX_I64 <vopc<0xb5>, "V_CMPX_NE_I64">;
664 defm V_CMPX_GE_I64 : VOPCX_I64 <vopc<0xb6>, "V_CMPX_GE_I64">;
665 defm V_CMPX_T_I64 : VOPCX_I64 <vopc<0xb7>, "V_CMPX_T_I64">;
667 } // End hasSideEffects = 1
669 defm V_CMP_F_U32 : VOPC_I32 <vopc<0xc0>, "V_CMP_F_U32">;
670 defm V_CMP_LT_U32 : VOPC_I32 <vopc<0xc1>, "V_CMP_LT_U32", COND_ULT>;
671 defm V_CMP_EQ_U32 : VOPC_I32 <vopc<0xc2>, "V_CMP_EQ_U32", COND_EQ>;
672 defm V_CMP_LE_U32 : VOPC_I32 <vopc<0xc3>, "V_CMP_LE_U32", COND_ULE>;
673 defm V_CMP_GT_U32 : VOPC_I32 <vopc<0xc4>, "V_CMP_GT_U32", COND_UGT>;
674 defm V_CMP_NE_U32 : VOPC_I32 <vopc<0xc5>, "V_CMP_NE_U32", COND_NE>;
675 defm V_CMP_GE_U32 : VOPC_I32 <vopc<0xc6>, "V_CMP_GE_U32", COND_UGE>;
676 defm V_CMP_T_U32 : VOPC_I32 <vopc<0xc7>, "V_CMP_T_U32">;
678 let hasSideEffects = 1 in {
680 defm V_CMPX_F_U32 : VOPCX_I32 <vopc<0xd0>, "V_CMPX_F_U32">;
681 defm V_CMPX_LT_U32 : VOPCX_I32 <vopc<0xd1>, "V_CMPX_LT_U32">;
682 defm V_CMPX_EQ_U32 : VOPCX_I32 <vopc<0xd2>, "V_CMPX_EQ_U32">;
683 defm V_CMPX_LE_U32 : VOPCX_I32 <vopc<0xd3>, "V_CMPX_LE_U32">;
684 defm V_CMPX_GT_U32 : VOPCX_I32 <vopc<0xd4>, "V_CMPX_GT_U32">;
685 defm V_CMPX_NE_U32 : VOPCX_I32 <vopc<0xd5>, "V_CMPX_NE_U32">;
686 defm V_CMPX_GE_U32 : VOPCX_I32 <vopc<0xd6>, "V_CMPX_GE_U32">;
687 defm V_CMPX_T_U32 : VOPCX_I32 <vopc<0xd7>, "V_CMPX_T_U32">;
689 } // End hasSideEffects = 1
691 defm V_CMP_F_U64 : VOPC_I64 <vopc<0xe0>, "V_CMP_F_U64">;
692 defm V_CMP_LT_U64 : VOPC_I64 <vopc<0xe1>, "V_CMP_LT_U64", COND_ULT>;
693 defm V_CMP_EQ_U64 : VOPC_I64 <vopc<0xe2>, "V_CMP_EQ_U64", COND_EQ>;
694 defm V_CMP_LE_U64 : VOPC_I64 <vopc<0xe3>, "V_CMP_LE_U64", COND_ULE>;
695 defm V_CMP_GT_U64 : VOPC_I64 <vopc<0xe4>, "V_CMP_GT_U64", COND_UGT>;
696 defm V_CMP_NE_U64 : VOPC_I64 <vopc<0xe5>, "V_CMP_NE_U64", COND_NE>;
697 defm V_CMP_GE_U64 : VOPC_I64 <vopc<0xe6>, "V_CMP_GE_U64", COND_UGE>;
698 defm V_CMP_T_U64 : VOPC_I64 <vopc<0xe7>, "V_CMP_T_U64">;
700 let hasSideEffects = 1 in {
702 defm V_CMPX_F_U64 : VOPCX_I64 <vopc<0xf0>, "V_CMPX_F_U64">;
703 defm V_CMPX_LT_U64 : VOPCX_I64 <vopc<0xf1>, "V_CMPX_LT_U64">;
704 defm V_CMPX_EQ_U64 : VOPCX_I64 <vopc<0xf2>, "V_CMPX_EQ_U64">;
705 defm V_CMPX_LE_U64 : VOPCX_I64 <vopc<0xf3>, "V_CMPX_LE_U64">;
706 defm V_CMPX_GT_U64 : VOPCX_I64 <vopc<0xf4>, "V_CMPX_GT_U64">;
707 defm V_CMPX_NE_U64 : VOPCX_I64 <vopc<0xf5>, "V_CMPX_NE_U64">;
708 defm V_CMPX_GE_U64 : VOPCX_I64 <vopc<0xf6>, "V_CMPX_GE_U64">;
709 defm V_CMPX_T_U64 : VOPCX_I64 <vopc<0xf7>, "V_CMPX_T_U64">;
711 } // End hasSideEffects = 1
713 defm V_CMP_CLASS_F32 : VOPC_F32 <vopc<0x88>, "V_CMP_CLASS_F32">;
715 let hasSideEffects = 1 in {
716 defm V_CMPX_CLASS_F32 : VOPCX_F32 <vopc<0x98>, "V_CMPX_CLASS_F32">;
717 } // End hasSideEffects = 1
719 defm V_CMP_CLASS_F64 : VOPC_F64 <vopc<0xa8>, "V_CMP_CLASS_F64">;
721 let hasSideEffects = 1 in {
722 defm V_CMPX_CLASS_F64 : VOPCX_F64 <vopc<0xb8>, "V_CMPX_CLASS_F64">;
723 } // End hasSideEffects = 1
725 } // End isCompare = 1
727 //===----------------------------------------------------------------------===//
729 //===----------------------------------------------------------------------===//
732 def DS_ADD_U32 : DS_1A1D_NORET <0x0, "DS_ADD_U32", VReg_32>;
733 def DS_SUB_U32 : DS_1A1D_NORET <0x1, "DS_SUB_U32", VReg_32>;
734 def DS_RSUB_U32 : DS_1A1D_NORET <0x2, "DS_RSUB_U32", VReg_32>;
735 def DS_INC_U32 : DS_1A1D_NORET <0x3, "DS_INC_U32", VReg_32>;
736 def DS_DEC_U32 : DS_1A1D_NORET <0x4, "DS_DEC_U32", VReg_32>;
737 def DS_MIN_I32 : DS_1A1D_NORET <0x5, "DS_MIN_I32", VReg_32>;
738 def DS_MAX_I32 : DS_1A1D_NORET <0x6, "DS_MAX_I32", VReg_32>;
739 def DS_MIN_U32 : DS_1A1D_NORET <0x7, "DS_MIN_U32", VReg_32>;
740 def DS_MAX_U32 : DS_1A1D_NORET <0x8, "DS_MAX_U32", VReg_32>;
741 def DS_AND_B32 : DS_1A1D_NORET <0x9, "DS_AND_B32", VReg_32>;
742 def DS_OR_B32 : DS_1A1D_NORET <0xa, "DS_OR_B32", VReg_32>;
743 def DS_XOR_B32 : DS_1A1D_NORET <0xb, "DS_XOR_B32", VReg_32>;
744 def DS_MSKOR_B32 : DS_1A1D_NORET <0xc, "DS_MSKOR_B32", VReg_32>;
745 def DS_CMPST_B32 : DS_1A2D_NORET <0x10, "DS_CMPST_B32", VReg_32>;
746 def DS_CMPST_F32 : DS_1A2D_NORET <0x11, "DS_CMPST_F32", VReg_32>;
747 def DS_MIN_F32 : DS_1A1D_NORET <0x12, "DS_MIN_F32", VReg_32>;
748 def DS_MAX_F32 : DS_1A1D_NORET <0x13, "DS_MAX_F32", VReg_32>;
750 def DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "DS_ADD_RTN_U32", VReg_32, "DS_ADD_U32">;
751 def DS_SUB_RTN_U32 : DS_1A1D_RET <0x21, "DS_SUB_RTN_U32", VReg_32, "DS_SUB_U32">;
752 def DS_RSUB_RTN_U32 : DS_1A1D_RET <0x22, "DS_RSUB_RTN_U32", VReg_32, "DS_RSUB_U32">;
753 def DS_INC_RTN_U32 : DS_1A1D_RET <0x23, "DS_INC_RTN_U32", VReg_32, "DS_INC_U32">;
754 def DS_DEC_RTN_U32 : DS_1A1D_RET <0x24, "DS_DEC_RTN_U32", VReg_32, "DS_DEC_U32">;
755 def DS_MIN_RTN_I32 : DS_1A1D_RET <0x25, "DS_MIN_RTN_I32", VReg_32, "DS_MIN_I32">;
756 def DS_MAX_RTN_I32 : DS_1A1D_RET <0x26, "DS_MAX_RTN_I32", VReg_32, "DS_MAX_I32">;
757 def DS_MIN_RTN_U32 : DS_1A1D_RET <0x27, "DS_MIN_RTN_U32", VReg_32, "DS_MIN_U32">;
758 def DS_MAX_RTN_U32 : DS_1A1D_RET <0x28, "DS_MAX_RTN_U32", VReg_32, "DS_MAX_U32">;
759 def DS_AND_RTN_B32 : DS_1A1D_RET <0x29, "DS_AND_RTN_B32", VReg_32, "DS_AND_B32">;
760 def DS_OR_RTN_B32 : DS_1A1D_RET <0x2a, "DS_OR_RTN_B32", VReg_32, "DS_OR_B32">;
761 def DS_XOR_RTN_B32 : DS_1A1D_RET <0x2b, "DS_XOR_RTN_B32", VReg_32, "DS_XOR_B32">;
762 def DS_MSKOR_RTN_B32 : DS_1A1D_RET <0x2c, "DS_MSKOR_RTN_B32", VReg_32, "DS_MSKOR_B32">;
763 def DS_WRXCHG_RTN_B32 : DS_1A1D_RET <0x2d, "DS_WRXCHG_RTN_B32", VReg_32>;
764 //def DS_WRXCHG2_RTN_B32 : DS_2A0D_RET <0x2e, "DS_WRXCHG2_RTN_B32", VReg_32, "DS_WRXCHG2_B32">;
765 //def DS_WRXCHG2ST64_RTN_B32 : DS_2A0D_RET <0x2f, "DS_WRXCHG2_RTN_B32", VReg_32, "DS_WRXCHG2ST64_B32">;
766 def DS_CMPST_RTN_B32 : DS_1A2D_RET <0x30, "DS_CMPST_RTN_B32", VReg_32, "DS_CMPST_B32">;
767 def DS_CMPST_RTN_F32 : DS_1A2D_RET <0x31, "DS_CMPST_RTN_F32", VReg_32, "DS_CMPST_F32">;
768 def DS_MIN_RTN_F32 : DS_1A1D_RET <0x32, "DS_MIN_RTN_F32", VReg_32, "DS_MIN_F32">;
769 def DS_MAX_RTN_F32 : DS_1A1D_RET <0x33, "DS_MAX_RTN_F32", VReg_32, "DS_MAX_F32">;
771 let SubtargetPredicate = isCI in {
772 def DS_WRAP_RTN_F32 : DS_1A1D_RET <0x34, "DS_WRAP_RTN_F32", VReg_32, "DS_WRAP_F32">;
776 def DS_ADD_U64 : DS_1A1D_NORET <0x40, "DS_ADD_U64", VReg_64>;
777 def DS_SUB_U64 : DS_1A1D_NORET <0x41, "DS_SUB_U64", VReg_64>;
778 def DS_RSUB_U64 : DS_1A1D_NORET <0x42, "DS_RSUB_U64", VReg_64>;
779 def DS_INC_U64 : DS_1A1D_NORET <0x43, "DS_INC_U64", VReg_64>;
780 def DS_DEC_U64 : DS_1A1D_NORET <0x44, "DS_DEC_U64", VReg_64>;
781 def DS_MIN_I64 : DS_1A1D_NORET <0x45, "DS_MIN_I64", VReg_64>;
782 def DS_MAX_I64 : DS_1A1D_NORET <0x46, "DS_MAX_I64", VReg_64>;
783 def DS_MIN_U64 : DS_1A1D_NORET <0x47, "DS_MIN_U64", VReg_64>;
784 def DS_MAX_U64 : DS_1A1D_NORET <0x48, "DS_MAX_U64", VReg_64>;
785 def DS_AND_B64 : DS_1A1D_NORET <0x49, "DS_AND_B64", VReg_64>;
786 def DS_OR_B64 : DS_1A1D_NORET <0x4a, "DS_OR_B64", VReg_64>;
787 def DS_XOR_B64 : DS_1A1D_NORET <0x4b, "DS_XOR_B64", VReg_64>;
788 def DS_MSKOR_B64 : DS_1A1D_NORET <0x4c, "DS_MSKOR_B64", VReg_64>;
789 def DS_CMPST_B64 : DS_1A2D_NORET <0x50, "DS_CMPST_B64", VReg_64>;
790 def DS_CMPST_F64 : DS_1A2D_NORET <0x51, "DS_CMPST_F64", VReg_64>;
791 def DS_MIN_F64 : DS_1A1D_NORET <0x52, "DS_MIN_F64", VReg_64>;
792 def DS_MAX_F64 : DS_1A1D_NORET <0x53, "DS_MAX_F64", VReg_64>;
794 def DS_ADD_RTN_U64 : DS_1A1D_RET <0x60, "DS_ADD_RTN_U64", VReg_64, "DS_ADD_U64">;
795 def DS_SUB_RTN_U64 : DS_1A1D_RET <0x61, "DS_SUB_RTN_U64", VReg_64, "DS_SUB_U64">;
796 def DS_RSUB_RTN_U64 : DS_1A1D_RET <0x62, "DS_RSUB_RTN_U64", VReg_64, "DS_RSUB_U64">;
797 def DS_INC_RTN_U64 : DS_1A1D_RET <0x63, "DS_INC_RTN_U64", VReg_64, "DS_INC_U64">;
798 def DS_DEC_RTN_U64 : DS_1A1D_RET <0x64, "DS_DEC_RTN_U64", VReg_64, "DS_DEC_U64">;
799 def DS_MIN_RTN_I64 : DS_1A1D_RET <0x65, "DS_MIN_RTN_I64", VReg_64, "DS_MIN_I64">;
800 def DS_MAX_RTN_I64 : DS_1A1D_RET <0x66, "DS_MAX_RTN_I64", VReg_64, "DS_MAX_I64">;
801 def DS_MIN_RTN_U64 : DS_1A1D_RET <0x67, "DS_MIN_RTN_U64", VReg_64, "DS_MIN_U64">;
802 def DS_MAX_RTN_U64 : DS_1A1D_RET <0x68, "DS_MAX_RTN_U64", VReg_64, "DS_MAX_U64">;
803 def DS_AND_RTN_B64 : DS_1A1D_RET <0x69, "DS_AND_RTN_B64", VReg_64, "DS_AND_B64">;
804 def DS_OR_RTN_B64 : DS_1A1D_RET <0x6a, "DS_OR_RTN_B64", VReg_64, "DS_OR_B64">;
805 def DS_XOR_RTN_B64 : DS_1A1D_RET <0x6b, "DS_XOR_RTN_B64", VReg_64, "DS_XOR_B64">;
806 def DS_MSKOR_RTN_B64 : DS_1A1D_RET <0x6c, "DS_MSKOR_RTN_B64", VReg_64, "DS_MSKOR_B64">;
807 def DS_WRXCHG_RTN_B64 : DS_1A1D_RET <0x6d, "DS_WRXCHG_RTN_B64", VReg_64, "DS_WRXCHG_B64">;
808 //def DS_WRXCHG2_RTN_B64 : DS_2A0D_RET <0x6e, "DS_WRXCHG2_RTN_B64", VReg_64, "DS_WRXCHG2_B64">;
809 //def DS_WRXCHG2ST64_RTN_B64 : DS_2A0D_RET <0x6f, "DS_WRXCHG2_RTN_B64", VReg_64, "DS_WRXCHG2ST64_B64">;
810 def DS_CMPST_RTN_B64 : DS_1A2D_RET <0x70, "DS_CMPST_RTN_B64", VReg_64, "DS_CMPST_B64">;
811 def DS_CMPST_RTN_F64 : DS_1A2D_RET <0x71, "DS_CMPST_RTN_F64", VReg_64, "DS_CMPST_F64">;
812 def DS_MIN_RTN_F64 : DS_1A1D_RET <0x72, "DS_MIN_F64", VReg_64, "DS_MIN_F64">;
813 def DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "DS_MAX_F64", VReg_64, "DS_MAX_F64">;
815 //let SubtargetPredicate = isCI in {
816 // DS_CONDXCHG32_RTN_B64
817 // DS_CONDXCHG32_RTN_B128
820 // TODO: _SRC2_* forms
822 def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>;
823 def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "DS_WRITE_B8", VReg_32>;
824 def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "DS_WRITE_B16", VReg_32>;
825 def DS_WRITE_B64 : DS_Store_Helper <0x00000004d, "DS_WRITE_B64", VReg_64>;
827 def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>;
828 def DS_READ_I8 : DS_Load_Helper <0x00000039, "DS_READ_I8", VReg_32>;
829 def DS_READ_U8 : DS_Load_Helper <0x0000003a, "DS_READ_U8", VReg_32>;
830 def DS_READ_I16 : DS_Load_Helper <0x0000003b, "DS_READ_I16", VReg_32>;
831 def DS_READ_U16 : DS_Load_Helper <0x0000003c, "DS_READ_U16", VReg_32>;
832 def DS_READ_B64 : DS_Load_Helper <0x00000076, "DS_READ_B64", VReg_64>;
835 def DS_WRITE2_B32 : DS_Store2_Helper <0x0000000E, "DS_WRITE2_B32", VReg_32>;
836 def DS_WRITE2ST64_B32 : DS_Store2_Helper <0x0000000F, "DS_WRITE2ST64_B32", VReg_32>;
837 def DS_WRITE2_B64 : DS_Store2_Helper <0x0000004E, "DS_WRITE2_B64", VReg_64>;
838 def DS_WRITE2ST64_B64 : DS_Store2_Helper <0x0000004F, "DS_WRITE2ST64_B64", VReg_64>;
840 def DS_READ2_B32 : DS_Load2_Helper <0x00000037, "DS_READ2_B32", VReg_64>;
841 def DS_READ2ST64_B32 : DS_Load2_Helper <0x00000038, "DS_READ2ST64_B32", VReg_64>;
842 def DS_READ2_B64 : DS_Load2_Helper <0x00000075, "DS_READ2_B64", VReg_128>;
843 def DS_READ2ST64_B64 : DS_Load2_Helper <0x00000076, "DS_READ2ST64_B64", VReg_128>;
845 //===----------------------------------------------------------------------===//
846 // MUBUF Instructions
847 //===----------------------------------------------------------------------===//
849 //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>;
850 //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>;
851 //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>;
852 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>;
853 //def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>;
854 //def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>;
855 //def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>;
856 //def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>;
857 defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <
858 0x00000008, "BUFFER_LOAD_UBYTE", VReg_32, i32, az_extloadi8_global
860 defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <
861 0x00000009, "BUFFER_LOAD_SBYTE", VReg_32, i32, sextloadi8_global
863 defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <
864 0x0000000a, "BUFFER_LOAD_USHORT", VReg_32, i32, az_extloadi16_global
866 defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <
867 0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32, i32, sextloadi16_global
869 defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <
870 0x0000000c, "BUFFER_LOAD_DWORD", VReg_32, i32, global_load
872 defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <
873 0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64, v2i32, global_load
875 defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <
876 0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128, v4i32, global_load
879 defm BUFFER_STORE_BYTE : MUBUF_Store_Helper <
880 0x00000018, "BUFFER_STORE_BYTE", VReg_32, i32, truncstorei8_global
883 defm BUFFER_STORE_SHORT : MUBUF_Store_Helper <
884 0x0000001a, "BUFFER_STORE_SHORT", VReg_32, i32, truncstorei16_global
887 defm BUFFER_STORE_DWORD : MUBUF_Store_Helper <
888 0x0000001c, "BUFFER_STORE_DWORD", VReg_32, i32, global_store
891 defm BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper <
892 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64, v2i32, global_store
895 defm BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper <
896 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128, v4i32, global_store
898 //def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>;
899 //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>;
900 defm BUFFER_ATOMIC_ADD : MUBUF_Atomic <
901 0x00000032, "BUFFER_ATOMIC_ADD", VReg_32, i32, atomic_add_global
903 defm BUFFER_ATOMIC_SUB : MUBUF_Atomic <
904 0x00000033, "BUFFER_ATOMIC_SUB", VReg_32, i32, atomic_sub_global
906 //def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>;
907 defm BUFFER_ATOMIC_SMIN : MUBUF_Atomic <
908 0x00000035, "BUFFER_ATOMIC_SMIN", VReg_32, i32, atomic_min_global
910 defm BUFFER_ATOMIC_UMIN : MUBUF_Atomic <
911 0x00000036, "BUFFER_ATOMIC_UMIN", VReg_32, i32, atomic_umin_global
913 defm BUFFER_ATOMIC_SMAX : MUBUF_Atomic <
914 0x00000037, "BUFFER_ATOMIC_SMAX", VReg_32, i32, atomic_max_global
916 defm BUFFER_ATOMIC_UMAX : MUBUF_Atomic <
917 0x00000038, "BUFFER_ATOMIC_UMAX", VReg_32, i32, atomic_umax_global
919 defm BUFFER_ATOMIC_AND : MUBUF_Atomic <
920 0x00000039, "BUFFER_ATOMIC_AND", VReg_32, i32, atomic_and_global
922 defm BUFFER_ATOMIC_OR : MUBUF_Atomic <
923 0x0000003a, "BUFFER_ATOMIC_OR", VReg_32, i32, atomic_or_global
925 defm BUFFER_ATOMIC_XOR : MUBUF_Atomic <
926 0x0000003b, "BUFFER_ATOMIC_XOR", VReg_32, i32, atomic_xor_global
928 //def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>;
929 //def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>;
930 //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>;
931 //def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>;
932 //def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>;
933 //def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>;
934 //def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>;
935 //def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>;
936 //def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>;
937 //def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>;
938 //def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>;
939 //def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>;
940 //def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>;
941 //def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>;
942 //def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>;
943 //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>;
944 //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>;
945 //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>;
946 //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>;
947 //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>;
948 //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>;
949 //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>;
950 //def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>;
951 //def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>;
953 //===----------------------------------------------------------------------===//
954 // MTBUF Instructions
955 //===----------------------------------------------------------------------===//
957 //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>;
958 //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>;
959 //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>;
960 defm TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>;
961 defm TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "TBUFFER_STORE_FORMAT_X", VReg_32>;
962 defm TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FORMAT_XY", VReg_64>;
963 defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>;
964 defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>;
966 //===----------------------------------------------------------------------===//
968 //===----------------------------------------------------------------------===//
970 defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "IMAGE_LOAD">;
971 defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "IMAGE_LOAD_MIP">;
972 //def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>;
973 //def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>;
974 //def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>;
975 //def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>;
976 //def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>;
977 //def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>;
978 //def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>;
979 //def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>;
980 defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "IMAGE_GET_RESINFO">;
981 //def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>;
982 //def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>;
983 //def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>;
984 //def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>;
985 //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>;
986 //def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>;
987 //def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>;
988 //def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>;
989 //def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>;
990 //def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>;
991 //def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>;
992 //def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>;
993 //def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>;
994 //def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>;
995 //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>;
996 //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>;
997 //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>;
998 defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">;
999 defm IMAGE_SAMPLE_CL : MIMG_Sampler <0x00000021, "IMAGE_SAMPLE_CL">;
1000 defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">;
1001 defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, "IMAGE_SAMPLE_D_CL">;
1002 defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">;
1003 defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">;
1004 defm IMAGE_SAMPLE_B_CL : MIMG_Sampler <0x00000026, "IMAGE_SAMPLE_B_CL">;
1005 defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, "IMAGE_SAMPLE_LZ">;
1006 defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">;
1007 defm IMAGE_SAMPLE_C_CL : MIMG_Sampler <0x00000029, "IMAGE_SAMPLE_C_CL">;
1008 defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">;
1009 defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, "IMAGE_SAMPLE_C_D_CL">;
1010 defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">;
1011 defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">;
1012 defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler <0x0000002e, "IMAGE_SAMPLE_C_B_CL">;
1013 defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, "IMAGE_SAMPLE_C_LZ">;
1014 defm IMAGE_SAMPLE_O : MIMG_Sampler <0x00000030, "IMAGE_SAMPLE_O">;
1015 defm IMAGE_SAMPLE_CL_O : MIMG_Sampler <0x00000031, "IMAGE_SAMPLE_CL_O">;
1016 defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, "IMAGE_SAMPLE_D_O">;
1017 defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, "IMAGE_SAMPLE_D_CL_O">;
1018 defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, "IMAGE_SAMPLE_L_O">;
1019 defm IMAGE_SAMPLE_B_O : MIMG_Sampler <0x00000035, "IMAGE_SAMPLE_B_O">;
1020 defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler <0x00000036, "IMAGE_SAMPLE_B_CL_O">;
1021 defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, "IMAGE_SAMPLE_LZ_O">;
1022 defm IMAGE_SAMPLE_C_O : MIMG_Sampler <0x00000038, "IMAGE_SAMPLE_C_O">;
1023 defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler <0x00000039, "IMAGE_SAMPLE_C_CL_O">;
1024 defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, "IMAGE_SAMPLE_C_D_O">;
1025 defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, "IMAGE_SAMPLE_C_D_CL_O">;
1026 defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, "IMAGE_SAMPLE_C_L_O">;
1027 defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler <0x0000003d, "IMAGE_SAMPLE_C_B_O">;
1028 defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler <0x0000003e, "IMAGE_SAMPLE_C_B_CL_O">;
1029 defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, "IMAGE_SAMPLE_C_LZ_O">;
1030 defm IMAGE_GATHER4 : MIMG_Gather <0x00000040, "IMAGE_GATHER4">;
1031 defm IMAGE_GATHER4_CL : MIMG_Gather <0x00000041, "IMAGE_GATHER4_CL">;
1032 defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, "IMAGE_GATHER4_L">;
1033 defm IMAGE_GATHER4_B : MIMG_Gather <0x00000045, "IMAGE_GATHER4_B">;
1034 defm IMAGE_GATHER4_B_CL : MIMG_Gather <0x00000046, "IMAGE_GATHER4_B_CL">;
1035 defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, "IMAGE_GATHER4_LZ">;
1036 defm IMAGE_GATHER4_C : MIMG_Gather <0x00000048, "IMAGE_GATHER4_C">;
1037 defm IMAGE_GATHER4_C_CL : MIMG_Gather <0x00000049, "IMAGE_GATHER4_C_CL">;
1038 defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, "IMAGE_GATHER4_C_L">;
1039 defm IMAGE_GATHER4_C_B : MIMG_Gather <0x0000004d, "IMAGE_GATHER4_C_B">;
1040 defm IMAGE_GATHER4_C_B_CL : MIMG_Gather <0x0000004e, "IMAGE_GATHER4_C_B_CL">;
1041 defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, "IMAGE_GATHER4_C_LZ">;
1042 defm IMAGE_GATHER4_O : MIMG_Gather <0x00000050, "IMAGE_GATHER4_O">;
1043 defm IMAGE_GATHER4_CL_O : MIMG_Gather <0x00000051, "IMAGE_GATHER4_CL_O">;
1044 defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, "IMAGE_GATHER4_L_O">;
1045 defm IMAGE_GATHER4_B_O : MIMG_Gather <0x00000055, "IMAGE_GATHER4_B_O">;
1046 defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, "IMAGE_GATHER4_B_CL_O">;
1047 defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, "IMAGE_GATHER4_LZ_O">;
1048 defm IMAGE_GATHER4_C_O : MIMG_Gather <0x00000058, "IMAGE_GATHER4_C_O">;
1049 defm IMAGE_GATHER4_C_CL_O : MIMG_Gather <0x00000059, "IMAGE_GATHER4_C_CL_O">;
1050 defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, "IMAGE_GATHER4_C_L_O">;
1051 defm IMAGE_GATHER4_C_B_O : MIMG_Gather <0x0000005d, "IMAGE_GATHER4_C_B_O">;
1052 defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather <0x0000005e, "IMAGE_GATHER4_C_B_CL_O">;
1053 defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, "IMAGE_GATHER4_C_LZ_O">;
1054 defm IMAGE_GET_LOD : MIMG_Sampler <0x00000060, "IMAGE_GET_LOD">;
1055 defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, "IMAGE_SAMPLE_CD">;
1056 defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, "IMAGE_SAMPLE_CD_CL">;
1057 defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, "IMAGE_SAMPLE_C_CD">;
1058 defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, "IMAGE_SAMPLE_C_CD_CL">;
1059 defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, "IMAGE_SAMPLE_CD_O">;
1060 defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, "IMAGE_SAMPLE_CD_CL_O">;
1061 defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, "IMAGE_SAMPLE_C_CD_O">;
1062 defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, "IMAGE_SAMPLE_C_CD_CL_O">;
1063 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>;
1064 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>;
1066 //===----------------------------------------------------------------------===//
1067 // Flat Instructions
1068 //===----------------------------------------------------------------------===//
1070 let Predicates = [HasFlatAddressSpace] in {
1071 def FLAT_LOAD_UBYTE : FLAT_Load_Helper <0x00000008, "FLAT_LOAD_UBYTE", VReg_32>;
1072 def FLAT_LOAD_SBYTE : FLAT_Load_Helper <0x00000009, "FLAT_LOAD_SBYTE", VReg_32>;
1073 def FLAT_LOAD_USHORT : FLAT_Load_Helper <0x0000000a, "FLAT_LOAD_USHORT", VReg_32>;
1074 def FLAT_LOAD_SSHORT : FLAT_Load_Helper <0x0000000b, "FLAT_LOAD_SSHORT", VReg_32>;
1075 def FLAT_LOAD_DWORD : FLAT_Load_Helper <0x0000000c, "FLAT_LOAD_DWORD", VReg_32>;
1076 def FLAT_LOAD_DWORDX2 : FLAT_Load_Helper <0x0000000d, "FLAT_LOAD_DWORDX2", VReg_64>;
1077 def FLAT_LOAD_DWORDX4 : FLAT_Load_Helper <0x0000000e, "FLAT_LOAD_DWORDX4", VReg_128>;
1078 def FLAT_LOAD_DWORDX3 : FLAT_Load_Helper <0x00000010, "FLAT_LOAD_DWORDX3", VReg_96>;
1080 def FLAT_STORE_BYTE : FLAT_Store_Helper <
1081 0x00000018, "FLAT_STORE_BYTE", VReg_32
1084 def FLAT_STORE_SHORT : FLAT_Store_Helper <
1085 0x0000001a, "FLAT_STORE_SHORT", VReg_32
1088 def FLAT_STORE_DWORD : FLAT_Store_Helper <
1089 0x0000001c, "FLAT_STORE_DWORD", VReg_32
1092 def FLAT_STORE_DWORDX2 : FLAT_Store_Helper <
1093 0x0000001d, "FLAT_STORE_DWORDX2", VReg_64
1096 def FLAT_STORE_DWORDX4 : FLAT_Store_Helper <
1097 0x0000001e, "FLAT_STORE_DWORDX4", VReg_128
1100 def FLAT_STORE_DWORDX3 : FLAT_Store_Helper <
1101 0x0000001e, "FLAT_STORE_DWORDX3", VReg_96
1104 //def FLAT_ATOMIC_SWAP : FLAT_ <0x00000030, "FLAT_ATOMIC_SWAP", []>;
1105 //def FLAT_ATOMIC_CMPSWAP : FLAT_ <0x00000031, "FLAT_ATOMIC_CMPSWAP", []>;
1106 //def FLAT_ATOMIC_ADD : FLAT_ <0x00000032, "FLAT_ATOMIC_ADD", []>;
1107 //def FLAT_ATOMIC_SUB : FLAT_ <0x00000033, "FLAT_ATOMIC_SUB", []>;
1108 //def FLAT_ATOMIC_RSUB : FLAT_ <0x00000034, "FLAT_ATOMIC_RSUB", []>;
1109 //def FLAT_ATOMIC_SMIN : FLAT_ <0x00000035, "FLAT_ATOMIC_SMIN", []>;
1110 //def FLAT_ATOMIC_UMIN : FLAT_ <0x00000036, "FLAT_ATOMIC_UMIN", []>;
1111 //def FLAT_ATOMIC_SMAX : FLAT_ <0x00000037, "FLAT_ATOMIC_SMAX", []>;
1112 //def FLAT_ATOMIC_UMAX : FLAT_ <0x00000038, "FLAT_ATOMIC_UMAX", []>;
1113 //def FLAT_ATOMIC_AND : FLAT_ <0x00000039, "FLAT_ATOMIC_AND", []>;
1114 //def FLAT_ATOMIC_OR : FLAT_ <0x0000003a, "FLAT_ATOMIC_OR", []>;
1115 //def FLAT_ATOMIC_XOR : FLAT_ <0x0000003b, "FLAT_ATOMIC_XOR", []>;
1116 //def FLAT_ATOMIC_INC : FLAT_ <0x0000003c, "FLAT_ATOMIC_INC", []>;
1117 //def FLAT_ATOMIC_DEC : FLAT_ <0x0000003d, "FLAT_ATOMIC_DEC", []>;
1118 //def FLAT_ATOMIC_FCMPSWAP : FLAT_ <0x0000003e, "FLAT_ATOMIC_FCMPSWAP", []>;
1119 //def FLAT_ATOMIC_FMIN : FLAT_ <0x0000003f, "FLAT_ATOMIC_FMIN", []>;
1120 //def FLAT_ATOMIC_FMAX : FLAT_ <0x00000040, "FLAT_ATOMIC_FMAX", []>;
1121 //def FLAT_ATOMIC_SWAP_X2 : FLAT_X2 <0x00000050, "FLAT_ATOMIC_SWAP_X2", []>;
1122 //def FLAT_ATOMIC_CMPSWAP_X2 : FLAT_X2 <0x00000051, "FLAT_ATOMIC_CMPSWAP_X2", []>;
1123 //def FLAT_ATOMIC_ADD_X2 : FLAT_X2 <0x00000052, "FLAT_ATOMIC_ADD_X2", []>;
1124 //def FLAT_ATOMIC_SUB_X2 : FLAT_X2 <0x00000053, "FLAT_ATOMIC_SUB_X2", []>;
1125 //def FLAT_ATOMIC_RSUB_X2 : FLAT_X2 <0x00000054, "FLAT_ATOMIC_RSUB_X2", []>;
1126 //def FLAT_ATOMIC_SMIN_X2 : FLAT_X2 <0x00000055, "FLAT_ATOMIC_SMIN_X2", []>;
1127 //def FLAT_ATOMIC_UMIN_X2 : FLAT_X2 <0x00000056, "FLAT_ATOMIC_UMIN_X2", []>;
1128 //def FLAT_ATOMIC_SMAX_X2 : FLAT_X2 <0x00000057, "FLAT_ATOMIC_SMAX_X2", []>;
1129 //def FLAT_ATOMIC_UMAX_X2 : FLAT_X2 <0x00000058, "FLAT_ATOMIC_UMAX_X2", []>;
1130 //def FLAT_ATOMIC_AND_X2 : FLAT_X2 <0x00000059, "FLAT_ATOMIC_AND_X2", []>;
1131 //def FLAT_ATOMIC_OR_X2 : FLAT_X2 <0x0000005a, "FLAT_ATOMIC_OR_X2", []>;
1132 //def FLAT_ATOMIC_XOR_X2 : FLAT_X2 <0x0000005b, "FLAT_ATOMIC_XOR_X2", []>;
1133 //def FLAT_ATOMIC_INC_X2 : FLAT_X2 <0x0000005c, "FLAT_ATOMIC_INC_X2", []>;
1134 //def FLAT_ATOMIC_DEC_X2 : FLAT_X2 <0x0000005d, "FLAT_ATOMIC_DEC_X2", []>;
1135 //def FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_X2 <0x0000005e, "FLAT_ATOMIC_FCMPSWAP_X2", []>;
1136 //def FLAT_ATOMIC_FMIN_X2 : FLAT_X2 <0x0000005f, "FLAT_ATOMIC_FMIN_X2", []>;
1137 //def FLAT_ATOMIC_FMAX_X2 : FLAT_X2 <0x00000060, "FLAT_ATOMIC_FMAX_X2", []>;
1139 } // End HasFlatAddressSpace predicate
1140 //===----------------------------------------------------------------------===//
1141 // VOP1 Instructions
1142 //===----------------------------------------------------------------------===//
1144 //def V_NOP : VOP1_ <0x00000000, "V_NOP", []>;
1146 let isMoveImm = 1 in {
1147 defm V_MOV_B32 : VOP1Inst <vop1<0x1>, "V_MOV_B32", VOP_I32_I32>;
1148 } // End isMoveImm = 1
1150 let Uses = [EXEC] in {
1152 def V_READFIRSTLANE_B32 : VOP1 <
1154 (outs SReg_32:$vdst),
1155 (ins VReg_32:$src0),
1156 "V_READFIRSTLANE_B32 $vdst, $src0",
1162 defm V_CVT_I32_F64 : VOP1Inst <vop1<0x3>, "V_CVT_I32_F64",
1163 VOP_I32_F64, fp_to_sint
1165 defm V_CVT_F64_I32 : VOP1Inst <vop1<0x4>, "V_CVT_F64_I32",
1166 VOP_F64_I32, sint_to_fp
1168 defm V_CVT_F32_I32 : VOP1Inst <vop1<0x5>, "V_CVT_F32_I32",
1169 VOP_F32_I32, sint_to_fp
1171 defm V_CVT_F32_U32 : VOP1Inst <vop1<0x6>, "V_CVT_F32_U32",
1172 VOP_F32_I32, uint_to_fp
1174 defm V_CVT_U32_F32 : VOP1Inst <vop1<0x7>, "V_CVT_U32_F32",
1175 VOP_I32_F32, fp_to_uint
1177 defm V_CVT_I32_F32 : VOP1Inst <vop1<0x8>, "V_CVT_I32_F32",
1178 VOP_I32_F32, fp_to_sint
1180 defm V_MOV_FED_B32 : VOP1Inst <vop1<0x9>, "V_MOV_FED_B32", VOP_I32_I32>;
1181 defm V_CVT_F16_F32 : VOP1Inst <vop1<0xa>, "V_CVT_F16_F32",
1182 VOP_I32_F32, fp_to_f16
1184 defm V_CVT_F32_F16 : VOP1Inst <vop1<0xb>, "V_CVT_F32_F16",
1185 VOP_F32_I32, f16_to_fp
1187 //defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>;
1188 //defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>;
1189 //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>;
1190 defm V_CVT_F32_F64 : VOP1Inst <vop1<0xf>, "V_CVT_F32_F64",
1193 defm V_CVT_F64_F32 : VOP1Inst <vop1<0x10>, "V_CVT_F64_F32",
1194 VOP_F64_F32, fextend
1196 defm V_CVT_F32_UBYTE0 : VOP1Inst <vop1<0x11>, "V_CVT_F32_UBYTE0",
1197 VOP_F32_I32, AMDGPUcvt_f32_ubyte0
1199 defm V_CVT_F32_UBYTE1 : VOP1Inst <vop1<0x12>, "V_CVT_F32_UBYTE1",
1200 VOP_F32_I32, AMDGPUcvt_f32_ubyte1
1202 defm V_CVT_F32_UBYTE2 : VOP1Inst <vop1<0x13>, "V_CVT_F32_UBYTE2",
1203 VOP_F32_I32, AMDGPUcvt_f32_ubyte2
1205 defm V_CVT_F32_UBYTE3 : VOP1Inst <vop1<0x14>, "V_CVT_F32_UBYTE3",
1206 VOP_F32_I32, AMDGPUcvt_f32_ubyte3
1208 defm V_CVT_U32_F64 : VOP1Inst <vop1<0x15>, "V_CVT_U32_F64",
1209 VOP_I32_F64, fp_to_uint
1211 defm V_CVT_F64_U32 : VOP1Inst <vop1<0x16>, "V_CVT_F64_U32",
1212 VOP_F64_I32, uint_to_fp
1215 defm V_FRACT_F32 : VOP1Inst <vop1<0x20>, "V_FRACT_F32",
1216 VOP_F32_F32, AMDGPUfract
1218 defm V_TRUNC_F32 : VOP1Inst <vop1<0x21>, "V_TRUNC_F32",
1221 defm V_CEIL_F32 : VOP1Inst <vop1<0x22>, "V_CEIL_F32",
1224 defm V_RNDNE_F32 : VOP1Inst <vop1<0x23>, "V_RNDNE_F32",
1227 defm V_FLOOR_F32 : VOP1Inst <vop1<0x24>, "V_FLOOR_F32",
1230 defm V_EXP_F32 : VOP1Inst <vop1<0x25>, "V_EXP_F32",
1233 defm V_LOG_CLAMP_F32 : VOP1Inst <vop1<0x26>, "V_LOG_CLAMP_F32", VOP_F32_F32>;
1234 defm V_LOG_F32 : VOP1Inst <vop1<0x27>, "V_LOG_F32",
1238 defm V_RCP_CLAMP_F32 : VOP1Inst <vop1<0x28>, "V_RCP_CLAMP_F32", VOP_F32_F32>;
1239 defm V_RCP_LEGACY_F32 : VOP1Inst <vop1<0x29>, "V_RCP_LEGACY_F32", VOP_F32_F32>;
1240 defm V_RCP_F32 : VOP1Inst <vop1<0x2a>, "V_RCP_F32",
1241 VOP_F32_F32, AMDGPUrcp
1243 defm V_RCP_IFLAG_F32 : VOP1Inst <vop1<0x2b>, "V_RCP_IFLAG_F32", VOP_F32_F32>;
1244 defm V_RSQ_CLAMP_F32 : VOP1Inst <vop1<0x2c>, "V_RSQ_CLAMP_F32",
1245 VOP_F32_F32, AMDGPUrsq_clamped
1247 defm V_RSQ_LEGACY_F32 : VOP1Inst <vop1<0x2d>, "V_RSQ_LEGACY_F32",
1248 VOP_F32_F32, AMDGPUrsq_legacy
1250 defm V_RSQ_F32 : VOP1Inst <vop1<0x2e>, "V_RSQ_F32",
1251 VOP_F32_F32, AMDGPUrsq
1253 defm V_RCP_F64 : VOP1Inst <vop1<0x2f>, "V_RCP_F64",
1254 VOP_F64_F64, AMDGPUrcp
1256 defm V_RCP_CLAMP_F64 : VOP1Inst <vop1<0x30>, "V_RCP_CLAMP_F64", VOP_F64_F64>;
1257 defm V_RSQ_F64 : VOP1Inst <vop1<0x31>, "V_RSQ_F64",
1258 VOP_F64_F64, AMDGPUrsq
1260 defm V_RSQ_CLAMP_F64 : VOP1Inst <vop1<0x32>, "V_RSQ_CLAMP_F64",
1261 VOP_F64_F64, AMDGPUrsq_clamped
1263 defm V_SQRT_F32 : VOP1Inst <vop1<0x33>, "V_SQRT_F32",
1266 defm V_SQRT_F64 : VOP1Inst <vop1<0x34>, "V_SQRT_F64",
1269 defm V_SIN_F32 : VOP1Inst <vop1<0x35>, "V_SIN_F32",
1270 VOP_F32_F32, AMDGPUsin
1272 defm V_COS_F32 : VOP1Inst <vop1<0x36>, "V_COS_F32",
1273 VOP_F32_F32, AMDGPUcos
1275 defm V_NOT_B32 : VOP1Inst <vop1<0x37>, "V_NOT_B32", VOP_I32_I32>;
1276 defm V_BFREV_B32 : VOP1Inst <vop1<0x38>, "V_BFREV_B32", VOP_I32_I32>;
1277 defm V_FFBH_U32 : VOP1Inst <vop1<0x39>, "V_FFBH_U32", VOP_I32_I32>;
1278 defm V_FFBL_B32 : VOP1Inst <vop1<0x3a>, "V_FFBL_B32", VOP_I32_I32>;
1279 defm V_FFBH_I32 : VOP1Inst <vop1<0x3b>, "V_FFBH_I32", VOP_I32_I32>;
1280 //defm V_FREXP_EXP_I32_F64 : VOPInst <0x0000003c, "V_FREXP_EXP_I32_F64", VOP_I32_F32>;
1281 defm V_FREXP_MANT_F64 : VOP1Inst <vop1<0x3d>, "V_FREXP_MANT_F64", VOP_F64_F64>;
1282 defm V_FRACT_F64 : VOP1Inst <vop1<0x3e>, "V_FRACT_F64", VOP_F64_F64>;
1283 //defm V_FREXP_EXP_I32_F32 : VOPInst <0x0000003f, "V_FREXP_EXP_I32_F32", VOP_I32_F32>;
1284 defm V_FREXP_MANT_F32 : VOP1Inst <vop1<0x40>, "V_FREXP_MANT_F32", VOP_F32_F32>;
1285 //def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>;
1286 defm V_MOVRELD_B32 : VOP1Inst <vop1<0x42>, "V_MOVRELD_B32", VOP_I32_I32>;
1287 defm V_MOVRELS_B32 : VOP1Inst <vop1<0x43>, "V_MOVRELS_B32", VOP_I32_I32>;
1288 defm V_MOVRELSD_B32 : VOP1Inst <vop1<0x44>, "V_MOVRELSD_B32", VOP_I32_I32>;
1291 //===----------------------------------------------------------------------===//
1292 // VINTRP Instructions
1293 //===----------------------------------------------------------------------===//
1295 def V_INTERP_P1_F32 : VINTRP <
1297 (outs VReg_32:$dst),
1298 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1299 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]",
1301 let DisableEncoding = "$m0";
1304 def V_INTERP_P2_F32 : VINTRP <
1306 (outs VReg_32:$dst),
1307 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1308 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]",
1311 let Constraints = "$src0 = $dst";
1312 let DisableEncoding = "$src0,$m0";
1316 def V_INTERP_MOV_F32 : VINTRP <
1318 (outs VReg_32:$dst),
1319 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1320 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]",
1322 let DisableEncoding = "$m0";
1325 //===----------------------------------------------------------------------===//
1326 // VOP2 Instructions
1327 //===----------------------------------------------------------------------===//
1329 def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
1330 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc),
1331 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]",
1334 let DisableEncoding = "$vcc";
1337 def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst),
1338 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2),
1339 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2",
1340 [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))]
1342 let src0_modifiers = 0;
1343 let src1_modifiers = 0;
1344 let src2_modifiers = 0;
1347 def V_READLANE_B32 : VOP2 <
1349 (outs SReg_32:$vdst),
1350 (ins VReg_32:$src0, SSrc_32:$vsrc1),
1351 "V_READLANE_B32 $vdst, $src0, $vsrc1",
1355 def V_WRITELANE_B32 : VOP2 <
1357 (outs VReg_32:$vdst),
1358 (ins SReg_32:$src0, SSrc_32:$vsrc1),
1359 "V_WRITELANE_B32 $vdst, $src0, $vsrc1",
1363 let isCommutable = 1 in {
1364 defm V_ADD_F32 : VOP2Inst <vop2<0x3>, "V_ADD_F32",
1365 VOP_F32_F32_F32, fadd
1368 defm V_SUB_F32 : VOP2Inst <vop2<0x4>, "V_SUB_F32", VOP_F32_F32_F32, fsub>;
1369 defm V_SUBREV_F32 : VOP2Inst <vop2<0x5>, "V_SUBREV_F32",
1370 VOP_F32_F32_F32, null_frag, "V_SUB_F32"
1372 } // End isCommutable = 1
1374 defm V_MAC_LEGACY_F32 : VOP2Inst <vop2<0x6>, "V_MAC_LEGACY_F32",
1378 let isCommutable = 1 in {
1380 defm V_MUL_LEGACY_F32 : VOP2Inst <vop2<0x7>, "V_MUL_LEGACY_F32",
1381 VOP_F32_F32_F32, int_AMDGPU_mul
1384 defm V_MUL_F32 : VOP2Inst <vop2<0x8>, "V_MUL_F32",
1385 VOP_F32_F32_F32, fmul
1389 defm V_MUL_I32_I24 : VOP2Inst <vop2<0x9>, "V_MUL_I32_I24",
1390 VOP_I32_I32_I32, AMDGPUmul_i24
1392 //defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>;
1393 defm V_MUL_U32_U24 : VOP2Inst <vop2<0xb>, "V_MUL_U32_U24",
1394 VOP_I32_I32_I32, AMDGPUmul_u24
1396 //defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>;
1399 defm V_MIN_LEGACY_F32 : VOP2Inst <vop2<0xd>, "V_MIN_LEGACY_F32",
1400 VOP_F32_F32_F32, AMDGPUfmin
1403 defm V_MAX_LEGACY_F32 : VOP2Inst <vop2<0xe>, "V_MAX_LEGACY_F32",
1404 VOP_F32_F32_F32, AMDGPUfmax
1407 defm V_MIN_F32 : VOP2Inst <vop2<0xf>, "V_MIN_F32", VOP_F32_F32_F32>;
1408 defm V_MAX_F32 : VOP2Inst <vop2<0x10>, "V_MAX_F32", VOP_F32_F32_F32>;
1409 defm V_MIN_I32 : VOP2Inst <vop2<0x11>, "V_MIN_I32", VOP_I32_I32_I32, AMDGPUsmin>;
1410 defm V_MAX_I32 : VOP2Inst <vop2<0x12>, "V_MAX_I32", VOP_I32_I32_I32, AMDGPUsmax>;
1411 defm V_MIN_U32 : VOP2Inst <vop2<0x13>, "V_MIN_U32", VOP_I32_I32_I32, AMDGPUumin>;
1412 defm V_MAX_U32 : VOP2Inst <vop2<0x14>, "V_MAX_U32", VOP_I32_I32_I32, AMDGPUumax>;
1414 defm V_LSHR_B32 : VOP2Inst <vop2<0x15>, "V_LSHR_B32", VOP_I32_I32_I32, srl>;
1416 defm V_LSHRREV_B32 : VOP2Inst <
1417 vop2<0x16>, "V_LSHRREV_B32", VOP_I32_I32_I32, null_frag, "V_LSHR_B32"
1420 defm V_ASHR_I32 : VOP2Inst <vop2<0x17>, "V_ASHR_I32",
1421 VOP_I32_I32_I32, sra
1423 defm V_ASHRREV_I32 : VOP2Inst <
1424 vop2<0x18>, "V_ASHRREV_I32", VOP_I32_I32_I32, null_frag, "V_ASHR_I32"
1427 let hasPostISelHook = 1 in {
1429 defm V_LSHL_B32 : VOP2Inst <vop2<0x19>, "V_LSHL_B32", VOP_I32_I32_I32, shl>;
1432 defm V_LSHLREV_B32 : VOP2Inst <
1433 vop2<0x1a>, "V_LSHLREV_B32", VOP_I32_I32_I32, null_frag, "V_LSHL_B32"
1436 defm V_AND_B32 : VOP2Inst <vop2<0x1b>, "V_AND_B32",
1437 VOP_I32_I32_I32, and>;
1438 defm V_OR_B32 : VOP2Inst <vop2<0x1c>, "V_OR_B32",
1441 defm V_XOR_B32 : VOP2Inst <vop2<0x1d>, "V_XOR_B32",
1442 VOP_I32_I32_I32, xor
1445 } // End isCommutable = 1
1447 defm V_BFM_B32 : VOP2Inst <vop2<0x1e>, "V_BFM_B32",
1448 VOP_I32_I32_I32, AMDGPUbfm>;
1449 defm V_MAC_F32 : VOP2Inst <vop2<0x1f>, "V_MAC_F32", VOP_F32_F32_F32>;
1450 defm V_MADMK_F32 : VOP2Inst <vop2<0x20>, "V_MADMK_F32", VOP_F32_F32_F32>;
1451 defm V_MADAK_F32 : VOP2Inst <vop2<0x21>, "V_MADAK_F32", VOP_F32_F32_F32>;
1452 defm V_BCNT_U32_B32 : VOP2Inst <vop2<0x22>, "V_BCNT_U32_B32", VOP_I32_I32_I32>;
1453 defm V_MBCNT_LO_U32_B32 : VOP2Inst <vop2<0x23>, "V_MBCNT_LO_U32_B32",
1456 defm V_MBCNT_HI_U32_B32 : VOP2Inst <vop2<0x24>, "V_MBCNT_HI_U32_B32",
1460 let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC
1461 // No patterns so that the scalar instructions are always selected.
1462 // The scalar versions will be replaced with vector when needed later.
1463 defm V_ADD_I32 : VOP2bInst <vop2<0x25>, "V_ADD_I32",
1464 VOP_I32_I32_I32, add
1466 defm V_SUB_I32 : VOP2bInst <vop2<0x26>, "V_SUB_I32",
1467 VOP_I32_I32_I32, sub
1469 defm V_SUBREV_I32 : VOP2bInst <vop2<0x27>, "V_SUBREV_I32",
1470 VOP_I32_I32_I32, null_frag, "V_SUB_I32"
1473 let Uses = [VCC] in { // Carry-in comes from VCC
1474 defm V_ADDC_U32 : VOP2bInst <vop2<0x28>, "V_ADDC_U32",
1475 VOP_I32_I32_I32_VCC, adde
1477 defm V_SUBB_U32 : VOP2bInst <vop2<0x29>, "V_SUBB_U32",
1478 VOP_I32_I32_I32_VCC, sube
1480 defm V_SUBBREV_U32 : VOP2bInst <vop2<0x2a>, "V_SUBBREV_U32",
1481 VOP_I32_I32_I32_VCC, null_frag, "V_SUBB_U32"
1484 } // End Uses = [VCC]
1485 } // End isCommutable = 1, Defs = [VCC]
1487 defm V_LDEXP_F32 : VOP2Inst <vop2<0x2b>, "V_LDEXP_F32",
1488 VOP_F32_F32_I32, AMDGPUldexp
1490 ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>;
1491 ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>;
1492 ////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>;
1493 defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <vop2<0x2f>, "V_CVT_PKRTZ_F16_F32",
1494 VOP_I32_F32_F32, int_SI_packf16
1496 ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>;
1497 ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>;
1499 //===----------------------------------------------------------------------===//
1500 // VOP3 Instructions
1501 //===----------------------------------------------------------------------===//
1503 defm V_MAD_LEGACY_F32 : VOP3Inst <vop3<0x140>, "V_MAD_LEGACY_F32",
1506 defm V_MAD_F32 : VOP3Inst <vop3<0x141>, "V_MAD_F32",
1507 VOP_F32_F32_F32_F32, fmad
1509 defm V_MAD_I32_I24 : VOP3Inst <vop3<0x142>, "V_MAD_I32_I24",
1510 VOP_I32_I32_I32_I32, AMDGPUmad_i24
1512 defm V_MAD_U32_U24 : VOP3Inst <vop3<0x143>, "V_MAD_U32_U24",
1513 VOP_I32_I32_I32_I32, AMDGPUmad_u24
1516 defm V_CUBEID_F32 : VOP3Inst <vop3<0x144>, "V_CUBEID_F32",
1519 defm V_CUBESC_F32 : VOP3Inst <vop3<0x145>, "V_CUBESC_F32",
1522 defm V_CUBETC_F32 : VOP3Inst <vop3<0x146>, "V_CUBETC_F32",
1525 defm V_CUBEMA_F32 : VOP3Inst <vop3<0x147>, "V_CUBEMA_F32",
1528 defm V_BFE_U32 : VOP3Inst <vop3<0x148>, "V_BFE_U32",
1529 VOP_I32_I32_I32_I32, AMDGPUbfe_u32
1531 defm V_BFE_I32 : VOP3Inst <vop3<0x149>, "V_BFE_I32",
1532 VOP_I32_I32_I32_I32, AMDGPUbfe_i32
1534 defm V_BFI_B32 : VOP3Inst <vop3<0x14a>, "V_BFI_B32",
1535 VOP_I32_I32_I32_I32, AMDGPUbfi
1537 defm V_FMA_F32 : VOP3Inst <vop3<0x14b>, "V_FMA_F32",
1538 VOP_F32_F32_F32_F32, fma
1540 defm V_FMA_F64 : VOP3Inst <vop3<0x14c>, "V_FMA_F64",
1541 VOP_F64_F64_F64_F64, fma
1543 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>;
1544 defm V_ALIGNBIT_B32 : VOP3Inst <vop3<0x14e>, "V_ALIGNBIT_B32",
1547 defm V_ALIGNBYTE_B32 : VOP3Inst <vop3<0x14f>, "V_ALIGNBYTE_B32",
1550 defm V_MULLIT_F32 : VOP3Inst <vop3<0x150>, "V_MULLIT_F32",
1551 VOP_F32_F32_F32_F32>;
1552 ////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>;
1553 ////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>;
1554 ////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>;
1555 ////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>;
1556 ////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>;
1557 ////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>;
1558 ////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>;
1559 ////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>;
1560 ////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>;
1561 //def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>;
1562 //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>;
1563 //def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>;
1564 defm V_SAD_U32 : VOP3Inst <vop3<0x15d>, "V_SAD_U32",
1567 ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>;
1568 defm V_DIV_FIXUP_F32 : VOP3Inst <
1569 vop3<0x15f>, "V_DIV_FIXUP_F32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup
1571 defm V_DIV_FIXUP_F64 : VOP3Inst <
1572 vop3<0x160>, "V_DIV_FIXUP_F64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup
1575 defm V_LSHL_B64 : VOP3Inst <vop3<0x161>, "V_LSHL_B64",
1576 VOP_I64_I64_I32, shl
1578 defm V_LSHR_B64 : VOP3Inst <vop3<0x162>, "V_LSHR_B64",
1579 VOP_I64_I64_I32, srl
1581 defm V_ASHR_I64 : VOP3Inst <vop3<0x163>, "V_ASHR_I64",
1582 VOP_I64_I64_I32, sra
1585 let isCommutable = 1 in {
1587 defm V_ADD_F64 : VOP3Inst <vop3<0x164>, "V_ADD_F64",
1588 VOP_F64_F64_F64, fadd
1590 defm V_MUL_F64 : VOP3Inst <vop3<0x165>, "V_MUL_F64",
1591 VOP_F64_F64_F64, fmul
1593 defm V_MIN_F64 : VOP3Inst <vop3<0x166>, "V_MIN_F64",
1596 defm V_MAX_F64 : VOP3Inst <vop3<0x167>, "V_MAX_F64",
1600 } // isCommutable = 1
1602 defm V_LDEXP_F64 : VOP3Inst <vop3<0x168>, "V_LDEXP_F64",
1603 VOP_F64_F64_I32, AMDGPUldexp
1606 let isCommutable = 1 in {
1608 defm V_MUL_LO_U32 : VOP3Inst <vop3<0x169>, "V_MUL_LO_U32",
1611 defm V_MUL_HI_U32 : VOP3Inst <vop3<0x16a>, "V_MUL_HI_U32",
1614 defm V_MUL_LO_I32 : VOP3Inst <vop3<0x16b>, "V_MUL_LO_I32",
1617 defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c>, "V_MUL_HI_I32",
1621 } // isCommutable = 1
1623 defm V_DIV_SCALE_F32 : VOP3b_32 <vop3<0x16d>, "V_DIV_SCALE_F32", []>;
1625 // Double precision division pre-scale.
1626 defm V_DIV_SCALE_F64 : VOP3b_64 <vop3<0x16e>, "V_DIV_SCALE_F64", []>;
1628 defm V_DIV_FMAS_F32 : VOP3Inst <vop3<0x16f>, "V_DIV_FMAS_F32",
1629 VOP_F32_F32_F32_F32, AMDGPUdiv_fmas
1631 defm V_DIV_FMAS_F64 : VOP3Inst <vop3<0x170>, "V_DIV_FMAS_F64",
1632 VOP_F64_F64_F64_F64, AMDGPUdiv_fmas
1634 //def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>;
1635 //def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>;
1636 //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>;
1637 defm V_TRIG_PREOP_F64 : VOP3Inst <
1638 vop3<0x174>, "V_TRIG_PREOP_F64", VOP_F64_F64_I32, AMDGPUtrig_preop
1641 //===----------------------------------------------------------------------===//
1642 // Pseudo Instructions
1643 //===----------------------------------------------------------------------===//
1645 let isCodeGenOnly = 1, isPseudo = 1 in {
1647 def V_MOV_I1 : InstSI <
1650 "", [(set i1:$dst, (imm:$src))]
1653 def V_AND_I1 : InstSI <
1654 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1655 [(set i1:$dst, (and i1:$src0, i1:$src1))]
1658 def V_OR_I1 : InstSI <
1659 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1660 [(set i1:$dst, (or i1:$src0, i1:$src1))]
1663 def V_XOR_I1 : InstSI <
1664 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1665 [(set i1:$dst, (xor i1:$src0, i1:$src1))]
1668 let hasSideEffects = 1 in {
1669 def SGPR_USE : InstSI <(outs),(ins), "", []>;
1672 // SI pseudo instructions. These are used by the CFG structurizer pass
1673 // and should be lowered to ISA instructions prior to codegen.
1675 let mayLoad = 1, mayStore = 1, hasSideEffects = 1,
1676 Uses = [EXEC], Defs = [EXEC] in {
1678 let isBranch = 1, isTerminator = 1 in {
1681 (outs SReg_64:$dst),
1682 (ins SReg_64:$vcc, brtarget:$target),
1684 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))]
1687 def SI_ELSE : InstSI <
1688 (outs SReg_64:$dst),
1689 (ins SReg_64:$src, brtarget:$target),
1691 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]
1693 let Constraints = "$src = $dst";
1696 def SI_LOOP : InstSI <
1698 (ins SReg_64:$saved, brtarget:$target),
1699 "SI_LOOP $saved, $target",
1700 [(int_SI_loop i64:$saved, bb:$target)]
1703 } // end isBranch = 1, isTerminator = 1
1705 def SI_BREAK : InstSI <
1706 (outs SReg_64:$dst),
1708 "SI_ELSE $dst, $src",
1709 [(set i64:$dst, (int_SI_break i64:$src))]
1712 def SI_IF_BREAK : InstSI <
1713 (outs SReg_64:$dst),
1714 (ins SReg_64:$vcc, SReg_64:$src),
1715 "SI_IF_BREAK $dst, $vcc, $src",
1716 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))]
1719 def SI_ELSE_BREAK : InstSI <
1720 (outs SReg_64:$dst),
1721 (ins SReg_64:$src0, SReg_64:$src1),
1722 "SI_ELSE_BREAK $dst, $src0, $src1",
1723 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))]
1726 def SI_END_CF : InstSI <
1728 (ins SReg_64:$saved),
1730 [(int_SI_end_cf i64:$saved)]
1733 def SI_KILL : InstSI <
1737 [(int_AMDGPU_kill f32:$src)]
1740 } // end mayLoad = 1, mayStore = 1, hasSideEffects = 1
1741 // Uses = [EXEC], Defs = [EXEC]
1743 let Uses = [EXEC], Defs = [EXEC,VCC,M0] in {
1745 //defm SI_ : RegisterLoadStore <VReg_32, FRAMEri, ADDRIndirect>;
1747 let UseNamedOperandTable = 1 in {
1749 def SI_RegisterLoad : InstSI <
1750 (outs VReg_32:$dst, SReg_64:$temp),
1751 (ins FRAMEri32:$addr, i32imm:$chan),
1754 let isRegisterLoad = 1;
1758 class SIRegStore<dag outs> : InstSI <
1760 (ins VReg_32:$val, FRAMEri32:$addr, i32imm:$chan),
1763 let isRegisterStore = 1;
1767 let usesCustomInserter = 1 in {
1768 def SI_RegisterStorePseudo : SIRegStore<(outs)>;
1769 } // End usesCustomInserter = 1
1770 def SI_RegisterStore : SIRegStore<(outs SReg_64:$temp)>;
1773 } // End UseNamedOperandTable = 1
1775 def SI_INDIRECT_SRC : InstSI <
1776 (outs VReg_32:$dst, SReg_64:$temp),
1777 (ins unknown:$src, VSrc_32:$idx, i32imm:$off),
1778 "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off",
1782 class SI_INDIRECT_DST<RegisterClass rc> : InstSI <
1783 (outs rc:$dst, SReg_64:$temp),
1784 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val),
1785 "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val",
1788 let Constraints = "$src = $dst";
1791 def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VReg_32>;
1792 def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
1793 def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
1794 def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
1795 def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
1797 } // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0]
1799 let usesCustomInserter = 1 in {
1801 // This pseudo instruction takes a pointer as input and outputs a resource
1802 // constant that can be used with the ADDR64 MUBUF instructions.
1803 def SI_ADDR64_RSRC : InstSI <
1804 (outs SReg_128:$srsrc),
1809 def V_SUB_F64 : InstSI <
1810 (outs VReg_64:$dst),
1811 (ins VReg_64:$src0, VReg_64:$src1),
1812 "V_SUB_F64 $dst, $src0, $src1",
1813 [(set f64:$dst, (fsub f64:$src0, f64:$src1))]
1816 } // end usesCustomInserter
1818 multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
1820 def _SAVE : InstSI <
1822 (ins sgpr_class:$src, i32imm:$frame_idx),
1826 def _RESTORE : InstSI <
1827 (outs sgpr_class:$dst),
1828 (ins i32imm:$frame_idx),
1834 defm SI_SPILL_S32 : SI_SPILL_SGPR <SReg_32>;
1835 defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>;
1836 defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>;
1837 defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>;
1838 defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;
1840 multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> {
1841 def _SAVE : InstSI <
1843 (ins vgpr_class:$src, i32imm:$frame_idx),
1847 def _RESTORE : InstSI <
1848 (outs vgpr_class:$dst),
1849 (ins i32imm:$frame_idx),
1854 defm SI_SPILL_V32 : SI_SPILL_VGPR <VReg_32>;
1855 defm SI_SPILL_V64 : SI_SPILL_VGPR <VReg_64>;
1856 defm SI_SPILL_V96 : SI_SPILL_VGPR <VReg_96>;
1857 defm SI_SPILL_V128 : SI_SPILL_VGPR <VReg_128>;
1858 defm SI_SPILL_V256 : SI_SPILL_VGPR <VReg_256>;
1859 defm SI_SPILL_V512 : SI_SPILL_VGPR <VReg_512>;
1861 let Defs = [SCC] in {
1863 def SI_CONSTDATA_PTR : InstSI <
1864 (outs SReg_64:$dst),
1866 "", [(set SReg_64:$dst, (i64 SIconstdata_ptr))]
1869 } // End Defs = [SCC]
1871 } // end IsCodeGenOnly, isPseudo
1873 } // end SubtargetPredicate = SI
1875 let Predicates = [isSI] in {
1878 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2),
1879 (V_CNDMASK_B32_e64 $src2, $src1,
1880 (V_CMP_GT_F32_e64 SRCMODS.NONE, 0, SRCMODS.NONE, $src0,
1881 DSTCLAMP.NONE, DSTOMOD.NONE))
1886 (SI_KILL 0xbf800000)
1889 /* int_SI_vs_load_input */
1891 (SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr),
1892 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0)
1897 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
1898 f32:$src0, f32:$src1, f32:$src2, f32:$src3),
1899 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
1900 $src0, $src1, $src2, $src3)
1903 //===----------------------------------------------------------------------===//
1905 //===----------------------------------------------------------------------===//
1907 multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
1909 // 1. Offset as 8bit DWORD immediate
1911 (constant_load (add i64:$sbase, (i64 IMM8bitDWORD:$offset))),
1912 (vt (Instr_IMM $sbase, (as_dword_i32imm $offset)))
1915 // 2. Offset loaded in an 32bit SGPR
1917 (constant_load (add i64:$sbase, (i64 IMM32bit:$offset))),
1918 (vt (Instr_SGPR $sbase, (S_MOV_B32 (i32 (as_i32imm $offset)))))
1921 // 3. No offset at all
1923 (constant_load i64:$sbase),
1924 (vt (Instr_IMM $sbase, 0))
1928 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>;
1929 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
1930 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>;
1931 defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>;
1932 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
1933 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>;
1934 defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
1936 // 1. Offset as 8bit DWORD immediate
1938 (SIload_constant v4i32:$sbase, IMM8bitDWORD:$offset),
1939 (S_BUFFER_LOAD_DWORD_IMM $sbase, (as_dword_i32imm $offset))
1942 // 2. Offset loaded in an 32bit SGPR
1944 (SIload_constant v4i32:$sbase, imm:$offset),
1945 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset))
1948 } // Predicates = [isSI] in {
1950 //===----------------------------------------------------------------------===//
1952 //===----------------------------------------------------------------------===//
1955 (i64 (ctpop i64:$src)),
1956 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1957 (S_BCNT1_I32_B64 $src), sub0),
1958 (S_MOV_B32 0), sub1)
1961 //===----------------------------------------------------------------------===//
1963 //===----------------------------------------------------------------------===//
1965 // V_ADD_I32_e32/S_ADD_U32 produces carry in VCC/SCC. For the vector
1966 // case, the sgpr-copies pass will fix this to use the vector version.
1968 (i32 (addc i32:$src0, i32:$src1)),
1969 (S_ADD_U32 $src0, $src1)
1972 let Predicates = [isSI] in {
1974 //===----------------------------------------------------------------------===//
1976 //===----------------------------------------------------------------------===//
1979 (int_AMDGPU_barrier_global),
1983 //===----------------------------------------------------------------------===//
1985 //===----------------------------------------------------------------------===//
1987 let Predicates = [UnsafeFPMath] in {
1988 def : RcpPat<V_RCP_F64_e32, f64>;
1989 defm : RsqPat<V_RSQ_F64_e32, f64>;
1990 defm : RsqPat<V_RSQ_F32_e32, f32>;
1993 //===----------------------------------------------------------------------===//
1995 //===----------------------------------------------------------------------===//
1998 (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)),
1999 (V_BCNT_U32_B32_e64 $popcnt, $val)
2002 /********** ======================= **********/
2003 /********** Image sampling patterns **********/
2004 /********** ======================= **********/
2007 class SampleRawPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
2008 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i32:$unorm,
2009 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
2010 (opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da),
2011 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc),
2012 $addr, $rsrc, $sampler)
2015 multiclass SampleRawPatterns<SDPatternOperator name, string opcode> {
2016 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
2017 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
2018 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
2019 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V8), v8i32>;
2020 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V16), v16i32>;
2024 class ImagePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
2025 (name vt:$addr, v8i32:$rsrc, i32:$dmask, i32:$unorm,
2026 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
2027 (opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da),
2028 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc),
2032 multiclass ImagePatterns<SDPatternOperator name, string opcode> {
2033 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
2034 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
2035 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
2039 defm : SampleRawPatterns<int_SI_image_sample, "IMAGE_SAMPLE">;
2040 defm : SampleRawPatterns<int_SI_image_sample_cl, "IMAGE_SAMPLE_CL">;
2041 defm : SampleRawPatterns<int_SI_image_sample_d, "IMAGE_SAMPLE_D">;
2042 defm : SampleRawPatterns<int_SI_image_sample_d_cl, "IMAGE_SAMPLE_D_CL">;
2043 defm : SampleRawPatterns<int_SI_image_sample_l, "IMAGE_SAMPLE_L">;
2044 defm : SampleRawPatterns<int_SI_image_sample_b, "IMAGE_SAMPLE_B">;
2045 defm : SampleRawPatterns<int_SI_image_sample_b_cl, "IMAGE_SAMPLE_B_CL">;
2046 defm : SampleRawPatterns<int_SI_image_sample_lz, "IMAGE_SAMPLE_LZ">;
2047 defm : SampleRawPatterns<int_SI_image_sample_cd, "IMAGE_SAMPLE_CD">;
2048 defm : SampleRawPatterns<int_SI_image_sample_cd_cl, "IMAGE_SAMPLE_CD_CL">;
2050 // Sample with comparison
2051 defm : SampleRawPatterns<int_SI_image_sample_c, "IMAGE_SAMPLE_C">;
2052 defm : SampleRawPatterns<int_SI_image_sample_c_cl, "IMAGE_SAMPLE_C_CL">;
2053 defm : SampleRawPatterns<int_SI_image_sample_c_d, "IMAGE_SAMPLE_C_D">;
2054 defm : SampleRawPatterns<int_SI_image_sample_c_d_cl, "IMAGE_SAMPLE_C_D_CL">;
2055 defm : SampleRawPatterns<int_SI_image_sample_c_l, "IMAGE_SAMPLE_C_L">;
2056 defm : SampleRawPatterns<int_SI_image_sample_c_b, "IMAGE_SAMPLE_C_B">;
2057 defm : SampleRawPatterns<int_SI_image_sample_c_b_cl, "IMAGE_SAMPLE_C_B_CL">;
2058 defm : SampleRawPatterns<int_SI_image_sample_c_lz, "IMAGE_SAMPLE_C_LZ">;
2059 defm : SampleRawPatterns<int_SI_image_sample_c_cd, "IMAGE_SAMPLE_C_CD">;
2060 defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl, "IMAGE_SAMPLE_C_CD_CL">;
2062 // Sample with offsets
2063 defm : SampleRawPatterns<int_SI_image_sample_o, "IMAGE_SAMPLE_O">;
2064 defm : SampleRawPatterns<int_SI_image_sample_cl_o, "IMAGE_SAMPLE_CL_O">;
2065 defm : SampleRawPatterns<int_SI_image_sample_d_o, "IMAGE_SAMPLE_D_O">;
2066 defm : SampleRawPatterns<int_SI_image_sample_d_cl_o, "IMAGE_SAMPLE_D_CL_O">;
2067 defm : SampleRawPatterns<int_SI_image_sample_l_o, "IMAGE_SAMPLE_L_O">;
2068 defm : SampleRawPatterns<int_SI_image_sample_b_o, "IMAGE_SAMPLE_B_O">;
2069 defm : SampleRawPatterns<int_SI_image_sample_b_cl_o, "IMAGE_SAMPLE_B_CL_O">;
2070 defm : SampleRawPatterns<int_SI_image_sample_lz_o, "IMAGE_SAMPLE_LZ_O">;
2071 defm : SampleRawPatterns<int_SI_image_sample_cd_o, "IMAGE_SAMPLE_CD_O">;
2072 defm : SampleRawPatterns<int_SI_image_sample_cd_cl_o, "IMAGE_SAMPLE_CD_CL_O">;
2074 // Sample with comparison and offsets
2075 defm : SampleRawPatterns<int_SI_image_sample_c_o, "IMAGE_SAMPLE_C_O">;
2076 defm : SampleRawPatterns<int_SI_image_sample_c_cl_o, "IMAGE_SAMPLE_C_CL_O">;
2077 defm : SampleRawPatterns<int_SI_image_sample_c_d_o, "IMAGE_SAMPLE_C_D_O">;
2078 defm : SampleRawPatterns<int_SI_image_sample_c_d_cl_o, "IMAGE_SAMPLE_C_D_CL_O">;
2079 defm : SampleRawPatterns<int_SI_image_sample_c_l_o, "IMAGE_SAMPLE_C_L_O">;
2080 defm : SampleRawPatterns<int_SI_image_sample_c_b_o, "IMAGE_SAMPLE_C_B_O">;
2081 defm : SampleRawPatterns<int_SI_image_sample_c_b_cl_o, "IMAGE_SAMPLE_C_B_CL_O">;
2082 defm : SampleRawPatterns<int_SI_image_sample_c_lz_o, "IMAGE_SAMPLE_C_LZ_O">;
2083 defm : SampleRawPatterns<int_SI_image_sample_c_cd_o, "IMAGE_SAMPLE_C_CD_O">;
2084 defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl_o, "IMAGE_SAMPLE_C_CD_CL_O">;
2087 // Only the variants which make sense are defined.
2088 def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V2, v2i32>;
2089 def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V4, v4i32>;
2090 def : SampleRawPattern<int_SI_gather4_cl, IMAGE_GATHER4_CL_V4_V4, v4i32>;
2091 def : SampleRawPattern<int_SI_gather4_l, IMAGE_GATHER4_L_V4_V4, v4i32>;
2092 def : SampleRawPattern<int_SI_gather4_b, IMAGE_GATHER4_B_V4_V4, v4i32>;
2093 def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V4, v4i32>;
2094 def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V8, v8i32>;
2095 def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V2, v2i32>;
2096 def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V4, v4i32>;
2098 def : SampleRawPattern<int_SI_gather4_c, IMAGE_GATHER4_C_V4_V4, v4i32>;
2099 def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V4, v4i32>;
2100 def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V8, v8i32>;
2101 def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V4, v4i32>;
2102 def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V8, v8i32>;
2103 def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V4, v4i32>;
2104 def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V8, v8i32>;
2105 def : SampleRawPattern<int_SI_gather4_c_b_cl, IMAGE_GATHER4_C_B_CL_V4_V8, v8i32>;
2106 def : SampleRawPattern<int_SI_gather4_c_lz, IMAGE_GATHER4_C_LZ_V4_V4, v4i32>;
2108 def : SampleRawPattern<int_SI_gather4_o, IMAGE_GATHER4_O_V4_V4, v4i32>;
2109 def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V4, v4i32>;
2110 def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V8, v8i32>;
2111 def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V4, v4i32>;
2112 def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V8, v8i32>;
2113 def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V4, v4i32>;
2114 def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V8, v8i32>;
2115 def : SampleRawPattern<int_SI_gather4_b_cl_o, IMAGE_GATHER4_B_CL_O_V4_V8, v8i32>;
2116 def : SampleRawPattern<int_SI_gather4_lz_o, IMAGE_GATHER4_LZ_O_V4_V4, v4i32>;
2118 def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V4, v4i32>;
2119 def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V8, v8i32>;
2120 def : SampleRawPattern<int_SI_gather4_c_cl_o, IMAGE_GATHER4_C_CL_O_V4_V8, v8i32>;
2121 def : SampleRawPattern<int_SI_gather4_c_l_o, IMAGE_GATHER4_C_L_O_V4_V8, v8i32>;
2122 def : SampleRawPattern<int_SI_gather4_c_b_o, IMAGE_GATHER4_C_B_O_V4_V8, v8i32>;
2123 def : SampleRawPattern<int_SI_gather4_c_b_cl_o, IMAGE_GATHER4_C_B_CL_O_V4_V8, v8i32>;
2124 def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V4, v4i32>;
2125 def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V8, v8i32>;
2127 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V1, i32>;
2128 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V2, v2i32>;
2129 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V4, v4i32>;
2131 def : ImagePattern<int_SI_getresinfo, IMAGE_GET_RESINFO_V4_V1, i32>;
2132 defm : ImagePatterns<int_SI_image_load, "IMAGE_LOAD">;
2133 defm : ImagePatterns<int_SI_image_load_mip, "IMAGE_LOAD_MIP">;
2135 /* SIsample for simple 1D texture lookup */
2137 (SIsample i32:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
2138 (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2141 class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
2142 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
2143 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2146 class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
2147 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_RECT),
2148 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2151 class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
2152 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_ARRAY),
2153 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2156 class SampleShadowPattern<SDNode name, MIMG opcode,
2157 ValueType vt> : Pat <
2158 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW),
2159 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2162 class SampleShadowArrayPattern<SDNode name, MIMG opcode,
2163 ValueType vt> : Pat <
2164 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
2165 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2168 /* SIsample* for texture lookups consuming more address parameters */
2169 multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l,
2170 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b,
2171 MIMG sample_d, MIMG sample_c_d, ValueType addr_type> {
2172 def : SamplePattern <SIsample, sample, addr_type>;
2173 def : SampleRectPattern <SIsample, sample, addr_type>;
2174 def : SampleArrayPattern <SIsample, sample, addr_type>;
2175 def : SampleShadowPattern <SIsample, sample_c, addr_type>;
2176 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>;
2178 def : SamplePattern <SIsamplel, sample_l, addr_type>;
2179 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>;
2180 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>;
2181 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>;
2183 def : SamplePattern <SIsampleb, sample_b, addr_type>;
2184 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>;
2185 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>;
2186 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>;
2188 def : SamplePattern <SIsampled, sample_d, addr_type>;
2189 def : SampleArrayPattern <SIsampled, sample_d, addr_type>;
2190 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>;
2191 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>;
2194 defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2,
2195 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2,
2196 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2,
2197 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2,
2199 defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4,
2200 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4,
2201 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4,
2202 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4,
2204 defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8,
2205 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8,
2206 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8,
2207 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8,
2209 defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16,
2210 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16,
2211 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16,
2212 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16,
2215 /* int_SI_imageload for texture fetches consuming varying address parameters */
2216 class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2217 (name addr_type:$addr, v32i8:$rsrc, imm),
2218 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
2221 class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2222 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY),
2223 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
2226 class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2227 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA),
2228 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
2231 class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2232 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA),
2233 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
2236 multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> {
2237 def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>;
2238 def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>;
2241 multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> {
2242 def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>;
2243 def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>;
2246 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V2, v2i32>;
2247 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V4, v4i32>;
2249 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V2, v2i32>;
2250 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V4, v4i32>;
2252 /* Image resource information */
2254 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm),
2255 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
2259 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY),
2260 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
2264 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA),
2265 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
2268 /********** ============================================ **********/
2269 /********** Extraction, Insertion, Building and Casting **********/
2270 /********** ============================================ **********/
2272 foreach Index = 0-2 in {
2273 def Extract_Element_v2i32_#Index : Extract_Element <
2274 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
2276 def Insert_Element_v2i32_#Index : Insert_Element <
2277 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
2280 def Extract_Element_v2f32_#Index : Extract_Element <
2281 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
2283 def Insert_Element_v2f32_#Index : Insert_Element <
2284 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
2288 foreach Index = 0-3 in {
2289 def Extract_Element_v4i32_#Index : Extract_Element <
2290 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
2292 def Insert_Element_v4i32_#Index : Insert_Element <
2293 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
2296 def Extract_Element_v4f32_#Index : Extract_Element <
2297 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
2299 def Insert_Element_v4f32_#Index : Insert_Element <
2300 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
2304 foreach Index = 0-7 in {
2305 def Extract_Element_v8i32_#Index : Extract_Element <
2306 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
2308 def Insert_Element_v8i32_#Index : Insert_Element <
2309 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
2312 def Extract_Element_v8f32_#Index : Extract_Element <
2313 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
2315 def Insert_Element_v8f32_#Index : Insert_Element <
2316 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
2320 foreach Index = 0-15 in {
2321 def Extract_Element_v16i32_#Index : Extract_Element <
2322 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
2324 def Insert_Element_v16i32_#Index : Insert_Element <
2325 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
2328 def Extract_Element_v16f32_#Index : Extract_Element <
2329 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
2331 def Insert_Element_v16f32_#Index : Insert_Element <
2332 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
2336 def : BitConvert <i32, f32, SReg_32>;
2337 def : BitConvert <i32, f32, VReg_32>;
2339 def : BitConvert <f32, i32, SReg_32>;
2340 def : BitConvert <f32, i32, VReg_32>;
2342 def : BitConvert <i64, f64, VReg_64>;
2344 def : BitConvert <f64, i64, VReg_64>;
2346 def : BitConvert <v2f32, v2i32, VReg_64>;
2347 def : BitConvert <v2i32, v2f32, VReg_64>;
2348 def : BitConvert <v2i32, i64, VReg_64>;
2349 def : BitConvert <i64, v2i32, VReg_64>;
2350 def : BitConvert <v2f32, i64, VReg_64>;
2351 def : BitConvert <i64, v2f32, VReg_64>;
2352 def : BitConvert <v2i32, f64, VReg_64>;
2353 def : BitConvert <f64, v2i32, VReg_64>;
2354 def : BitConvert <v4f32, v4i32, VReg_128>;
2355 def : BitConvert <v4i32, v4f32, VReg_128>;
2357 def : BitConvert <v8f32, v8i32, SReg_256>;
2358 def : BitConvert <v8i32, v8f32, SReg_256>;
2359 def : BitConvert <v8i32, v32i8, SReg_256>;
2360 def : BitConvert <v32i8, v8i32, SReg_256>;
2361 def : BitConvert <v8i32, v32i8, VReg_256>;
2362 def : BitConvert <v8i32, v8f32, VReg_256>;
2363 def : BitConvert <v8f32, v8i32, VReg_256>;
2364 def : BitConvert <v32i8, v8i32, VReg_256>;
2366 def : BitConvert <v16i32, v16f32, VReg_512>;
2367 def : BitConvert <v16f32, v16i32, VReg_512>;
2369 /********** =================== **********/
2370 /********** Src & Dst modifiers **********/
2371 /********** =================== **********/
2373 def FCLAMP_SI : AMDGPUShaderInst <
2374 (outs VReg_32:$dst),
2375 (ins VSrc_32:$src0),
2376 "FCLAMP_SI $dst, $src0",
2379 let usesCustomInserter = 1;
2383 (AMDGPUclamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)),
2384 (FCLAMP_SI f32:$src)
2387 /********** ================================ **********/
2388 /********** Floating point absolute/negative **********/
2389 /********** ================================ **********/
2391 // Prevent expanding both fneg and fabs.
2393 // FIXME: Should use S_OR_B32
2395 (fneg (fabs f32:$src)),
2396 (V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
2399 // FIXME: Should use S_OR_B32
2401 (fneg (fabs f64:$src)),
2403 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2404 (i32 (EXTRACT_SUBREG f64:$src, sub0)), sub0),
2405 (V_OR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
2406 (V_MOV_B32_e32 0x80000000)), sub1)) // Set sign bit.
2411 (V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff))
2416 (V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000))
2422 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2423 (i32 (EXTRACT_SUBREG f64:$src, sub0)), sub0),
2424 (V_AND_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
2425 (V_MOV_B32_e32 0x7fffffff)), sub1)) // Set sign bit.
2431 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2432 (i32 (EXTRACT_SUBREG f64:$src, sub0)), sub0),
2433 (V_XOR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
2434 (V_MOV_B32_e32 0x80000000)), sub1))
2437 /********** ================== **********/
2438 /********** Immediate Patterns **********/
2439 /********** ================== **********/
2442 (SGPRImm<(i32 imm)>:$imm),
2443 (S_MOV_B32 imm:$imm)
2447 (SGPRImm<(f32 fpimm)>:$imm),
2448 (S_MOV_B32 fpimm:$imm)
2453 (V_MOV_B32_e32 imm:$imm)
2458 (V_MOV_B32_e32 fpimm:$imm)
2462 (i64 InlineImm<i64>:$imm),
2463 (S_MOV_B64 InlineImm<i64>:$imm)
2466 /********** ===================== **********/
2467 /********** Interpolation Paterns **********/
2468 /********** ===================== **********/
2471 (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params),
2472 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, $params)
2476 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, v2i32:$ij),
2477 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0),
2478 imm:$attr_chan, imm:$attr, i32:$params),
2479 (EXTRACT_SUBREG $ij, sub1),
2480 imm:$attr_chan, imm:$attr, $params)
2483 /********** ================== **********/
2484 /********** Intrinsic Patterns **********/
2485 /********** ================== **********/
2487 /* llvm.AMDGPU.pow */
2488 def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>;
2491 (int_AMDGPU_div f32:$src0, f32:$src1),
2492 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1))
2496 (fdiv f64:$src0, f64:$src1),
2497 (V_MUL_F64 0 /* src0_modifiers */, $src0,
2498 0 /* src1_modifiers */, (V_RCP_F64_e32 $src1),
2499 0 /* clamp */, 0 /* omod */)
2503 (int_AMDGPU_cube v4f32:$src),
2504 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2505 (V_CUBETC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
2506 0 /* src1_modifiers */, (EXTRACT_SUBREG $src, sub1),
2507 0 /* src2_modifiers */, (EXTRACT_SUBREG $src, sub2),
2508 0 /* clamp */, 0 /* omod */),
2510 (V_CUBESC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
2511 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2512 0 /* src2_modifiers */,(EXTRACT_SUBREG $src, sub2),
2513 0 /* clamp */, 0 /* omod */),
2515 (V_CUBEMA_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0),
2516 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2517 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2),
2518 0 /* clamp */, 0 /* omod */),
2520 (V_CUBEID_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0),
2521 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2522 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2),
2523 0 /* clamp */, 0 /* omod */),
2528 (i32 (sext i1:$src0)),
2529 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
2532 class Ext32Pat <SDNode ext> : Pat <
2533 (i32 (ext i1:$src0)),
2534 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0)
2537 def : Ext32Pat <zext>;
2538 def : Ext32Pat <anyext>;
2540 // Offset in an 32Bit VGPR
2542 (SIload_constant v4i32:$sbase, i32:$voff),
2543 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0, 0)
2546 // The multiplication scales from [0,1] to the unsigned integer range
2548 (AMDGPUurecip i32:$src0),
2550 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1,
2551 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
2556 (V_MBCNT_HI_U32_B32_e32 0xffffffff,
2557 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0))
2560 //===----------------------------------------------------------------------===//
2562 //===----------------------------------------------------------------------===//
2564 def : IMad24Pat<V_MAD_I32_I24>;
2565 def : UMad24Pat<V_MAD_U32_U24>;
2568 (mulhu i32:$src0, i32:$src1),
2569 (V_MUL_HI_U32 $src0, $src1)
2573 (mulhs i32:$src0, i32:$src1),
2574 (V_MUL_HI_I32 $src0, $src1)
2577 def : Vop3ModPat<V_MAD_F32, VOP_F32_F32_F32_F32, AMDGPUmad>;
2580 defm : BFIPatterns <V_BFI_B32, S_MOV_B32>;
2581 def : ROTRPattern <V_ALIGNBIT_B32>;
2583 /********** ======================= **********/
2584 /********** Load/Store Patterns **********/
2585 /********** ======================= **********/
2587 class DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat <
2588 (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
2589 (inst (i1 0), $ptr, (as_i16imm $offset))
2592 def : DSReadPat <DS_READ_I8, i32, sextloadi8_local>;
2593 def : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>;
2594 def : DSReadPat <DS_READ_I16, i32, sextloadi16_local>;
2595 def : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>;
2596 def : DSReadPat <DS_READ_B32, i32, local_load>;
2598 let AddedComplexity = 100 in {
2600 def : DSReadPat <DS_READ_B64, v2i32, local_load_aligned8bytes>;
2602 } // End AddedComplexity = 100
2605 (v2i32 (local_load (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
2607 (DS_READ2_B32 (i1 0), $ptr, $offset0, $offset1)
2610 class DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat <
2611 (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
2612 (inst (i1 0), $ptr, $value, (as_i16imm $offset))
2615 def : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>;
2616 def : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>;
2617 def : DSWritePat <DS_WRITE_B32, i32, local_store>;
2619 let AddedComplexity = 100 in {
2621 def : DSWritePat <DS_WRITE_B64, v2i32, local_store_aligned8bytes>;
2622 } // End AddedComplexity = 100
2625 (local_store v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
2627 (DS_WRITE2_B32 (i1 0), $ptr, (EXTRACT_SUBREG $value, sub0),
2628 (EXTRACT_SUBREG $value, sub1), $offset0, $offset1)
2631 class DSAtomicRetPat<DS inst, ValueType vt, PatFrag frag> : Pat <
2632 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
2633 (inst (i1 0), $ptr, $value, (as_i16imm $offset))
2636 // Special case of DSAtomicRetPat for add / sub 1 -> inc / dec
2638 // We need to use something for the data0, so we set a register to
2639 // -1. For the non-rtn variants, the manual says it does
2640 // DS[A] = (DS[A] >= D0) ? 0 : DS[A] + 1, and setting D0 to uint_max
2641 // will always do the increment so I'm assuming it's the same.
2643 // We also load this -1 with s_mov_b32 / s_mov_b64 even though this
2644 // needs to be a VGPR. The SGPR copy pass will fix this, and it's
2645 // easier since there is no v_mov_b64.
2646 class DSAtomicIncRetPat<DS inst, ValueType vt,
2647 Instruction LoadImm, PatFrag frag> : Pat <
2648 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), (vt 1)),
2649 (inst (i1 0), $ptr, (LoadImm (vt -1)), (as_i16imm $offset))
2653 class DSAtomicCmpXChg <DS inst, ValueType vt, PatFrag frag> : Pat <
2654 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
2655 (inst (i1 0), $ptr, $cmp, $swap, (as_i16imm $offset))
2660 def : DSAtomicIncRetPat<DS_INC_RTN_U32, i32,
2661 S_MOV_B32, atomic_load_add_local>;
2662 def : DSAtomicIncRetPat<DS_DEC_RTN_U32, i32,
2663 S_MOV_B32, atomic_load_sub_local>;
2665 def : DSAtomicRetPat<DS_WRXCHG_RTN_B32, i32, atomic_swap_local>;
2666 def : DSAtomicRetPat<DS_ADD_RTN_U32, i32, atomic_load_add_local>;
2667 def : DSAtomicRetPat<DS_SUB_RTN_U32, i32, atomic_load_sub_local>;
2668 def : DSAtomicRetPat<DS_AND_RTN_B32, i32, atomic_load_and_local>;
2669 def : DSAtomicRetPat<DS_OR_RTN_B32, i32, atomic_load_or_local>;
2670 def : DSAtomicRetPat<DS_XOR_RTN_B32, i32, atomic_load_xor_local>;
2671 def : DSAtomicRetPat<DS_MIN_RTN_I32, i32, atomic_load_min_local>;
2672 def : DSAtomicRetPat<DS_MAX_RTN_I32, i32, atomic_load_max_local>;
2673 def : DSAtomicRetPat<DS_MIN_RTN_U32, i32, atomic_load_umin_local>;
2674 def : DSAtomicRetPat<DS_MAX_RTN_U32, i32, atomic_load_umax_local>;
2676 def : DSAtomicCmpXChg<DS_CMPST_RTN_B32, i32, atomic_cmp_swap_32_local>;
2679 def : DSAtomicIncRetPat<DS_INC_RTN_U64, i64,
2680 S_MOV_B64, atomic_load_add_local>;
2681 def : DSAtomicIncRetPat<DS_DEC_RTN_U64, i64,
2682 S_MOV_B64, atomic_load_sub_local>;
2684 def : DSAtomicRetPat<DS_WRXCHG_RTN_B64, i64, atomic_swap_local>;
2685 def : DSAtomicRetPat<DS_ADD_RTN_U64, i64, atomic_load_add_local>;
2686 def : DSAtomicRetPat<DS_SUB_RTN_U64, i64, atomic_load_sub_local>;
2687 def : DSAtomicRetPat<DS_AND_RTN_B64, i64, atomic_load_and_local>;
2688 def : DSAtomicRetPat<DS_OR_RTN_B64, i64, atomic_load_or_local>;
2689 def : DSAtomicRetPat<DS_XOR_RTN_B64, i64, atomic_load_xor_local>;
2690 def : DSAtomicRetPat<DS_MIN_RTN_I64, i64, atomic_load_min_local>;
2691 def : DSAtomicRetPat<DS_MAX_RTN_I64, i64, atomic_load_max_local>;
2692 def : DSAtomicRetPat<DS_MIN_RTN_U64, i64, atomic_load_umin_local>;
2693 def : DSAtomicRetPat<DS_MAX_RTN_U64, i64, atomic_load_umax_local>;
2695 def : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, atomic_cmp_swap_64_local>;
2698 //===----------------------------------------------------------------------===//
2700 //===----------------------------------------------------------------------===//
2702 multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
2703 PatFrag constant_ld> {
2705 (vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))),
2706 (Instr_ADDR64 $srsrc, $vaddr, $offset)
2710 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, sextloadi8_constant>;
2711 defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, az_extloadi8_constant>;
2712 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_constant>;
2713 defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, az_extloadi16_constant>;
2714 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32, constant_load>;
2715 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32, constant_load>;
2716 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32, constant_load>;
2718 class MUBUFScratchLoadPat <MUBUF Instr, ValueType vt, PatFrag ld> : Pat <
2719 (vt (ld (MUBUFScratch v4i32:$srsrc, i32:$vaddr,
2720 i32:$soffset, u16imm:$offset))),
2721 (Instr $srsrc, $vaddr, $soffset, $offset, 0, 0, 0)
2724 def : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, i32, sextloadi8_private>;
2725 def : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, i32, extloadi8_private>;
2726 def : MUBUFScratchLoadPat <BUFFER_LOAD_SSHORT_OFFEN, i32, sextloadi16_private>;
2727 def : MUBUFScratchLoadPat <BUFFER_LOAD_USHORT_OFFEN, i32, extloadi16_private>;
2728 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORD_OFFEN, i32, load_private>;
2729 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX2_OFFEN, v2i32, load_private>;
2730 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX4_OFFEN, v4i32, load_private>;
2732 // BUFFER_LOAD_DWORD*, addr64=0
2733 multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen,
2737 (vt (int_SI_buffer_load_dword v4i32:$rsrc, (i32 imm), i32:$soffset,
2738 imm:$offset, 0, 0, imm:$glc, imm:$slc,
2740 (offset $rsrc, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2741 (as_i1imm $slc), (as_i1imm $tfe))
2745 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2746 imm:$offset, 1, 0, imm:$glc, imm:$slc,
2748 (offen $rsrc, $vaddr, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc),
2753 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2754 imm:$offset, 0, 1, imm:$glc, imm:$slc,
2756 (idxen $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2757 (as_i1imm $slc), (as_i1imm $tfe))
2761 (vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset,
2762 imm, 1, 1, imm:$glc, imm:$slc,
2764 (bothen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
2769 defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN,
2770 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
2771 defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN,
2772 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>;
2773 defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN,
2774 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
2776 class MUBUFScratchStorePat <MUBUF Instr, ValueType vt, PatFrag st> : Pat <
2777 (st vt:$value, (MUBUFScratch v4i32:$srsrc, i32:$vaddr, i32:$soffset,
2779 (Instr $value, $srsrc, $vaddr, $soffset, $offset, 0, 0, 0)
2782 def : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, i32, truncstorei8_private>;
2783 def : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, i32, truncstorei16_private>;
2784 def : MUBUFScratchStorePat <BUFFER_STORE_DWORD_OFFEN, i32, store_private>;
2785 def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX2_OFFEN, v2i32, store_private>;
2786 def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, v4i32, store_private>;
2789 class MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> : Pat <
2790 (st vt:$value, (MUBUFScratch v4i32:$srsrc, i64:$vaddr, u16imm:$offset)),
2791 (Instr $value, $srsrc, $vaddr, $offset)
2794 def : MUBUFStore_Pattern <BUFFER_STORE_BYTE_ADDR64, i32, truncstorei8_private>;
2795 def : MUBUFStore_Pattern <BUFFER_STORE_SHORT_ADDR64, i32, truncstorei16_private>;
2796 def : MUBUFStore_Pattern <BUFFER_STORE_DWORD_ADDR64, i32, store_private>;
2797 def : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2_ADDR64, v2i32, store_private>;
2798 def : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4_ADDR64, v4i32, store_private>;
2802 //===----------------------------------------------------------------------===//
2804 //===----------------------------------------------------------------------===//
2806 // TBUFFER_STORE_FORMAT_*, addr64=0
2807 class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat<
2808 (SItbuffer_store v4i32:$rsrc, vt:$vdata, num_channels, i32:$vaddr,
2809 i32:$soffset, imm:$inst_offset, imm:$dfmt,
2810 imm:$nfmt, imm:$offen, imm:$idxen,
2811 imm:$glc, imm:$slc, imm:$tfe),
2813 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen),
2814 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc,
2815 (as_i1imm $slc), (as_i1imm $tfe), $soffset)
2818 def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>;
2819 def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>;
2820 def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>;
2821 def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>;
2823 let SubtargetPredicate = isCI in {
2825 // Sea island new arithmetic instructinos
2826 defm V_TRUNC_F64 : VOP1Inst <vop1<0x17>, "V_TRUNC_F64",
2829 defm V_CEIL_F64 : VOP1Inst <vop1<0x18>, "V_CEIL_F64",
2832 defm V_FLOOR_F64 : VOP1Inst <vop1<0x1A>, "V_FLOOR_F64",
2835 defm V_RNDNE_F64 : VOP1Inst <vop1<0x19>, "V_RNDNE_F64",
2839 defm V_QSAD_PK_U16_U8 : VOP3Inst <vop3<0x173>, "V_QSAD_PK_U16_U8",
2842 defm V_MQSAD_U16_U8 : VOP3Inst <vop3<0x172>, "V_MQSAD_U16_U8",
2845 defm V_MQSAD_U32_U8 : VOP3Inst <vop3<0x175>, "V_MQSAD_U32_U8",
2848 defm V_MAD_U64_U32 : VOP3Inst <vop3<0x176>, "V_MAD_U64_U32",
2852 // XXX - Does this set VCC?
2853 defm V_MAD_I64_I32 : VOP3Inst <vop3<0x177>, "V_MAD_I64_I32",
2857 // Remaining instructions:
2859 // S_CBRANCH_CDBGUSER
2860 // S_CBRANCH_CDBGSYS
2861 // S_CBRANCH_CDBGSYS_OR_USER
2862 // S_CBRANCH_CDBGSYS_AND_USER
2867 // DS_GWS_SEMA_RELEASE_ALL
2869 // DS_CNDXCHG32_RTN_B64
2872 // DS_CONDXCHG32_RTN_B128
2875 // BUFFER_LOAD_DWORDX3
2876 // BUFFER_STORE_DWORDX3
2880 //===----------------------------------------------------------------------===//
2882 //===----------------------------------------------------------------------===//
2884 class FLATLoad_Pattern <FLAT Instr_ADDR64, ValueType vt,
2886 Pat <(vt (flat_ld i64:$ptr)),
2890 def : FLATLoad_Pattern <FLAT_LOAD_SBYTE, i32, sextloadi8_flat>;
2891 def : FLATLoad_Pattern <FLAT_LOAD_UBYTE, i32, az_extloadi8_flat>;
2892 def : FLATLoad_Pattern <FLAT_LOAD_SSHORT, i32, sextloadi16_flat>;
2893 def : FLATLoad_Pattern <FLAT_LOAD_USHORT, i32, az_extloadi16_flat>;
2894 def : FLATLoad_Pattern <FLAT_LOAD_DWORD, i32, flat_load>;
2895 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX2, i64, flat_load>;
2896 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX2, i64, az_extloadi32_flat>;
2897 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX2, v2i32, flat_load>;
2898 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX4, v4i32, flat_load>;
2900 class FLATStore_Pattern <FLAT Instr, ValueType vt, PatFrag st> :
2901 Pat <(st vt:$value, i64:$ptr),
2902 (Instr $value, $ptr)
2905 def : FLATStore_Pattern <FLAT_STORE_BYTE, i32, truncstorei8_flat>;
2906 def : FLATStore_Pattern <FLAT_STORE_SHORT, i32, truncstorei16_flat>;
2907 def : FLATStore_Pattern <FLAT_STORE_DWORD, i32, flat_store>;
2908 def : FLATStore_Pattern <FLAT_STORE_DWORDX2, i64, flat_store>;
2909 def : FLATStore_Pattern <FLAT_STORE_DWORDX2, v2i32, flat_store>;
2910 def : FLATStore_Pattern <FLAT_STORE_DWORDX4, v4i32, flat_store>;
2912 /********** ====================== **********/
2913 /********** Indirect adressing **********/
2914 /********** ====================== **********/
2916 multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, SI_INDIRECT_DST IndDst> {
2918 // 1. Extract with offset
2920 (vector_extract vt:$vec, (add i32:$idx, imm:$off)),
2921 (eltvt (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off))
2924 // 2. Extract without offset
2926 (vector_extract vt:$vec, i32:$idx),
2927 (eltvt (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0))
2930 // 3. Insert with offset
2932 (vector_insert vt:$vec, eltvt:$val, (add i32:$idx, imm:$off)),
2933 (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val)
2936 // 4. Insert without offset
2938 (vector_insert vt:$vec, eltvt:$val, i32:$idx),
2939 (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val)
2943 defm : SI_INDIRECT_Pattern <v2f32, f32, SI_INDIRECT_DST_V2>;
2944 defm : SI_INDIRECT_Pattern <v4f32, f32, SI_INDIRECT_DST_V4>;
2945 defm : SI_INDIRECT_Pattern <v8f32, f32, SI_INDIRECT_DST_V8>;
2946 defm : SI_INDIRECT_Pattern <v16f32, f32, SI_INDIRECT_DST_V16>;
2948 defm : SI_INDIRECT_Pattern <v2i32, i32, SI_INDIRECT_DST_V2>;
2949 defm : SI_INDIRECT_Pattern <v4i32, i32, SI_INDIRECT_DST_V4>;
2950 defm : SI_INDIRECT_Pattern <v8i32, i32, SI_INDIRECT_DST_V8>;
2951 defm : SI_INDIRECT_Pattern <v16i32, i32, SI_INDIRECT_DST_V16>;
2953 //===----------------------------------------------------------------------===//
2954 // Conversion Patterns
2955 //===----------------------------------------------------------------------===//
2957 def : Pat<(i32 (sext_inreg i32:$src, i1)),
2958 (S_BFE_I32 i32:$src, 65536)>; // 0 | 1 << 16
2960 // TODO: Match 64-bit BFE. SI has a 64-bit BFE, but it's scalar only so it
2961 // might not be worth the effort, and will need to expand to shifts when
2962 // fixing SGPR copies.
2964 // Handle sext_inreg in i64
2966 (i64 (sext_inreg i64:$src, i1)),
2967 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2968 (S_BFE_I32 (EXTRACT_SUBREG i64:$src, sub0), 65536), sub0), // 0 | 1 << 16
2969 (S_MOV_B32 -1), sub1)
2973 (i64 (sext_inreg i64:$src, i8)),
2974 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2975 (S_SEXT_I32_I8 (EXTRACT_SUBREG i64:$src, sub0)), sub0),
2976 (S_MOV_B32 -1), sub1)
2980 (i64 (sext_inreg i64:$src, i16)),
2981 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2982 (S_SEXT_I32_I16 (EXTRACT_SUBREG i64:$src, sub0)), sub0),
2983 (S_MOV_B32 -1), sub1)
2986 class ZExt_i64_i32_Pat <SDNode ext> : Pat <
2987 (i64 (ext i32:$src)),
2988 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $src, sub0),
2989 (S_MOV_B32 0), sub1)
2992 class ZExt_i64_i1_Pat <SDNode ext> : Pat <
2993 (i64 (ext i1:$src)),
2995 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2996 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src), sub0),
2997 (S_MOV_B32 0), sub1)
3001 def : ZExt_i64_i32_Pat<zext>;
3002 def : ZExt_i64_i32_Pat<anyext>;
3003 def : ZExt_i64_i1_Pat<zext>;
3004 def : ZExt_i64_i1_Pat<anyext>;
3007 (i64 (sext i32:$src)),
3009 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $src, sub0),
3010 (S_ASHR_I32 $src, 31), sub1)
3014 (i64 (sext i1:$src)),
3017 (i64 (IMPLICIT_DEF)),
3018 (V_CNDMASK_B32_e64 0, -1, $src), sub0),
3019 (V_CNDMASK_B32_e64 0, -1, $src), sub1)
3023 (f32 (sint_to_fp i1:$src)),
3024 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_NEG_ONE, $src)
3028 (f32 (uint_to_fp i1:$src)),
3029 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_ONE, $src)
3033 (f64 (sint_to_fp i1:$src)),
3034 (V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src))
3038 (f64 (uint_to_fp i1:$src)),
3039 (V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src))
3042 //===----------------------------------------------------------------------===//
3043 // Miscellaneous Patterns
3044 //===----------------------------------------------------------------------===//
3047 (i32 (trunc i64:$a)),
3048 (EXTRACT_SUBREG $a, sub0)
3052 (i1 (trunc i32:$a)),
3053 (V_CMP_EQ_I32_e64 (V_AND_B32_e64 (i32 1), $a), 1)
3056 //============================================================================//
3057 // Miscellaneous Optimization Patterns
3058 //============================================================================//
3060 def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e64>;
3062 } // End isSI predicate