1 //===-- SIInstructions.td - SI Instruction Defintions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This file was originally auto-generated from a GPU register header file and
10 // all the instruction definitions were originally commented out. Instructions
11 // that are not yet supported remain commented out.
12 //===----------------------------------------------------------------------===//
19 def INTERP : InterpSlots;
21 def InterpSlot : Operand<i32> {
22 let PrintMethod = "printInterpSlot";
25 def isSI : Predicate<"Subtarget.getGeneration() "
26 "== AMDGPUSubtarget::SOUTHERN_ISLANDS">;
28 let Predicates = [isSI] in {
30 let neverHasSideEffects = 1 in {
32 let isMoveImm = 1 in {
33 def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>;
34 def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>;
35 def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>;
36 def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>;
37 } // End isMoveImm = 1
39 def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32", []>;
40 def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", []>;
41 def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>;
42 def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>;
43 def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>;
44 def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>;
45 } // End neverHasSideEffects = 1
47 ////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>;
48 ////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>;
49 ////def S_BCNT1_I32_B32 : SOP1_BCNT1 <0x0000000f, "S_BCNT1_I32_B32", []>;
50 ////def S_BCNT1_I32_B64 : SOP1_BCNT1 <0x00000010, "S_BCNT1_I32_B64", []>;
51 ////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>;
52 ////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>;
53 ////def S_FF1_I32_B32 : SOP1_FF1 <0x00000013, "S_FF1_I32_B32", []>;
54 ////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>;
55 //def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", []>;
56 //def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>;
57 def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>;
58 //def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>;
59 //def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8", []>;
60 //def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16", []>;
61 ////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>;
62 ////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>;
63 ////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>;
64 ////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>;
65 def S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>;
66 def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>;
67 def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>;
68 def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>;
70 let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in {
72 def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>;
73 def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>;
74 def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>;
75 def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>;
76 def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>;
77 def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>;
78 def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>;
79 def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>;
81 } // End hasSideEffects = 1
83 def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>;
84 def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>;
85 def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>;
86 def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>;
87 def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>;
88 def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>;
89 //def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>;
90 def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>;
91 def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>;
92 def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>;
93 def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>;
94 def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>;
97 This instruction is disabled for now until we can figure out how to teach
98 the instruction selector to correctly use the S_CMP* vs V_CMP*
101 When this instruction is enabled the code generator sometimes produces this
104 SCC = S_CMPK_EQ_I32 SGPR0, imm
106 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
108 def S_CMPK_EQ_I32 : SOPK <
109 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1),
111 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))]
115 let isCompare = 1 in {
116 def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>;
117 def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>;
118 def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>;
119 def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>;
120 def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>;
121 def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>;
122 def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>;
123 def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>;
124 def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>;
125 def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>;
126 def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>;
127 } // End isCompare = 1
129 def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>;
130 def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>;
131 //def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>;
132 def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>;
133 def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>;
134 def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>;
135 //def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>;
136 //def EXP : EXP_ <0x00000000, "EXP", []>;
138 let isCompare = 1 in {
140 defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">;
141 defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_LT>;
142 defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", f32, COND_EQ>;
143 defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", f32, COND_LE>;
144 defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", f32, COND_GT>;
145 defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32", f32, COND_NE>;
146 defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", f32, COND_GE>;
147 defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32">;
148 defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32">;
149 defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32">;
150 defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32">;
151 defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32">;
152 defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32">;
153 defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", f32, COND_NE>;
154 defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">;
155 defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">;
157 let hasSideEffects = 1, Defs = [EXEC] in {
159 defm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32">;
160 defm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32">;
161 defm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32">;
162 defm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32">;
163 defm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32">;
164 defm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32">;
165 defm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32">;
166 defm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32">;
167 defm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32">;
168 defm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32">;
169 defm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32">;
170 defm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32">;
171 defm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32">;
172 defm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32">;
173 defm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32">;
174 defm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32">;
176 } // End hasSideEffects = 1, Defs = [EXEC]
178 defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">;
179 defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64", f64, COND_LT>;
180 defm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64", f64, COND_EQ>;
181 defm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64", f64, COND_LE>;
182 defm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64", f64, COND_GT>;
183 defm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64">;
184 defm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64", f64, COND_GE>;
185 defm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64">;
186 defm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64">;
187 defm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64">;
188 defm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64">;
189 defm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64">;
190 defm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64">;
191 defm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64", f64, COND_NE>;
192 defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">;
193 defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">;
195 let hasSideEffects = 1, Defs = [EXEC] in {
197 defm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64">;
198 defm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64">;
199 defm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64">;
200 defm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64">;
201 defm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64">;
202 defm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64">;
203 defm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64">;
204 defm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64">;
205 defm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64">;
206 defm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64">;
207 defm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64">;
208 defm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64">;
209 defm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64">;
210 defm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64">;
211 defm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64">;
212 defm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64">;
214 } // End hasSideEffects = 1, Defs = [EXEC]
216 defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">;
217 defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">;
218 defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32">;
219 defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32">;
220 defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32">;
221 defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32">;
222 defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32">;
223 defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32">;
224 defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32">;
225 defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32">;
226 defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32">;
227 defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32">;
228 defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32">;
229 defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">;
230 defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">;
231 defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">;
233 let hasSideEffects = 1, Defs = [EXEC] in {
235 defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32">;
236 defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32">;
237 defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32">;
238 defm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32">;
239 defm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32">;
240 defm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32">;
241 defm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32">;
242 defm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32">;
243 defm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32">;
244 defm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32">;
245 defm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32">;
246 defm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32">;
247 defm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32">;
248 defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32">;
249 defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32">;
250 defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32">;
252 } // End hasSideEffects = 1, Defs = [EXEC]
254 defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">;
255 defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">;
256 defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">;
257 defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64">;
258 defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64">;
259 defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64">;
260 defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64">;
261 defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64">;
262 defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64">;
263 defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64">;
264 defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64">;
265 defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64">;
266 defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64">;
267 defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">;
268 defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">;
269 defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">;
271 let hasSideEffects = 1, Defs = [EXEC] in {
273 defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">;
274 defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">;
275 defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">;
276 defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64">;
277 defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64">;
278 defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64">;
279 defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64">;
280 defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64">;
281 defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64">;
282 defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64">;
283 defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64">;
284 defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64">;
285 defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64">;
286 defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">;
287 defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">;
288 defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">;
290 } // End hasSideEffects = 1, Defs = [EXEC]
292 defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">;
293 defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_LT>;
294 defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>;
295 defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", i32, COND_LE>;
296 defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", i32, COND_GT>;
297 defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", i32, COND_NE>;
298 defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_GE>;
299 defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">;
301 let hasSideEffects = 1, Defs = [EXEC] in {
303 defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32">;
304 defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32">;
305 defm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32">;
306 defm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32">;
307 defm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32">;
308 defm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32">;
309 defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32">;
310 defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32">;
312 } // End hasSideEffects = 1, Defs = [EXEC]
314 defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">;
315 defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64">;
316 defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64">;
317 defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64">;
318 defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64">;
319 defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64">;
320 defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64">;
321 defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">;
323 let hasSideEffects = 1, Defs = [EXEC] in {
325 defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64">;
326 defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64">;
327 defm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64">;
328 defm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64">;
329 defm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64">;
330 defm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64">;
331 defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64">;
332 defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64">;
334 } // End hasSideEffects = 1, Defs = [EXEC]
336 defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">;
337 defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32">;
338 defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32">;
339 defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32">;
340 defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32">;
341 defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32">;
342 defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32">;
343 defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">;
345 let hasSideEffects = 1, Defs = [EXEC] in {
347 defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32">;
348 defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32">;
349 defm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32">;
350 defm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32">;
351 defm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32">;
352 defm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32">;
353 defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32">;
354 defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32">;
356 } // End hasSideEffects = 1, Defs = [EXEC]
358 defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">;
359 defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64">;
360 defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64">;
361 defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64">;
362 defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64">;
363 defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64">;
364 defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64">;
365 defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">;
367 let hasSideEffects = 1, Defs = [EXEC] in {
369 defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64">;
370 defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64">;
371 defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64">;
372 defm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64">;
373 defm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64">;
374 defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64">;
375 defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64">;
376 defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64">;
378 } // End hasSideEffects = 1, Defs = [EXEC]
380 defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">;
382 let hasSideEffects = 1, Defs = [EXEC] in {
383 defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">;
384 } // End hasSideEffects = 1, Defs = [EXEC]
386 defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">;
388 let hasSideEffects = 1, Defs = [EXEC] in {
389 defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">;
390 } // End hasSideEffects = 1, Defs = [EXEC]
392 } // End isCompare = 1
394 def DS_ADD_U32_RTN : DS_1A1D_RET <0x20, "DS_ADD_U32_RTN", VReg_32>;
395 def DS_SUB_U32_RTN : DS_1A1D_RET <0x21, "DS_SUB_U32_RTN", VReg_32>;
396 def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>;
397 def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "DS_WRITE_B8", VReg_32>;
398 def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "DS_WRITE_B16", VReg_32>;
399 def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>;
400 def DS_READ_I8 : DS_Load_Helper <0x00000039, "DS_READ_I8", VReg_32>;
401 def DS_READ_U8 : DS_Load_Helper <0x0000003a, "DS_READ_U8", VReg_32>;
402 def DS_READ_I16 : DS_Load_Helper <0x0000003b, "DS_READ_I16", VReg_32>;
403 def DS_READ_U16 : DS_Load_Helper <0x0000003c, "DS_READ_U16", VReg_32>;
405 //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>;
406 //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>;
407 //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>;
408 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>;
409 //def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>;
410 //def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>;
411 //def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>;
412 //def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>;
413 defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <0x00000008, "BUFFER_LOAD_UBYTE", VReg_32>;
414 defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <0x00000009, "BUFFER_LOAD_SBYTE", VReg_32>;
415 defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <0x0000000a, "BUFFER_LOAD_USHORT", VReg_32>;
416 defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32>;
417 defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <0x0000000c, "BUFFER_LOAD_DWORD", VReg_32>;
418 defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64>;
419 defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128>;
421 def BUFFER_STORE_BYTE : MUBUF_Store_Helper <
422 0x00000018, "BUFFER_STORE_BYTE", VReg_32
425 def BUFFER_STORE_SHORT : MUBUF_Store_Helper <
426 0x0000001a, "BUFFER_STORE_SHORT", VReg_32
429 def BUFFER_STORE_DWORD : MUBUF_Store_Helper <
430 0x0000001c, "BUFFER_STORE_DWORD", VReg_32
433 def BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper <
434 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64
437 def BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper <
438 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128
440 //def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>;
441 //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>;
442 //def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>;
443 //def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>;
444 //def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>;
445 //def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>;
446 //def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>;
447 //def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>;
448 //def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>;
449 //def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>;
450 //def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>;
451 //def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>;
452 //def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>;
453 //def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>;
454 //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>;
455 //def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>;
456 //def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>;
457 //def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>;
458 //def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>;
459 //def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>;
460 //def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>;
461 //def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>;
462 //def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>;
463 //def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>;
464 //def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>;
465 //def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>;
466 //def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>;
467 //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>;
468 //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>;
469 //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>;
470 //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>;
471 //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>;
472 //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>;
473 //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>;
474 //def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>;
475 //def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>;
476 //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>;
477 //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>;
478 //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>;
479 def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>;
480 //def TBUFFER_STORE_FORMAT_X : MTBUF_ <0x00000004, "TBUFFER_STORE_FORMAT_X", []>;
481 //def TBUFFER_STORE_FORMAT_XY : MTBUF_ <0x00000005, "TBUFFER_STORE_FORMAT_XY", []>;
482 //def TBUFFER_STORE_FORMAT_XYZ : MTBUF_ <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", []>;
483 //def TBUFFER_STORE_FORMAT_XYZW : MTBUF_ <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", []>;
487 defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SReg_32>;
488 defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>;
489 defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>;
490 defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>;
491 defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>;
493 defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
494 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SReg_32
497 defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
498 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64
501 defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper <
502 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128
505 defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <
506 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256
509 defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
510 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512
515 //def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>;
516 //def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>;
517 defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "IMAGE_LOAD">;
518 defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "IMAGE_LOAD_MIP">;
519 //def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>;
520 //def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>;
521 //def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>;
522 //def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>;
523 //def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>;
524 //def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>;
525 //def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>;
526 //def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>;
527 def IMAGE_GET_RESINFO : MIMG_NoSampler_Helper <0x0000000e, "IMAGE_GET_RESINFO", VReg_32>;
528 //def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>;
529 //def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>;
530 //def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>;
531 //def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>;
532 //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>;
533 //def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>;
534 //def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>;
535 //def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>;
536 //def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>;
537 //def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>;
538 //def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>;
539 //def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>;
540 //def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>;
541 //def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>;
542 //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>;
543 //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>;
544 //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>;
545 defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">;
546 //def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>;
547 defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">;
548 //def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>;
549 defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">;
550 defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">;
551 //def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>;
552 //def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>;
553 defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">;
554 //def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>;
555 defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">;
556 //def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>;
557 defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">;
558 defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">;
559 //def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>;
560 //def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>;
561 //def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>;
562 //def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>;
563 //def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>;
564 //def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>;
565 //def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>;
566 //def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>;
567 //def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>;
568 //def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>;
569 //def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>;
570 //def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>;
571 //def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>;
572 //def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>;
573 //def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>;
574 //def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>;
575 //def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>;
576 //def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>;
577 //def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>;
578 //def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>;
579 //def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>;
580 //def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>;
581 //def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>;
582 //def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>;
583 //def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>;
584 //def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>;
585 //def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>;
586 //def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>;
587 //def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>;
588 //def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>;
589 //def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>;
590 //def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>;
591 //def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>;
592 //def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>;
593 //def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>;
594 //def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>;
595 //def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>;
596 //def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>;
597 //def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>;
598 //def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>;
599 //def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>;
600 //def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>;
601 //def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>;
602 //def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>;
603 //def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>;
604 //def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>;
605 //def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>;
606 //def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>;
607 //def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>;
608 //def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>;
609 //def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>;
610 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>;
611 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>;
612 //def V_NOP : VOP1_ <0x00000000, "V_NOP", []>;
615 let neverHasSideEffects = 1, isMoveImm = 1 in {
616 defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>;
617 } // End neverHasSideEffects = 1, isMoveImm = 1
619 defm V_READFIRSTLANE_B32 : VOP1_32 <0x00000002, "V_READFIRSTLANE_B32", []>;
620 defm V_CVT_I32_F64 : VOP1_32_64 <0x00000003, "V_CVT_I32_F64",
621 [(set i32:$dst, (fp_to_sint f64:$src0))]
623 defm V_CVT_F64_I32 : VOP1_64_32 <0x00000004, "V_CVT_F64_I32",
624 [(set f64:$dst, (sint_to_fp i32:$src0))]
626 defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32",
627 [(set f32:$dst, (sint_to_fp i32:$src0))]
629 defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32",
630 [(set f32:$dst, (uint_to_fp i32:$src0))]
632 defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32",
633 [(set i32:$dst, (fp_to_uint f32:$src0))]
635 defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32",
636 [(set i32:$dst, (fp_to_sint f32:$src0))]
638 defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>;
639 ////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>;
640 //defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>;
641 //defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>;
642 //defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>;
643 //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>;
644 defm V_CVT_F32_F64 : VOP1_32_64 <0x0000000f, "V_CVT_F32_F64",
645 [(set f32:$dst, (fround f64:$src0))]
647 defm V_CVT_F64_F32 : VOP1_64_32 <0x00000010, "V_CVT_F64_F32",
648 [(set f64:$dst, (fextend f32:$src0))]
650 //defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0", []>;
651 //defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1", []>;
652 //defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2", []>;
653 //defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", []>;
654 //defm V_CVT_U32_F64 : VOP1_32 <0x00000015, "V_CVT_U32_F64", []>;
655 //defm V_CVT_F64_U32 : VOP1_64 <0x00000016, "V_CVT_F64_U32", []>;
656 defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32",
657 [(set f32:$dst, (AMDGPUfract f32:$src0))]
659 defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32",
660 [(set f32:$dst, (int_AMDGPU_trunc f32:$src0))]
662 defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32",
663 [(set f32:$dst, (fceil f32:$src0))]
665 defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32",
666 [(set f32:$dst, (frint f32:$src0))]
668 defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32",
669 [(set f32:$dst, (ffloor f32:$src0))]
671 defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32",
672 [(set f32:$dst, (fexp2 f32:$src0))]
674 defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>;
675 defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32",
676 [(set f32:$dst, (flog2 f32:$src0))]
678 defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>;
679 defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>;
680 defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32",
681 [(set f32:$dst, (fdiv FP_ONE, f32:$src0))]
683 defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>;
684 defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>;
685 defm V_RSQ_LEGACY_F32 : VOP1_32 <
686 0x0000002d, "V_RSQ_LEGACY_F32",
687 [(set f32:$dst, (int_AMDGPU_rsq f32:$src0))]
689 defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32", []>;
690 defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64",
691 [(set f64:$dst, (fdiv FP_ONE, f64:$src0))]
693 defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>;
694 defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64", []>;
695 defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>;
696 defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32",
697 [(set f32:$dst, (fsqrt f32:$src0))]
699 defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64",
700 [(set f64:$dst, (fsqrt f64:$src0))]
702 defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>;
703 defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>;
704 defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>;
705 defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>;
706 defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>;
707 defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>;
708 defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>;
709 //defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>;
710 defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>;
711 defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>;
712 //defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>;
713 defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>;
714 //def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>;
715 defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>;
716 defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>;
717 defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>;
719 def V_INTERP_P1_F32 : VINTRP <
722 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
723 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]",
725 let DisableEncoding = "$m0";
728 def V_INTERP_P2_F32 : VINTRP <
731 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
732 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]",
735 let Constraints = "$src0 = $dst";
736 let DisableEncoding = "$src0,$m0";
740 def V_INTERP_MOV_F32 : VINTRP <
743 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
744 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]",
746 let DisableEncoding = "$m0";
749 //def S_NOP : SOPP_ <0x00000000, "S_NOP", []>;
751 let isTerminator = 1 in {
753 def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM",
760 let isBranch = 1 in {
761 def S_BRANCH : SOPP <
762 0x00000002, (ins brtarget:$target), "S_BRANCH $target",
767 let DisableEncoding = "$scc" in {
768 def S_CBRANCH_SCC0 : SOPP <
769 0x00000004, (ins brtarget:$target, SCCReg:$scc),
770 "S_CBRANCH_SCC0 $target", []
772 def S_CBRANCH_SCC1 : SOPP <
773 0x00000005, (ins brtarget:$target, SCCReg:$scc),
774 "S_CBRANCH_SCC1 $target",
777 } // End DisableEncoding = "$scc"
779 def S_CBRANCH_VCCZ : SOPP <
780 0x00000006, (ins brtarget:$target, VCCReg:$vcc),
781 "S_CBRANCH_VCCZ $target",
784 def S_CBRANCH_VCCNZ : SOPP <
785 0x00000007, (ins brtarget:$target, VCCReg:$vcc),
786 "S_CBRANCH_VCCNZ $target",
790 let DisableEncoding = "$exec" in {
791 def S_CBRANCH_EXECZ : SOPP <
792 0x00000008, (ins brtarget:$target, EXECReg:$exec),
793 "S_CBRANCH_EXECZ $target",
796 def S_CBRANCH_EXECNZ : SOPP <
797 0x00000009, (ins brtarget:$target, EXECReg:$exec),
798 "S_CBRANCH_EXECNZ $target",
801 } // End DisableEncoding = "$exec"
804 } // End isBranch = 1
805 } // End isTerminator = 1
807 let hasSideEffects = 1 in {
808 def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER",
809 [(int_AMDGPU_barrier_local)]
818 def S_WAITCNT : SOPP <0x0000000c, (ins i32imm:$simm16), "S_WAITCNT $simm16",
821 } // End hasSideEffects
822 //def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>;
823 //def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>;
824 //def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>;
825 //def S_SENDMSG : SOPP_ <0x00000010, "S_SENDMSG", []>;
826 //def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>;
827 //def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>;
828 //def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>;
829 //def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>;
830 //def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>;
831 //def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
833 def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
834 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc),
835 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]",
838 let DisableEncoding = "$vcc";
841 def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst),
842 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2,
843 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
844 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg",
845 [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))]
848 //f32 pattern for V_CNDMASK_B32_e64
850 (f32 (select i1:$src2, f32:$src1, f32:$src0)),
851 (V_CNDMASK_B32_e64 $src0, $src1, $src2)
854 //use two V_CNDMASK_B32_e64 instructions for f64
856 (f64 (select i1:$src2, f64:$src1, f64:$src0)),
857 (INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
858 (V_CNDMASK_B32_e64 (EXTRACT_SUBREG $src0, sub0),
859 (EXTRACT_SUBREG $src1, sub0),
861 (V_CNDMASK_B32_e64 (EXTRACT_SUBREG $src0, sub1),
862 (EXTRACT_SUBREG $src1, sub1),
866 defm V_READLANE_B32 : VOP2_32 <0x00000001, "V_READLANE_B32", []>;
867 defm V_WRITELANE_B32 : VOP2_32 <0x00000002, "V_WRITELANE_B32", []>;
869 let isCommutable = 1 in {
870 defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32",
871 [(set f32:$dst, (fadd f32:$src0, f32:$src1))]
874 defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32",
875 [(set f32:$dst, (fsub f32:$src0, f32:$src1))]
877 defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", [], "V_SUB_F32">;
878 } // End isCommutable = 1
880 defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>;
882 let isCommutable = 1 in {
884 defm V_MUL_LEGACY_F32 : VOP2_32 <
885 0x00000007, "V_MUL_LEGACY_F32",
886 [(set f32:$dst, (int_AMDGPU_mul f32:$src0, f32:$src1))]
889 defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32",
890 [(set f32:$dst, (fmul f32:$src0, f32:$src1))]
894 defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24",
895 [(set i32:$dst, (mul I24:$src0, I24:$src1))]
897 //defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>;
898 defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24",
899 [(set i32:$dst, (mul U24:$src0, U24:$src1))]
901 //defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>;
904 defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32",
905 [(set f32:$dst, (AMDGPUfmin f32:$src0, f32:$src1))]
908 defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32",
909 [(set f32:$dst, (AMDGPUfmax f32:$src0, f32:$src1))]
912 defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>;
913 defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>;
914 defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32",
915 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]
917 defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32",
918 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]
920 defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32",
921 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]
923 defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32",
924 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]
927 defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32",
928 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
930 defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">;
932 defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32",
933 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
935 defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">;
937 defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32",
938 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
940 defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">;
942 defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32",
943 [(set i32:$dst, (and i32:$src0, i32:$src1))]
945 defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32",
946 [(set i32:$dst, (or i32:$src0, i32:$src1))]
948 defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32",
949 [(set i32:$dst, (xor i32:$src0, i32:$src1))]
952 } // End isCommutable = 1
954 defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32", []>;
955 defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>;
956 defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>;
957 defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>;
958 //defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>;
959 defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>;
960 defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>;
962 let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC
963 defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32",
964 [(set i32:$dst, (add (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))]
967 defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32",
968 [(set i32:$dst, (sub i32:$src0, i32:$src1))]
970 defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], "V_SUB_I32">;
972 let Uses = [VCC] in { // Carry-out comes from VCC
973 defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", []>;
974 defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", []>;
975 defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], "V_SUBB_U32">;
976 } // End Uses = [VCC]
977 } // End isCommutable = 1, Defs = [VCC]
979 defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>;
980 ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>;
981 ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>;
982 ////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>;
983 defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32",
984 [(set i32:$dst, (int_SI_packf16 f32:$src0, f32:$src1))]
986 ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>;
987 ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>;
988 def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32", []>;
989 def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32", []>;
990 def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32", []>;
991 def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32", []>;
992 def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32", []>;
993 def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32", []>;
994 def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32", []>;
995 def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32", []>;
996 def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32", []>;
997 def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32", []>;
998 def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32", []>;
999 def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32", []>;
1000 ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>;
1001 ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>;
1002 ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>;
1003 ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>;
1004 //def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>;
1006 let neverHasSideEffects = 1 in {
1008 def V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>;
1009 def V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", []>;
1010 def V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24",
1011 [(set i32:$dst, (add (mul I24:$src0, I24:$src1), i32:$src2))]
1013 def V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24",
1014 [(set i32:$dst, (add (mul U24:$src0, U24:$src1), i32:$src2))]
1017 } // End neverHasSideEffects
1018 def V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>;
1019 def V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>;
1020 def V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>;
1021 def V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>;
1022 def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", []>;
1023 def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", []>;
1024 def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", []>;
1025 defm : BFIPatterns <V_BFI_B32>;
1026 def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32",
1027 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))]
1029 def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64",
1030 [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
1032 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>;
1033 def V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>;
1034 def : ROTRPattern <V_ALIGNBIT_B32>;
1036 def V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>;
1037 def V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>;
1038 ////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>;
1039 ////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>;
1040 ////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>;
1041 ////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>;
1042 ////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>;
1043 ////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>;
1044 ////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>;
1045 ////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>;
1046 ////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>;
1047 //def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>;
1048 //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>;
1049 //def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>;
1050 def V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>;
1051 ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>;
1052 def V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>;
1053 def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>;
1055 def V_LSHL_B64 : VOP3_64_Shift <0x00000161, "V_LSHL_B64",
1056 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
1058 def V_LSHR_B64 : VOP3_64_Shift <0x00000162, "V_LSHR_B64",
1059 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
1061 def V_ASHR_I64 : VOP3_64_Shift <0x00000163, "V_ASHR_I64",
1062 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
1065 let isCommutable = 1 in {
1067 def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>;
1068 def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>;
1069 def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>;
1070 def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>;
1072 } // isCommutable = 1
1075 (fadd f64:$src0, f64:$src1),
1076 (V_ADD_F64 $src0, $src1, (i64 0))
1080 (fmul f64:$src0, f64:$src1),
1081 (V_MUL_F64 $src0, $src1, (i64 0))
1084 def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>;
1086 let isCommutable = 1 in {
1088 def V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>;
1089 def V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>;
1090 def V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>;
1091 def V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>;
1093 } // isCommutable = 1
1096 (mul i32:$src0, i32:$src1),
1097 (V_MUL_LO_I32 $src0, $src1, (i32 0))
1101 (mulhu i32:$src0, i32:$src1),
1102 (V_MUL_HI_U32 $src0, $src1, (i32 0))
1106 (mulhs i32:$src0, i32:$src1),
1107 (V_MUL_HI_I32 $src0, $src1, (i32 0))
1110 def V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>;
1111 def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>;
1112 def V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>;
1113 def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>;
1114 //def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>;
1115 //def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>;
1116 //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>;
1117 def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>;
1118 def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>;
1119 def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>;
1120 def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32", []>;
1121 def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32", []>;
1122 def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32", []>;
1123 def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32", []>;
1124 def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32", []>;
1125 def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32", []>;
1126 def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32", []>;
1127 def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32", []>;
1129 def S_CSELECT_B32 : SOP2 <
1130 0x0000000a, (outs SReg_32:$dst),
1131 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32",
1135 def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>;
1137 def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32", []>;
1139 def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64",
1140 [(set i64:$dst, (and i64:$src0, i64:$src1))]
1144 (i1 (and i1:$src0, i1:$src1)),
1145 (S_AND_B64 $src0, $src1)
1148 def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32", []>;
1149 def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64", []>;
1151 (i1 (or i1:$src0, i1:$src1)),
1152 (S_OR_B64 $src0, $src1)
1154 def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32", []>;
1155 def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64",
1156 [(set i1:$dst, (xor i1:$src0, i1:$src1))]
1158 def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>;
1159 def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>;
1160 def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>;
1161 def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>;
1162 def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>;
1163 def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>;
1164 def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>;
1165 def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>;
1166 def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>;
1167 def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>;
1168 def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32", []>;
1169 def S_LSHL_B64 : SOP2_64 <0x0000001f, "S_LSHL_B64", []>;
1170 def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32", []>;
1171 def S_LSHR_B64 : SOP2_64 <0x00000021, "S_LSHR_B64", []>;
1172 def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32", []>;
1173 def S_ASHR_I64 : SOP2_64 <0x00000023, "S_ASHR_I64", []>;
1174 def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>;
1175 def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>;
1176 def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>;
1177 def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>;
1178 def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>;
1179 def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>;
1180 def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>;
1181 //def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>;
1182 def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>;
1184 let isCodeGenOnly = 1, isPseudo = 1 in {
1186 def LOAD_CONST : AMDGPUShaderInst <
1189 "LOAD_CONST $dst, $src",
1190 [(set GPRF32:$dst, (int_AMDGPU_load_const imm:$src))]
1193 // SI Psuedo instructions. These are used by the CFG structurizer pass
1194 // and should be lowered to ISA instructions prior to codegen.
1196 let mayLoad = 1, mayStore = 1, hasSideEffects = 1,
1197 Uses = [EXEC], Defs = [EXEC] in {
1199 let isBranch = 1, isTerminator = 1 in {
1201 def SI_IF : InstSI <
1202 (outs SReg_64:$dst),
1203 (ins SReg_64:$vcc, brtarget:$target),
1204 "SI_IF $dst, $vcc, $target",
1205 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))]
1208 def SI_ELSE : InstSI <
1209 (outs SReg_64:$dst),
1210 (ins SReg_64:$src, brtarget:$target),
1211 "SI_ELSE $dst, $src, $target",
1212 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]> {
1214 let Constraints = "$src = $dst";
1217 def SI_LOOP : InstSI <
1219 (ins SReg_64:$saved, brtarget:$target),
1220 "SI_LOOP $saved, $target",
1221 [(int_SI_loop i64:$saved, bb:$target)]
1224 } // end isBranch = 1, isTerminator = 1
1226 def SI_BREAK : InstSI <
1227 (outs SReg_64:$dst),
1229 "SI_ELSE $dst, $src",
1230 [(set i64:$dst, (int_SI_break i64:$src))]
1233 def SI_IF_BREAK : InstSI <
1234 (outs SReg_64:$dst),
1235 (ins SReg_64:$vcc, SReg_64:$src),
1236 "SI_IF_BREAK $dst, $vcc, $src",
1237 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))]
1240 def SI_ELSE_BREAK : InstSI <
1241 (outs SReg_64:$dst),
1242 (ins SReg_64:$src0, SReg_64:$src1),
1243 "SI_ELSE_BREAK $dst, $src0, $src1",
1244 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))]
1247 def SI_END_CF : InstSI <
1249 (ins SReg_64:$saved),
1251 [(int_SI_end_cf i64:$saved)]
1254 def SI_KILL : InstSI <
1258 [(int_AMDGPU_kill f32:$src)]
1261 } // end mayLoad = 1, mayStore = 1, hasSideEffects = 1
1262 // Uses = [EXEC], Defs = [EXEC]
1264 let Uses = [EXEC], Defs = [EXEC,VCC,M0] in {
1266 def SI_INDIRECT_SRC : InstSI <
1267 (outs VReg_32:$dst, SReg_64:$temp),
1268 (ins unknown:$src, VSrc_32:$idx, i32imm:$off),
1269 "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off",
1273 class SI_INDIRECT_DST<RegisterClass rc> : InstSI <
1274 (outs rc:$dst, SReg_64:$temp),
1275 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val),
1276 "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val",
1279 let Constraints = "$src = $dst";
1282 def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
1283 def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
1284 def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
1285 def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
1287 } // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0]
1289 let usesCustomInserter = 1 in {
1291 // This psuedo instruction takes a pointer as input and outputs a resource
1292 // constant that can be used with the ADDR64 MUBUF instructions.
1293 def SI_ADDR64_RSRC : InstSI <
1294 (outs SReg_128:$srsrc),
1299 def V_SUB_F64 : InstSI <
1300 (outs VReg_64:$dst),
1301 (ins VReg_64:$src0, VReg_64:$src1),
1302 "V_SUB_F64 $dst, $src0, $src1",
1306 } // end usesCustomInserter
1308 } // end IsCodeGenOnly, isPseudo
1311 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2),
1312 (V_CNDMASK_B32_e64 $src2, $src1, (V_CMP_GT_F32_e64 0, $src0))
1317 (SI_KILL (V_MOV_B32_e32 0xbf800000))
1320 /* int_SI_vs_load_input */
1322 (SIload_input i128:$tlst, IMM12bit:$attr_offset, i32:$buf_idx_vgpr),
1323 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset)
1328 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
1329 f32:$src0, f32:$src1, f32:$src2, f32:$src3),
1330 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
1331 $src0, $src1, $src2, $src3)
1335 (f64 (fsub f64:$src0, f64:$src1)),
1336 (V_SUB_F64 $src0, $src1)
1339 /********** ======================= **********/
1340 /********** Image sampling patterns **********/
1341 /********** ======================= **********/
1343 /* SIsample for simple 1D texture lookup */
1345 (SIsample i32:$addr, v32i8:$rsrc, i128:$sampler, imm),
1346 (IMAGE_SAMPLE_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1349 class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1350 (name vt:$addr, v32i8:$rsrc, i128:$sampler, imm),
1351 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1354 class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1355 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_RECT),
1356 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1359 class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1360 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_ARRAY),
1361 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1364 class SampleShadowPattern<SDNode name, MIMG opcode,
1365 ValueType vt> : Pat <
1366 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_SHADOW),
1367 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1370 class SampleShadowArrayPattern<SDNode name, MIMG opcode,
1371 ValueType vt> : Pat <
1372 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_SHADOW_ARRAY),
1373 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1376 /* SIsample* for texture lookups consuming more address parameters */
1377 multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l,
1378 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b,
1379 MIMG sample_d, MIMG sample_c_d, ValueType addr_type> {
1380 def : SamplePattern <SIsample, sample, addr_type>;
1381 def : SampleRectPattern <SIsample, sample, addr_type>;
1382 def : SampleArrayPattern <SIsample, sample, addr_type>;
1383 def : SampleShadowPattern <SIsample, sample_c, addr_type>;
1384 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>;
1386 def : SamplePattern <SIsamplel, sample_l, addr_type>;
1387 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>;
1388 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>;
1389 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>;
1391 def : SamplePattern <SIsampleb, sample_b, addr_type>;
1392 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>;
1393 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>;
1394 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>;
1396 def : SamplePattern <SIsampled, sample_d, addr_type>;
1397 def : SampleArrayPattern <SIsampled, sample_d, addr_type>;
1398 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>;
1399 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>;
1402 defm : SamplePatterns<IMAGE_SAMPLE_V2, IMAGE_SAMPLE_C_V2,
1403 IMAGE_SAMPLE_L_V2, IMAGE_SAMPLE_C_L_V2,
1404 IMAGE_SAMPLE_B_V2, IMAGE_SAMPLE_C_B_V2,
1405 IMAGE_SAMPLE_D_V2, IMAGE_SAMPLE_C_D_V2,
1407 defm : SamplePatterns<IMAGE_SAMPLE_V4, IMAGE_SAMPLE_C_V4,
1408 IMAGE_SAMPLE_L_V4, IMAGE_SAMPLE_C_L_V4,
1409 IMAGE_SAMPLE_B_V4, IMAGE_SAMPLE_C_B_V4,
1410 IMAGE_SAMPLE_D_V4, IMAGE_SAMPLE_C_D_V4,
1412 defm : SamplePatterns<IMAGE_SAMPLE_V8, IMAGE_SAMPLE_C_V8,
1413 IMAGE_SAMPLE_L_V8, IMAGE_SAMPLE_C_L_V8,
1414 IMAGE_SAMPLE_B_V8, IMAGE_SAMPLE_C_B_V8,
1415 IMAGE_SAMPLE_D_V8, IMAGE_SAMPLE_C_D_V8,
1417 defm : SamplePatterns<IMAGE_SAMPLE_V16, IMAGE_SAMPLE_C_V16,
1418 IMAGE_SAMPLE_L_V16, IMAGE_SAMPLE_C_L_V16,
1419 IMAGE_SAMPLE_B_V16, IMAGE_SAMPLE_C_B_V16,
1420 IMAGE_SAMPLE_D_V16, IMAGE_SAMPLE_C_D_V16,
1423 /* int_SI_imageload for texture fetches consuming varying address parameters */
1424 class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1425 (name addr_type:$addr, v32i8:$rsrc, imm),
1426 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
1429 class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1430 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY),
1431 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
1434 class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1435 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA),
1436 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
1439 class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1440 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA),
1441 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
1444 multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> {
1445 def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>;
1446 def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>;
1449 multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> {
1450 def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>;
1451 def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>;
1454 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V2, v2i32>;
1455 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4, v4i32>;
1457 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V2, v2i32>;
1458 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4, v4i32>;
1460 /* Image resource information */
1462 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm),
1463 (IMAGE_GET_RESINFO 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1467 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY),
1468 (IMAGE_GET_RESINFO 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1472 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA),
1473 (IMAGE_GET_RESINFO 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1476 /********** ============================================ **********/
1477 /********** Extraction, Insertion, Building and Casting **********/
1478 /********** ============================================ **********/
1480 foreach Index = 0-2 in {
1481 def Extract_Element_v2i32_#Index : Extract_Element <
1482 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
1484 def Insert_Element_v2i32_#Index : Insert_Element <
1485 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
1488 def Extract_Element_v2f32_#Index : Extract_Element <
1489 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
1491 def Insert_Element_v2f32_#Index : Insert_Element <
1492 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
1496 foreach Index = 0-3 in {
1497 def Extract_Element_v4i32_#Index : Extract_Element <
1498 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
1500 def Insert_Element_v4i32_#Index : Insert_Element <
1501 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
1504 def Extract_Element_v4f32_#Index : Extract_Element <
1505 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
1507 def Insert_Element_v4f32_#Index : Insert_Element <
1508 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
1512 foreach Index = 0-7 in {
1513 def Extract_Element_v8i32_#Index : Extract_Element <
1514 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
1516 def Insert_Element_v8i32_#Index : Insert_Element <
1517 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
1520 def Extract_Element_v8f32_#Index : Extract_Element <
1521 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
1523 def Insert_Element_v8f32_#Index : Insert_Element <
1524 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
1528 foreach Index = 0-15 in {
1529 def Extract_Element_v16i32_#Index : Extract_Element <
1530 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
1532 def Insert_Element_v16i32_#Index : Insert_Element <
1533 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
1536 def Extract_Element_v16f32_#Index : Extract_Element <
1537 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
1539 def Insert_Element_v16f32_#Index : Insert_Element <
1540 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
1544 def : BitConvert <i32, f32, SReg_32>;
1545 def : BitConvert <i32, f32, VReg_32>;
1547 def : BitConvert <f32, i32, SReg_32>;
1548 def : BitConvert <f32, i32, VReg_32>;
1550 def : BitConvert <i64, f64, VReg_64>;
1552 def : BitConvert <f64, i64, VReg_64>;
1554 def : BitConvert <v2f32, v2i32, VReg_64>;
1555 def : BitConvert <v2i32, v2f32, VReg_64>;
1557 def : BitConvert <v4f32, v4i32, VReg_128>;
1558 def : BitConvert <v4i32, v4f32, VReg_128>;
1560 def : BitConvert <v8i32, v32i8, SReg_256>;
1561 def : BitConvert <v32i8, v8i32, SReg_256>;
1562 def : BitConvert <v8i32, v32i8, VReg_256>;
1563 def : BitConvert <v32i8, v8i32, VReg_256>;
1565 /********** =================== **********/
1566 /********** Src & Dst modifiers **********/
1567 /********** =================== **********/
1570 (int_AMDIL_clamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)),
1571 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
1572 0 /* ABS */, 1 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */)
1577 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
1578 1 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */)
1583 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
1584 0 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 1 /* NEG */)
1587 /********** ================== **********/
1588 /********** Immediate Patterns **********/
1589 /********** ================== **********/
1592 (SGPRImm<(i32 imm)>:$imm),
1593 (S_MOV_B32 imm:$imm)
1597 (SGPRImm<(f32 fpimm)>:$imm),
1598 (S_MOV_B32 fpimm:$imm)
1603 (V_MOV_B32_e32 imm:$imm)
1608 (V_MOV_B32_e32 fpimm:$imm)
1613 (S_MOV_B64 imm:$imm)
1617 (i64 InlineImm<i64>:$imm),
1618 (S_MOV_B64 InlineImm<i64>:$imm)
1621 // i64 immediates aren't supported in hardware, split it into two 32bit values
1624 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1625 (S_MOV_B32 (i32 (LO32 imm:$imm))), sub0),
1626 (S_MOV_B32 (i32 (HI32 imm:$imm))), sub1)
1631 (INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
1632 (V_MOV_B32_e32 (f32 (LO32f fpimm:$imm))), sub0),
1633 (V_MOV_B32_e32 (f32 (HI32f fpimm:$imm))), sub1)
1636 /********** ===================== **********/
1637 /********** Interpolation Paterns **********/
1638 /********** ===================== **********/
1641 (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params),
1642 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, $params)
1646 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, v2i32:$ij),
1647 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0),
1648 imm:$attr_chan, imm:$attr, i32:$params),
1649 (EXTRACT_SUBREG $ij, sub1),
1650 imm:$attr_chan, imm:$attr, $params)
1653 /********** ================== **********/
1654 /********** Intrinsic Patterns **********/
1655 /********** ================== **********/
1657 /* llvm.AMDGPU.pow */
1658 def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>;
1661 (int_AMDGPU_div f32:$src0, f32:$src1),
1662 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1))
1666 (fdiv f32:$src0, f32:$src1),
1667 (V_MUL_F32_e32 $src0, (V_RCP_F32_e32 $src1))
1671 (fdiv f64:$src0, f64:$src1),
1672 (V_MUL_F64 $src0, (V_RCP_F64_e32 $src1), (i64 0))
1677 (V_COS_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
1682 (V_SIN_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
1686 (int_AMDGPU_cube v4f32:$src),
1687 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
1688 (V_CUBETC_F32 (EXTRACT_SUBREG $src, sub0),
1689 (EXTRACT_SUBREG $src, sub1),
1690 (EXTRACT_SUBREG $src, sub2)),
1692 (V_CUBESC_F32 (EXTRACT_SUBREG $src, sub0),
1693 (EXTRACT_SUBREG $src, sub1),
1694 (EXTRACT_SUBREG $src, sub2)),
1696 (V_CUBEMA_F32 (EXTRACT_SUBREG $src, sub0),
1697 (EXTRACT_SUBREG $src, sub1),
1698 (EXTRACT_SUBREG $src, sub2)),
1700 (V_CUBEID_F32 (EXTRACT_SUBREG $src, sub0),
1701 (EXTRACT_SUBREG $src, sub1),
1702 (EXTRACT_SUBREG $src, sub2)),
1707 (i32 (sext i1:$src0)),
1708 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
1711 // 1. Offset as 8bit DWORD immediate
1713 (SIload_constant i128:$sbase, IMM8bitDWORD:$offset),
1714 (S_BUFFER_LOAD_DWORD_IMM $sbase, IMM8bitDWORD:$offset)
1717 // 2. Offset loaded in an 32bit SGPR
1719 (SIload_constant i128:$sbase, imm:$offset),
1720 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset))
1723 // 3. Offset in an 32Bit VGPR
1725 (SIload_constant i128:$sbase, i32:$voff),
1726 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff)
1729 // The multiplication scales from [0,1] to the unsigned integer range
1731 (AMDGPUurecip i32:$src0),
1733 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1,
1734 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
1739 (V_MBCNT_HI_U32_B32_e32 0xffffffff,
1740 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0, 0, 0, 0, 0))
1743 /********** ================== **********/
1744 /********** VOP3 Patterns **********/
1745 /********** ================== **********/
1748 (f32 (fadd (fmul f32:$src0, f32:$src1), f32:$src2)),
1749 (V_MAD_F32 $src0, $src1, $src2)
1752 /********** ======================= **********/
1753 /********** Load/Store Patterns **********/
1754 /********** ======================= **********/
1756 class DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat <
1758 (vt (inst 0, $src0, $src0, $src0, 0, 0))
1761 def : DSReadPat <DS_READ_I8, i32, sextloadi8_local>;
1762 def : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>;
1763 def : DSReadPat <DS_READ_I16, i32, sextloadi16_local>;
1764 def : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>;
1765 def : DSReadPat <DS_READ_B32, i32, local_load>;
1767 (local_load i32:$src0),
1768 (i32 (DS_READ_B32 0, $src0, $src0, $src0, 0, 0))
1771 class DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat <
1772 (frag i32:$src1, i32:$src0),
1773 (inst 0, $src0, $src1, $src1, 0, 0)
1776 def : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>;
1777 def : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>;
1778 def : DSWritePat <DS_WRITE_B32, i32, local_store>;
1780 def : Pat <(atomic_load_add_local i32:$ptr, i32:$val),
1781 (DS_ADD_U32_RTN 0, $ptr, $val, 0, 0)>;
1783 def : Pat <(atomic_load_sub_local i32:$ptr, i32:$val),
1784 (DS_SUB_U32_RTN 0, $ptr, $val, 0, 0)>;
1786 /********** ================== **********/
1787 /********** SMRD Patterns **********/
1788 /********** ================== **********/
1790 multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
1792 // 1. Offset as 8bit DWORD immediate
1794 (constant_load (SIadd64bit32bit i64:$sbase, IMM8bitDWORD:$offset)),
1795 (vt (Instr_IMM $sbase, IMM8bitDWORD:$offset))
1798 // 2. Offset loaded in an 32bit SGPR
1800 (constant_load (SIadd64bit32bit i64:$sbase, imm:$offset)),
1801 (vt (Instr_SGPR $sbase, (S_MOV_B32 imm:$offset)))
1804 // 3. No offset at all
1806 (constant_load i64:$sbase),
1807 (vt (Instr_IMM $sbase, 0))
1811 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>;
1812 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
1813 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, i64>;
1814 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>;
1815 defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, i128>;
1816 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
1818 //===----------------------------------------------------------------------===//
1820 //===----------------------------------------------------------------------===//
1822 multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
1823 PatFrag global_ld, PatFrag constant_ld> {
1825 (vt (global_ld (add i64:$ptr, (i64 IMM12bit:$offset)))),
1826 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset))
1830 (vt (global_ld i64:$ptr)),
1831 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, 0)
1835 (vt (global_ld (add i64:$ptr, i64:$offset))),
1836 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0)
1840 (vt (constant_ld (add i64:$ptr, i64:$offset))),
1841 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0)
1845 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32,
1846 sextloadi8_global, sextloadi8_constant>;
1847 defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32,
1848 az_extloadi8_global, az_extloadi8_constant>;
1849 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32,
1850 sextloadi16_global, sextloadi16_constant>;
1851 defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32,
1852 az_extloadi16_global, az_extloadi16_constant>;
1853 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32,
1854 global_load, constant_load>;
1855 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64,
1856 global_load, constant_load>;
1857 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64,
1858 az_extloadi32_global, az_extloadi32_constant>;
1859 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32,
1860 global_load, constant_load>;
1861 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32,
1862 global_load, constant_load>;
1864 multiclass MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> {
1867 (st vt:$value, i64:$ptr),
1868 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, 0)
1872 (st vt:$value, (add i64:$ptr, i64:$offset)),
1873 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, 0)
1877 defm : MUBUFStore_Pattern <BUFFER_STORE_BYTE, i32, truncstorei8_global>;
1878 defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT, i32, truncstorei16_global>;
1879 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORD, i32, global_store>;
1880 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, i64, global_store>;
1881 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, v2i32, global_store>;
1882 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4, v4i32, global_store>;
1884 /********** ====================== **********/
1885 /********** Indirect adressing **********/
1886 /********** ====================== **********/
1888 multiclass SI_INDIRECT_Pattern <ValueType vt, SI_INDIRECT_DST IndDst> {
1890 // 1. Extract with offset
1892 (vector_extract vt:$vec, (add i32:$idx, imm:$off)),
1893 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off))
1896 // 2. Extract without offset
1898 (vector_extract vt:$vec, i32:$idx),
1899 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0))
1902 // 3. Insert with offset
1904 (vector_insert vt:$vec, f32:$val, (add i32:$idx, imm:$off)),
1905 (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val)
1908 // 4. Insert without offset
1910 (vector_insert vt:$vec, f32:$val, i32:$idx),
1911 (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val)
1915 defm : SI_INDIRECT_Pattern <v2f32, SI_INDIRECT_DST_V2>;
1916 defm : SI_INDIRECT_Pattern <v4f32, SI_INDIRECT_DST_V4>;
1917 defm : SI_INDIRECT_Pattern <v8f32, SI_INDIRECT_DST_V8>;
1918 defm : SI_INDIRECT_Pattern <v16f32, SI_INDIRECT_DST_V16>;
1920 /********** =============== **********/
1921 /********** Conditions **********/
1922 /********** =============== **********/
1925 (i1 (setcc f32:$src0, f32:$src1, SETO)),
1926 (V_CMP_O_F32_e64 $src0, $src1)
1930 (i1 (setcc f32:$src0, f32:$src1, SETUO)),
1931 (V_CMP_U_F32_e64 $src0, $src1)
1934 //============================================================================//
1935 // Miscellaneous Optimization Patterns
1936 //============================================================================//
1938 def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e32>;
1940 } // End isSI predicate