1 //===-- SIInstructions.td - SI Instruction Defintions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This file was originally auto-generated from a GPU register header file and
10 // all the instruction definitions were originally commented out. Instructions
11 // that are not yet supported remain commented out.
12 //===----------------------------------------------------------------------===//
19 def INTERP : InterpSlots;
21 def InterpSlot : Operand<i32> {
22 let PrintMethod = "printInterpSlot";
25 def SendMsgImm : Operand<i32> {
26 let PrintMethod = "printSendMsg";
29 def isSI : Predicate<"Subtarget.getGeneration() "
30 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">;
32 def isCI : Predicate<"Subtarget.getGeneration() "
33 ">= AMDGPUSubtarget::SEA_ISLANDS">;
35 def isCFDepth0 : Predicate<"isCFDepth0()">;
37 def WAIT_FLAG : InstFlag<"printWaitFlag">;
39 let SubtargetPredicate = isSI in {
40 let OtherPredicates = [isCFDepth0] in {
42 //===----------------------------------------------------------------------===//
44 //===----------------------------------------------------------------------===//
48 // We are using the SGPR_32 and not the SReg_32 register class for 32-bit
49 // SMRD instructions, because the SGPR_32 register class does not include M0
50 // and writing to M0 from an SMRD instruction will hang the GPU.
51 defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SGPR_32>;
52 defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>;
53 defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>;
54 defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>;
55 defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>;
57 defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
58 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SGPR_32
61 defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
62 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64
65 defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper <
66 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128
69 defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <
70 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256
73 defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
74 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512
79 //def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>;
80 //def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>;
82 //===----------------------------------------------------------------------===//
84 //===----------------------------------------------------------------------===//
86 let neverHasSideEffects = 1 in {
88 let isMoveImm = 1 in {
89 def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>;
90 def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>;
91 def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>;
92 def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>;
93 } // End isMoveImm = 1
95 def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32",
96 [(set i32:$dst, (not i32:$src0))]
99 def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", []>;
100 def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>;
101 def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>;
102 def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>;
103 def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>;
104 } // End neverHasSideEffects = 1
106 ////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>;
107 ////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>;
108 ////def S_BCNT1_I32_B32 : SOP1_BCNT1 <0x0000000f, "S_BCNT1_I32_B32", []>;
109 ////def S_BCNT1_I32_B64 : SOP1_BCNT1 <0x00000010, "S_BCNT1_I32_B64", []>;
110 ////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>;
111 ////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>;
112 ////def S_FF1_I32_B32 : SOP1_FF1 <0x00000013, "S_FF1_I32_B32", []>;
113 ////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>;
114 //def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", []>;
115 //def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>;
116 def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>;
117 //def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>;
118 def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8",
119 [(set i32:$dst, (sext_inreg i32:$src0, i8))]
121 def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16",
122 [(set i32:$dst, (sext_inreg i32:$src0, i16))]
125 ////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>;
126 ////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>;
127 ////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>;
128 ////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>;
129 def S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>;
130 def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>;
131 def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>;
132 def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>;
134 let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in {
136 def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>;
137 def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>;
138 def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>;
139 def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>;
140 def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>;
141 def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>;
142 def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>;
143 def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>;
145 } // End hasSideEffects = 1
147 def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>;
148 def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>;
149 def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>;
150 def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>;
151 def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>;
152 def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>;
153 //def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>;
154 def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>;
155 def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>;
156 def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>;
158 //===----------------------------------------------------------------------===//
160 //===----------------------------------------------------------------------===//
162 let Defs = [SCC] in { // Carry out goes to SCC
163 let isCommutable = 1 in {
164 def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>;
165 def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32",
166 [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))]
168 } // End isCommutable = 1
170 def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>;
171 def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32",
172 [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))]
175 let Uses = [SCC] in { // Carry in comes from SCC
176 let isCommutable = 1 in {
177 def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32",
178 [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
179 } // End isCommutable = 1
181 def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32",
182 [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
183 } // End Uses = [SCC]
184 } // End Defs = [SCC]
186 def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32",
187 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]
189 def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32",
190 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]
192 def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32",
193 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]
195 def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32",
196 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]
199 def S_CSELECT_B32 : SOP2 <
200 0x0000000a, (outs SReg_32:$dst),
201 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32",
205 def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>;
207 def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32",
208 [(set i32:$dst, (and i32:$src0, i32:$src1))]
211 def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64",
212 [(set i64:$dst, (and i64:$src0, i64:$src1))]
215 def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32",
216 [(set i32:$dst, (or i32:$src0, i32:$src1))]
219 def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64",
220 [(set i64:$dst, (or i64:$src0, i64:$src1))]
223 def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32",
224 [(set i32:$dst, (xor i32:$src0, i32:$src1))]
227 def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64",
228 [(set i64:$dst, (xor i64:$src0, i64:$src1))]
230 def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>;
231 def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>;
232 def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>;
233 def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>;
234 def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>;
235 def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>;
236 def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>;
237 def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>;
238 def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>;
239 def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>;
241 // Use added complexity so these patterns are preferred to the VALU patterns.
242 let AddedComplexity = 1 in {
244 def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32",
245 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
247 def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "S_LSHL_B64",
248 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
250 def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32",
251 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
253 def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "S_LSHR_B64",
254 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
256 def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32",
257 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
259 def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64",
260 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
263 } // End AddedComplexity = 1
265 def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>;
266 def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>;
267 def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>;
268 def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>;
269 def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>;
270 def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>;
271 def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>;
272 //def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>;
273 def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>;
275 //===----------------------------------------------------------------------===//
277 //===----------------------------------------------------------------------===//
279 def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32">;
280 def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32">;
281 def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32">;
282 def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32">;
283 def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32">;
284 def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32">;
285 def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32">;
286 def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32">;
287 def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32">;
288 def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32">;
289 def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32">;
290 def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32">;
291 ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>;
292 ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>;
293 ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>;
294 ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>;
295 //def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>;
297 //===----------------------------------------------------------------------===//
299 //===----------------------------------------------------------------------===//
301 def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>;
302 def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>;
305 This instruction is disabled for now until we can figure out how to teach
306 the instruction selector to correctly use the S_CMP* vs V_CMP*
309 When this instruction is enabled the code generator sometimes produces this
312 SCC = S_CMPK_EQ_I32 SGPR0, imm
314 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
316 def S_CMPK_EQ_I32 : SOPK <
317 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1),
319 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))]
323 let isCompare = 1 in {
324 def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>;
325 def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>;
326 def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>;
327 def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>;
328 def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>;
329 def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>;
330 def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>;
331 def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>;
332 def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>;
333 def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>;
334 def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>;
335 } // End isCompare = 1
337 let Defs = [SCC], isCommutable = 1 in {
338 def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>;
339 def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>;
342 //def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>;
343 def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>;
344 def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>;
345 def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>;
346 //def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>;
347 //def EXP : EXP_ <0x00000000, "EXP", []>;
349 } // End let OtherPredicates = [isCFDepth0]
351 //===----------------------------------------------------------------------===//
353 //===----------------------------------------------------------------------===//
355 def S_NOP : SOPP <0x00000000, (ins i16imm:$SIMM16), "S_NOP $SIMM16", []>;
357 let isTerminator = 1 in {
359 def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM",
366 let isBranch = 1 in {
367 def S_BRANCH : SOPP <
368 0x00000002, (ins brtarget:$target), "S_BRANCH $target",
373 let DisableEncoding = "$scc" in {
374 def S_CBRANCH_SCC0 : SOPP <
375 0x00000004, (ins brtarget:$target, SCCReg:$scc),
376 "S_CBRANCH_SCC0 $target", []
378 def S_CBRANCH_SCC1 : SOPP <
379 0x00000005, (ins brtarget:$target, SCCReg:$scc),
380 "S_CBRANCH_SCC1 $target",
383 } // End DisableEncoding = "$scc"
385 def S_CBRANCH_VCCZ : SOPP <
386 0x00000006, (ins brtarget:$target, VCCReg:$vcc),
387 "S_CBRANCH_VCCZ $target",
390 def S_CBRANCH_VCCNZ : SOPP <
391 0x00000007, (ins brtarget:$target, VCCReg:$vcc),
392 "S_CBRANCH_VCCNZ $target",
396 let DisableEncoding = "$exec" in {
397 def S_CBRANCH_EXECZ : SOPP <
398 0x00000008, (ins brtarget:$target, EXECReg:$exec),
399 "S_CBRANCH_EXECZ $target",
402 def S_CBRANCH_EXECNZ : SOPP <
403 0x00000009, (ins brtarget:$target, EXECReg:$exec),
404 "S_CBRANCH_EXECNZ $target",
407 } // End DisableEncoding = "$exec"
410 } // End isBranch = 1
411 } // End isTerminator = 1
413 let hasSideEffects = 1 in {
414 def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER",
415 [(int_AMDGPU_barrier_local)]
424 def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16",
427 //def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>;
428 //def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>;
429 //def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>;
431 let Uses = [EXEC] in {
432 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "S_SENDMSG $simm16",
433 [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)]
435 let DisableEncoding = "$m0";
437 } // End Uses = [EXEC]
439 //def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>;
440 //def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>;
441 //def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>;
442 //def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>;
443 //def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>;
444 //def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
445 } // End hasSideEffects
447 //===----------------------------------------------------------------------===//
449 //===----------------------------------------------------------------------===//
451 let isCompare = 1 in {
453 defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">;
454 defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_OLT>;
455 defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", f32, COND_OEQ>;
456 defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", f32, COND_OLE>;
457 defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", f32, COND_OGT>;
458 defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32">;
459 defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", f32, COND_OGE>;
460 defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32", f32, COND_O>;
461 defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32", f32, COND_UO>;
462 defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32">;
463 defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32">;
464 defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32">;
465 defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32">;
466 defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", f32, COND_UNE>;
467 defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">;
468 defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">;
470 let hasSideEffects = 1, Defs = [EXEC] in {
472 defm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32">;
473 defm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32">;
474 defm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32">;
475 defm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32">;
476 defm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32">;
477 defm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32">;
478 defm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32">;
479 defm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32">;
480 defm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32">;
481 defm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32">;
482 defm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32">;
483 defm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32">;
484 defm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32">;
485 defm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32">;
486 defm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32">;
487 defm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32">;
489 } // End hasSideEffects = 1, Defs = [EXEC]
491 defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">;
492 defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64", f64, COND_OLT>;
493 defm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64", f64, COND_OEQ>;
494 defm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64", f64, COND_OLE>;
495 defm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64", f64, COND_OGT>;
496 defm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64">;
497 defm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64", f64, COND_OGE>;
498 defm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64", f64, COND_O>;
499 defm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64", f64, COND_UO>;
500 defm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64">;
501 defm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64">;
502 defm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64">;
503 defm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64">;
504 defm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64", f64, COND_UNE>;
505 defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">;
506 defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">;
508 let hasSideEffects = 1, Defs = [EXEC] in {
510 defm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64">;
511 defm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64">;
512 defm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64">;
513 defm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64">;
514 defm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64">;
515 defm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64">;
516 defm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64">;
517 defm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64">;
518 defm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64">;
519 defm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64">;
520 defm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64">;
521 defm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64">;
522 defm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64">;
523 defm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64">;
524 defm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64">;
525 defm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64">;
527 } // End hasSideEffects = 1, Defs = [EXEC]
529 defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">;
530 defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">;
531 defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32">;
532 defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32">;
533 defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32">;
534 defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32">;
535 defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32">;
536 defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32">;
537 defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32">;
538 defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32">;
539 defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32">;
540 defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32">;
541 defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32">;
542 defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">;
543 defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">;
544 defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">;
546 let hasSideEffects = 1, Defs = [EXEC] in {
548 defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32">;
549 defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32">;
550 defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32">;
551 defm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32">;
552 defm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32">;
553 defm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32">;
554 defm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32">;
555 defm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32">;
556 defm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32">;
557 defm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32">;
558 defm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32">;
559 defm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32">;
560 defm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32">;
561 defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32">;
562 defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32">;
563 defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32">;
565 } // End hasSideEffects = 1, Defs = [EXEC]
567 defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">;
568 defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">;
569 defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">;
570 defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64">;
571 defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64">;
572 defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64">;
573 defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64">;
574 defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64">;
575 defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64">;
576 defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64">;
577 defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64">;
578 defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64">;
579 defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64">;
580 defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">;
581 defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">;
582 defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">;
584 let hasSideEffects = 1, Defs = [EXEC] in {
586 defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">;
587 defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">;
588 defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">;
589 defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64">;
590 defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64">;
591 defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64">;
592 defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64">;
593 defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64">;
594 defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64">;
595 defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64">;
596 defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64">;
597 defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64">;
598 defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64">;
599 defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">;
600 defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">;
601 defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">;
603 } // End hasSideEffects = 1, Defs = [EXEC]
605 defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">;
606 defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_SLT>;
607 defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>;
608 defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", i32, COND_SLE>;
609 defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", i32, COND_SGT>;
610 defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", i32, COND_NE>;
611 defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_SGE>;
612 defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">;
614 let hasSideEffects = 1, Defs = [EXEC] in {
616 defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32">;
617 defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32">;
618 defm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32">;
619 defm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32">;
620 defm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32">;
621 defm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32">;
622 defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32">;
623 defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32">;
625 } // End hasSideEffects = 1, Defs = [EXEC]
627 defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">;
628 defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64", i64, COND_SLT>;
629 defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64", i64, COND_EQ>;
630 defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64", i64, COND_SLE>;
631 defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64", i64, COND_SGT>;
632 defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64", i64, COND_NE>;
633 defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64", i64, COND_SGE>;
634 defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">;
636 let hasSideEffects = 1, Defs = [EXEC] in {
638 defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64">;
639 defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64">;
640 defm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64">;
641 defm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64">;
642 defm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64">;
643 defm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64">;
644 defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64">;
645 defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64">;
647 } // End hasSideEffects = 1, Defs = [EXEC]
649 defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">;
650 defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32", i32, COND_ULT>;
651 defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32", i32, COND_EQ>;
652 defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32", i32, COND_ULE>;
653 defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32", i32, COND_UGT>;
654 defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32", i32, COND_NE>;
655 defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32", i32, COND_UGE>;
656 defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">;
658 let hasSideEffects = 1, Defs = [EXEC] in {
660 defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32">;
661 defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32">;
662 defm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32">;
663 defm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32">;
664 defm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32">;
665 defm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32">;
666 defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32">;
667 defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32">;
669 } // End hasSideEffects = 1, Defs = [EXEC]
671 defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">;
672 defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64", i64, COND_ULT>;
673 defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64", i64, COND_EQ>;
674 defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64", i64, COND_ULE>;
675 defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64", i64, COND_UGT>;
676 defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64", i64, COND_NE>;
677 defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64", i64, COND_UGE>;
678 defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">;
680 let hasSideEffects = 1, Defs = [EXEC] in {
682 defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64">;
683 defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64">;
684 defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64">;
685 defm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64">;
686 defm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64">;
687 defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64">;
688 defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64">;
689 defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64">;
691 } // End hasSideEffects = 1, Defs = [EXEC]
693 defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">;
695 let hasSideEffects = 1, Defs = [EXEC] in {
696 defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">;
697 } // End hasSideEffects = 1, Defs = [EXEC]
699 defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">;
701 let hasSideEffects = 1, Defs = [EXEC] in {
702 defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">;
703 } // End hasSideEffects = 1, Defs = [EXEC]
705 } // End isCompare = 1
707 //===----------------------------------------------------------------------===//
709 //===----------------------------------------------------------------------===//
711 def DS_ADD_U32_RTN : DS_1A1D_RET <0x20, "DS_ADD_U32_RTN", VReg_32>;
712 def DS_SUB_U32_RTN : DS_1A1D_RET <0x21, "DS_SUB_U32_RTN", VReg_32>;
713 def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>;
714 def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "DS_WRITE_B8", VReg_32>;
715 def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "DS_WRITE_B16", VReg_32>;
716 def DS_WRITE_B64 : DS_Store_Helper <0x00000004d, "DS_WRITE_B64", VReg_64>;
718 def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>;
719 def DS_READ_I8 : DS_Load_Helper <0x00000039, "DS_READ_I8", VReg_32>;
720 def DS_READ_U8 : DS_Load_Helper <0x0000003a, "DS_READ_U8", VReg_32>;
721 def DS_READ_I16 : DS_Load_Helper <0x0000003b, "DS_READ_I16", VReg_32>;
722 def DS_READ_U16 : DS_Load_Helper <0x0000003c, "DS_READ_U16", VReg_32>;
723 def DS_READ_B64 : DS_Load_Helper <0x00000076, "DS_READ_B64", VReg_64>;
726 def DS_WRITE2_B32 : DS_Load2_Helper <0x0000000E, "DS_WRITE2_B32", VReg_64>;
727 def DS_WRITE2_B64 : DS_Load2_Helper <0x0000004E, "DS_WRITE2_B64", VReg_128>;
729 def DS_READ2_B32 : DS_Load2_Helper <0x00000037, "DS_READ2_B32", VReg_64>;
730 def DS_READ2_B64 : DS_Load2_Helper <0x00000075, "DS_READ2_B64", VReg_128>;
732 // TODO: DS_READ2ST64_B32, DS_READ2ST64_B64,
733 // DS_WRITE2ST64_B32, DS_WRITE2ST64_B64
735 //===----------------------------------------------------------------------===//
736 // MUBUF Instructions
737 //===----------------------------------------------------------------------===//
739 //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>;
740 //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>;
741 //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>;
742 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>;
743 //def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>;
744 //def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>;
745 //def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>;
746 //def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>;
747 defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <0x00000008, "BUFFER_LOAD_UBYTE", VReg_32>;
748 defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <0x00000009, "BUFFER_LOAD_SBYTE", VReg_32>;
749 defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <0x0000000a, "BUFFER_LOAD_USHORT", VReg_32>;
750 defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32>;
751 defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <0x0000000c, "BUFFER_LOAD_DWORD", VReg_32>;
752 defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64>;
753 defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128>;
755 def BUFFER_STORE_BYTE : MUBUF_Store_Helper <
756 0x00000018, "BUFFER_STORE_BYTE", VReg_32
759 def BUFFER_STORE_SHORT : MUBUF_Store_Helper <
760 0x0000001a, "BUFFER_STORE_SHORT", VReg_32
763 def BUFFER_STORE_DWORD : MUBUF_Store_Helper <
764 0x0000001c, "BUFFER_STORE_DWORD", VReg_32
767 def BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper <
768 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64
771 def BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper <
772 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128
774 //def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>;
775 //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>;
776 //def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>;
777 //def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>;
778 //def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>;
779 //def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>;
780 //def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>;
781 //def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>;
782 //def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>;
783 //def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>;
784 //def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>;
785 //def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>;
786 //def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>;
787 //def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>;
788 //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>;
789 //def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>;
790 //def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>;
791 //def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>;
792 //def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>;
793 //def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>;
794 //def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>;
795 //def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>;
796 //def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>;
797 //def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>;
798 //def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>;
799 //def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>;
800 //def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>;
801 //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>;
802 //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>;
803 //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>;
804 //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>;
805 //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>;
806 //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>;
807 //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>;
808 //def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>;
809 //def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>;
811 //===----------------------------------------------------------------------===//
812 // MTBUF Instructions
813 //===----------------------------------------------------------------------===//
815 //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>;
816 //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>;
817 //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>;
818 def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>;
819 def TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "TBUFFER_STORE_FORMAT_X", VReg_32>;
820 def TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FORMAT_XY", VReg_64>;
821 def TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>;
822 def TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>;
824 //===----------------------------------------------------------------------===//
826 //===----------------------------------------------------------------------===//
828 defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "IMAGE_LOAD">;
829 defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "IMAGE_LOAD_MIP">;
830 //def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>;
831 //def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>;
832 //def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>;
833 //def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>;
834 //def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>;
835 //def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>;
836 //def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>;
837 //def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>;
838 defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "IMAGE_GET_RESINFO">;
839 //def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>;
840 //def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>;
841 //def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>;
842 //def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>;
843 //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>;
844 //def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>;
845 //def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>;
846 //def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>;
847 //def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>;
848 //def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>;
849 //def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>;
850 //def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>;
851 //def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>;
852 //def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>;
853 //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>;
854 //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>;
855 //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>;
856 defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">;
857 //def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>;
858 defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">;
859 //def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>;
860 defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">;
861 defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">;
862 //def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>;
863 //def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>;
864 defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">;
865 //def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>;
866 defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">;
867 //def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>;
868 defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">;
869 defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">;
870 //def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>;
871 //def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>;
872 //def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>;
873 //def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>;
874 //def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>;
875 //def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>;
876 //def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>;
877 //def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>;
878 //def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>;
879 //def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>;
880 //def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>;
881 //def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>;
882 //def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>;
883 //def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>;
884 //def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>;
885 //def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>;
886 //def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>;
887 //def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>;
888 //def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>;
889 //def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>;
890 //def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>;
891 //def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>;
892 //def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>;
893 //def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>;
894 //def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>;
895 //def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>;
896 //def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>;
897 //def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>;
898 //def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>;
899 //def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>;
900 //def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>;
901 //def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>;
902 //def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>;
903 //def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>;
904 //def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>;
905 //def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>;
906 //def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>;
907 //def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>;
908 //def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>;
909 //def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>;
910 //def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>;
911 //def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>;
912 //def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>;
913 //def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>;
914 //def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>;
915 //def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>;
916 //def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>;
917 //def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>;
918 //def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>;
919 //def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>;
920 //def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>;
921 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>;
922 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>;
924 //===----------------------------------------------------------------------===//
926 //===----------------------------------------------------------------------===//
928 //def V_NOP : VOP1_ <0x00000000, "V_NOP", []>;
930 let neverHasSideEffects = 1, isMoveImm = 1 in {
931 defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>;
932 } // End neverHasSideEffects = 1, isMoveImm = 1
934 let Uses = [EXEC] in {
936 def V_READFIRSTLANE_B32 : VOP1 <
938 (outs SReg_32:$vdst),
940 "V_READFIRSTLANE_B32 $vdst, $src0",
946 defm V_CVT_I32_F64 : VOP1_32_64 <0x00000003, "V_CVT_I32_F64",
947 [(set i32:$dst, (fp_to_sint f64:$src0))]
949 defm V_CVT_F64_I32 : VOP1_64_32 <0x00000004, "V_CVT_F64_I32",
950 [(set f64:$dst, (sint_to_fp i32:$src0))]
952 defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32",
953 [(set f32:$dst, (sint_to_fp i32:$src0))]
955 defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32",
956 [(set f32:$dst, (uint_to_fp i32:$src0))]
958 defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32",
959 [(set i32:$dst, (fp_to_uint f32:$src0))]
961 defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32",
962 [(set i32:$dst, (fp_to_sint f32:$src0))]
964 defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>;
965 ////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>;
966 //defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>;
967 //defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>;
968 //defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>;
969 //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>;
970 defm V_CVT_F32_F64 : VOP1_32_64 <0x0000000f, "V_CVT_F32_F64",
971 [(set f32:$dst, (fround f64:$src0))]
973 defm V_CVT_F64_F32 : VOP1_64_32 <0x00000010, "V_CVT_F64_F32",
974 [(set f64:$dst, (fextend f32:$src0))]
976 //defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0", []>;
977 //defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1", []>;
978 //defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2", []>;
979 //defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", []>;
980 defm V_CVT_U32_F64 : VOP1_32_64 <0x00000015, "V_CVT_U32_F64",
981 [(set i32:$dst, (fp_to_uint f64:$src0))]
983 defm V_CVT_F64_U32 : VOP1_64_32 <0x00000016, "V_CVT_F64_U32",
984 [(set f64:$dst, (uint_to_fp i32:$src0))]
987 defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32",
988 [(set f32:$dst, (AMDGPUfract f32:$src0))]
990 defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32",
991 [(set f32:$dst, (int_AMDGPU_trunc f32:$src0))]
993 defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32",
994 [(set f32:$dst, (fceil f32:$src0))]
996 defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32",
997 [(set f32:$dst, (frint f32:$src0))]
999 defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32",
1000 [(set f32:$dst, (ffloor f32:$src0))]
1002 defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32",
1003 [(set f32:$dst, (fexp2 f32:$src0))]
1005 defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>;
1006 defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32",
1007 [(set f32:$dst, (flog2 f32:$src0))]
1009 defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>;
1010 defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>;
1011 defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32",
1012 [(set f32:$dst, (fdiv FP_ONE, f32:$src0))]
1014 defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>;
1015 defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>;
1016 defm V_RSQ_LEGACY_F32 : VOP1_32 <
1017 0x0000002d, "V_RSQ_LEGACY_F32",
1018 [(set f32:$dst, (int_AMDGPU_rsq f32:$src0))]
1020 defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32",
1021 [(set f32:$dst, (fdiv FP_ONE, (fsqrt f32:$src0)))]
1023 defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64",
1024 [(set f64:$dst, (fdiv FP_ONE, f64:$src0))]
1026 defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>;
1027 defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64",
1028 [(set f64:$dst, (fdiv FP_ONE, (fsqrt f64:$src0)))]
1030 defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>;
1031 defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32",
1032 [(set f32:$dst, (fsqrt f32:$src0))]
1034 defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64",
1035 [(set f64:$dst, (fsqrt f64:$src0))]
1037 defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>;
1038 defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>;
1039 defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>;
1040 defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>;
1041 defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>;
1042 defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>;
1043 defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>;
1044 //defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>;
1045 defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>;
1046 defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>;
1047 //defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>;
1048 defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>;
1049 //def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>;
1050 defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>;
1051 defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>;
1052 defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>;
1055 //===----------------------------------------------------------------------===//
1056 // VINTRP Instructions
1057 //===----------------------------------------------------------------------===//
1059 def V_INTERP_P1_F32 : VINTRP <
1061 (outs VReg_32:$dst),
1062 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1063 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]",
1065 let DisableEncoding = "$m0";
1068 def V_INTERP_P2_F32 : VINTRP <
1070 (outs VReg_32:$dst),
1071 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1072 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]",
1075 let Constraints = "$src0 = $dst";
1076 let DisableEncoding = "$src0,$m0";
1080 def V_INTERP_MOV_F32 : VINTRP <
1082 (outs VReg_32:$dst),
1083 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1084 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]",
1086 let DisableEncoding = "$m0";
1089 //===----------------------------------------------------------------------===//
1090 // VOP2 Instructions
1091 //===----------------------------------------------------------------------===//
1093 def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
1094 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc),
1095 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]",
1098 let DisableEncoding = "$vcc";
1101 def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst),
1102 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2,
1103 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
1104 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg",
1105 [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))]
1107 let src0_modifiers = 0;
1108 let src1_modifiers = 0;
1109 let src2_modifiers = 0;
1112 def V_READLANE_B32 : VOP2 <
1114 (outs SReg_32:$vdst),
1115 (ins VReg_32:$src0, SSrc_32:$vsrc1),
1116 "V_READLANE_B32 $vdst, $src0, $vsrc1",
1120 def V_WRITELANE_B32 : VOP2 <
1122 (outs VReg_32:$vdst),
1123 (ins SReg_32:$src0, SSrc_32:$vsrc1),
1124 "V_WRITELANE_B32 $vdst, $src0, $vsrc1",
1128 let isCommutable = 1 in {
1129 defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32",
1130 [(set f32:$dst, (fadd f32:$src0, f32:$src1))]
1133 defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32",
1134 [(set f32:$dst, (fsub f32:$src0, f32:$src1))]
1136 defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", [], "V_SUB_F32">;
1137 } // End isCommutable = 1
1139 defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>;
1141 let isCommutable = 1 in {
1143 defm V_MUL_LEGACY_F32 : VOP2_32 <
1144 0x00000007, "V_MUL_LEGACY_F32",
1145 [(set f32:$dst, (int_AMDGPU_mul f32:$src0, f32:$src1))]
1148 defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32",
1149 [(set f32:$dst, (fmul f32:$src0, f32:$src1))]
1153 defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24",
1154 [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))]
1156 //defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>;
1157 defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24",
1158 [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))]
1160 //defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>;
1163 defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32",
1164 [(set f32:$dst, (AMDGPUfmin f32:$src0, f32:$src1))]
1167 defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32",
1168 [(set f32:$dst, (AMDGPUfmax f32:$src0, f32:$src1))]
1171 defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>;
1172 defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>;
1173 defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32",
1174 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]>;
1175 defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32",
1176 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]>;
1177 defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32",
1178 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]>;
1179 defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32",
1180 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]>;
1182 defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32",
1183 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
1186 defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">;
1188 defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32",
1189 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
1191 defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">;
1193 let hasPostISelHook = 1 in {
1195 defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32",
1196 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
1200 defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">;
1202 defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32",
1203 [(set i32:$dst, (and i32:$src0, i32:$src1))]>;
1204 defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32",
1205 [(set i32:$dst, (or i32:$src0, i32:$src1))]
1207 defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32",
1208 [(set i32:$dst, (xor i32:$src0, i32:$src1))]
1211 } // End isCommutable = 1
1213 defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32",
1214 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))]>;
1215 defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>;
1216 defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>;
1217 defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>;
1218 //defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>;
1219 defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>;
1220 defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>;
1222 let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC
1223 // No patterns so that the scalar instructions are always selected.
1224 // The scalar versions will be replaced with vector when needed later.
1225 defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32",
1226 [(set i32:$dst, (add i32:$src0, i32:$src1))], VSrc_32>;
1227 defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32",
1228 [(set i32:$dst, (sub i32:$src0, i32:$src1))], VSrc_32>;
1229 defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], VSrc_32,
1232 let Uses = [VCC] in { // Carry-in comes from VCC
1233 defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32",
1234 [(set i32:$dst, (adde i32:$src0, i32:$src1))], VReg_32>;
1235 defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32",
1236 [(set i32:$dst, (sube i32:$src0, i32:$src1))], VReg_32>;
1237 defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], VReg_32,
1239 } // End Uses = [VCC]
1240 } // End isCommutable = 1, Defs = [VCC]
1242 defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>;
1243 ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>;
1244 ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>;
1245 ////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>;
1246 defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32",
1247 [(set i32:$dst, (int_SI_packf16 f32:$src0, f32:$src1))]
1249 ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>;
1250 ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>;
1252 //===----------------------------------------------------------------------===//
1253 // VOP3 Instructions
1254 //===----------------------------------------------------------------------===//
1256 let neverHasSideEffects = 1 in {
1258 defm V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>;
1259 defm V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32",
1260 [(set f32:$dst, (fadd (fmul f32:$src0, f32:$src1), f32:$src2))]
1262 defm V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24",
1263 [(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))]
1265 defm V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24",
1266 [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))]
1269 } // End neverHasSideEffects
1271 defm V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>;
1272 defm V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>;
1273 defm V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>;
1274 defm V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>;
1276 let neverHasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
1277 defm V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32",
1278 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))]>;
1279 defm V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32",
1280 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))]>;
1283 defm V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32",
1284 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))]>;
1285 defm V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32",
1286 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))]
1288 def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64",
1289 [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
1291 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>;
1292 defm V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>;
1294 defm V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>;
1295 defm V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>;
1296 ////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>;
1297 ////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>;
1298 ////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>;
1299 ////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>;
1300 ////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>;
1301 ////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>;
1302 ////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>;
1303 ////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>;
1304 ////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>;
1305 //def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>;
1306 //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>;
1307 //def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>;
1308 defm V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>;
1309 ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>;
1310 defm V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>;
1311 def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>;
1313 def V_LSHL_B64 : VOP3_64_Shift <0x00000161, "V_LSHL_B64",
1314 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
1316 def V_LSHR_B64 : VOP3_64_Shift <0x00000162, "V_LSHR_B64",
1317 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
1319 def V_ASHR_I64 : VOP3_64_Shift <0x00000163, "V_ASHR_I64",
1320 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
1323 let isCommutable = 1 in {
1325 def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>;
1326 def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>;
1327 def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>;
1328 def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>;
1330 } // isCommutable = 1
1332 def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>;
1334 let isCommutable = 1 in {
1336 defm V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>;
1337 defm V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>;
1338 defm V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>;
1339 defm V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>;
1341 } // isCommutable = 1
1343 defm V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>;
1344 def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>;
1345 defm V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>;
1346 def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>;
1347 //def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>;
1348 //def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>;
1349 //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>;
1350 def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>;
1352 //===----------------------------------------------------------------------===//
1353 // Pseudo Instructions
1354 //===----------------------------------------------------------------------===//
1356 let isCodeGenOnly = 1, isPseudo = 1 in {
1358 def V_MOV_I1 : InstSI <
1361 "", [(set i1:$dst, (imm:$src))]
1364 def V_AND_I1 : InstSI <
1365 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1366 [(set i1:$dst, (and i1:$src0, i1:$src1))]
1369 def V_OR_I1 : InstSI <
1370 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1371 [(set i1:$dst, (or i1:$src0, i1:$src1))]
1374 // SI pseudo instructions. These are used by the CFG structurizer pass
1375 // and should be lowered to ISA instructions prior to codegen.
1377 let mayLoad = 1, mayStore = 1, hasSideEffects = 1,
1378 Uses = [EXEC], Defs = [EXEC] in {
1380 let isBranch = 1, isTerminator = 1 in {
1383 (outs SReg_64:$dst),
1384 (ins SReg_64:$vcc, brtarget:$target),
1386 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))]
1389 def SI_ELSE : InstSI <
1390 (outs SReg_64:$dst),
1391 (ins SReg_64:$src, brtarget:$target),
1393 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]
1395 let Constraints = "$src = $dst";
1398 def SI_LOOP : InstSI <
1400 (ins SReg_64:$saved, brtarget:$target),
1401 "SI_LOOP $saved, $target",
1402 [(int_SI_loop i64:$saved, bb:$target)]
1405 } // end isBranch = 1, isTerminator = 1
1407 def SI_BREAK : InstSI <
1408 (outs SReg_64:$dst),
1410 "SI_ELSE $dst, $src",
1411 [(set i64:$dst, (int_SI_break i64:$src))]
1414 def SI_IF_BREAK : InstSI <
1415 (outs SReg_64:$dst),
1416 (ins SReg_64:$vcc, SReg_64:$src),
1417 "SI_IF_BREAK $dst, $vcc, $src",
1418 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))]
1421 def SI_ELSE_BREAK : InstSI <
1422 (outs SReg_64:$dst),
1423 (ins SReg_64:$src0, SReg_64:$src1),
1424 "SI_ELSE_BREAK $dst, $src0, $src1",
1425 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))]
1428 def SI_END_CF : InstSI <
1430 (ins SReg_64:$saved),
1432 [(int_SI_end_cf i64:$saved)]
1435 def SI_KILL : InstSI <
1439 [(int_AMDGPU_kill f32:$src)]
1442 } // end mayLoad = 1, mayStore = 1, hasSideEffects = 1
1443 // Uses = [EXEC], Defs = [EXEC]
1445 let Uses = [EXEC], Defs = [EXEC,VCC,M0] in {
1447 //defm SI_ : RegisterLoadStore <VReg_32, FRAMEri, ADDRIndirect>;
1449 let UseNamedOperandTable = 1 in {
1451 def SI_RegisterLoad : InstSI <
1452 (outs VReg_32:$dst, SReg_64:$temp),
1453 (ins FRAMEri32:$addr, i32imm:$chan),
1456 let isRegisterLoad = 1;
1460 class SIRegStore<dag outs> : InstSI <
1462 (ins VReg_32:$val, FRAMEri32:$addr, i32imm:$chan),
1465 let isRegisterStore = 1;
1469 let usesCustomInserter = 1 in {
1470 def SI_RegisterStorePseudo : SIRegStore<(outs)>;
1471 } // End usesCustomInserter = 1
1472 def SI_RegisterStore : SIRegStore<(outs SReg_64:$temp)>;
1475 } // End UseNamedOperandTable = 1
1477 def SI_INDIRECT_SRC : InstSI <
1478 (outs VReg_32:$dst, SReg_64:$temp),
1479 (ins unknown:$src, VSrc_32:$idx, i32imm:$off),
1480 "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off",
1484 class SI_INDIRECT_DST<RegisterClass rc> : InstSI <
1485 (outs rc:$dst, SReg_64:$temp),
1486 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val),
1487 "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val",
1490 let Constraints = "$src = $dst";
1493 def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VReg_32>;
1494 def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
1495 def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
1496 def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
1497 def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
1499 } // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0]
1501 let usesCustomInserter = 1 in {
1503 // This pseudo instruction takes a pointer as input and outputs a resource
1504 // constant that can be used with the ADDR64 MUBUF instructions.
1505 def SI_ADDR64_RSRC : InstSI <
1506 (outs SReg_128:$srsrc),
1511 def V_SUB_F64 : InstSI <
1512 (outs VReg_64:$dst),
1513 (ins VReg_64:$src0, VReg_64:$src1),
1514 "V_SUB_F64 $dst, $src0, $src1",
1518 } // end usesCustomInserter
1520 multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
1522 def _SAVE : InstSI <
1523 (outs VReg_32:$dst),
1524 (ins sgpr_class:$src, i32imm:$frame_idx),
1528 def _RESTORE : InstSI <
1529 (outs sgpr_class:$dst),
1530 (ins VReg_32:$src, i32imm:$frame_idx),
1536 defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>;
1537 defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>;
1538 defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>;
1539 defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;
1541 } // end IsCodeGenOnly, isPseudo
1543 } // end SubtargetPredicate = SI
1545 let Predicates = [isSI] in {
1548 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2),
1549 (V_CNDMASK_B32_e64 $src2, $src1, (V_CMP_GT_F32_e64 0, $src0))
1554 (SI_KILL 0xbf800000)
1557 /* int_SI_vs_load_input */
1559 (SIload_input v4i32:$tlst, IMM12bit:$attr_offset, i32:$buf_idx_vgpr),
1560 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0)
1565 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
1566 f32:$src0, f32:$src1, f32:$src2, f32:$src3),
1567 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
1568 $src0, $src1, $src2, $src3)
1572 (f64 (fsub f64:$src0, f64:$src1)),
1573 (V_SUB_F64 $src0, $src1)
1576 //===----------------------------------------------------------------------===//
1578 //===----------------------------------------------------------------------===//
1580 multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
1582 // 1. Offset as 8bit DWORD immediate
1584 (constant_load (add i64:$sbase, (i64 IMM8bitDWORD:$offset))),
1585 (vt (Instr_IMM $sbase, (as_dword_i32imm $offset)))
1588 // 2. Offset loaded in an 32bit SGPR
1590 (constant_load (add i64:$sbase, (i64 IMM32bit:$offset))),
1591 (vt (Instr_SGPR $sbase, (S_MOV_B32 (i32 (as_i32imm $offset)))))
1594 // 3. No offset at all
1596 (constant_load i64:$sbase),
1597 (vt (Instr_IMM $sbase, 0))
1601 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>;
1602 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
1603 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, i64>;
1604 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>;
1605 defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>;
1606 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
1607 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>;
1608 defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
1610 // 1. Offset as 8bit DWORD immediate
1612 (SIload_constant v4i32:$sbase, IMM8bitDWORD:$offset),
1613 (S_BUFFER_LOAD_DWORD_IMM $sbase, (as_dword_i32imm $offset))
1616 // 2. Offset loaded in an 32bit SGPR
1618 (SIload_constant v4i32:$sbase, imm:$offset),
1619 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset))
1622 //===----------------------------------------------------------------------===//
1624 //===----------------------------------------------------------------------===//
1627 (i1 (xor i1:$src0, i1:$src1)),
1628 (S_XOR_B64 $src0, $src1)
1631 //===----------------------------------------------------------------------===//
1633 //===----------------------------------------------------------------------===//
1636 (or i64:$src0, i64:$src1),
1637 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1638 (V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub0),
1639 (EXTRACT_SUBREG i64:$src1, sub0)), sub0),
1640 (V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub1),
1641 (EXTRACT_SUBREG i64:$src1, sub1)), sub1)
1644 class SextInReg <ValueType vt, int ShiftAmt> : Pat <
1645 (sext_inreg i32:$src0, vt),
1646 (V_ASHRREV_I32_e32 ShiftAmt, (V_LSHLREV_B32_e32 ShiftAmt, $src0))
1649 def : SextInReg <i8, 24>;
1650 def : SextInReg <i16, 16>;
1652 /********** ======================= **********/
1653 /********** Image sampling patterns **********/
1654 /********** ======================= **********/
1656 /* SIsample for simple 1D texture lookup */
1658 (SIsample i32:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
1659 (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1662 class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1663 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
1664 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1667 class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1668 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_RECT),
1669 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1672 class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1673 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_ARRAY),
1674 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1677 class SampleShadowPattern<SDNode name, MIMG opcode,
1678 ValueType vt> : Pat <
1679 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW),
1680 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1683 class SampleShadowArrayPattern<SDNode name, MIMG opcode,
1684 ValueType vt> : Pat <
1685 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
1686 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1689 /* SIsample* for texture lookups consuming more address parameters */
1690 multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l,
1691 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b,
1692 MIMG sample_d, MIMG sample_c_d, ValueType addr_type> {
1693 def : SamplePattern <SIsample, sample, addr_type>;
1694 def : SampleRectPattern <SIsample, sample, addr_type>;
1695 def : SampleArrayPattern <SIsample, sample, addr_type>;
1696 def : SampleShadowPattern <SIsample, sample_c, addr_type>;
1697 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>;
1699 def : SamplePattern <SIsamplel, sample_l, addr_type>;
1700 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>;
1701 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>;
1702 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>;
1704 def : SamplePattern <SIsampleb, sample_b, addr_type>;
1705 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>;
1706 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>;
1707 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>;
1709 def : SamplePattern <SIsampled, sample_d, addr_type>;
1710 def : SampleArrayPattern <SIsampled, sample_d, addr_type>;
1711 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>;
1712 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>;
1715 defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2,
1716 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2,
1717 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2,
1718 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2,
1720 defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4,
1721 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4,
1722 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4,
1723 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4,
1725 defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8,
1726 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8,
1727 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8,
1728 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8,
1730 defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16,
1731 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16,
1732 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16,
1733 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16,
1736 /* int_SI_imageload for texture fetches consuming varying address parameters */
1737 class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1738 (name addr_type:$addr, v32i8:$rsrc, imm),
1739 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
1742 class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1743 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY),
1744 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
1747 class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1748 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA),
1749 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
1752 class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1753 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA),
1754 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
1757 multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> {
1758 def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>;
1759 def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>;
1762 multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> {
1763 def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>;
1764 def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>;
1767 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V2, v2i32>;
1768 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V4, v4i32>;
1770 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V2, v2i32>;
1771 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V4, v4i32>;
1773 /* Image resource information */
1775 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm),
1776 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1780 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY),
1781 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1785 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA),
1786 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1789 /********** ============================================ **********/
1790 /********** Extraction, Insertion, Building and Casting **********/
1791 /********** ============================================ **********/
1793 foreach Index = 0-2 in {
1794 def Extract_Element_v2i32_#Index : Extract_Element <
1795 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
1797 def Insert_Element_v2i32_#Index : Insert_Element <
1798 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
1801 def Extract_Element_v2f32_#Index : Extract_Element <
1802 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
1804 def Insert_Element_v2f32_#Index : Insert_Element <
1805 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
1809 foreach Index = 0-3 in {
1810 def Extract_Element_v4i32_#Index : Extract_Element <
1811 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
1813 def Insert_Element_v4i32_#Index : Insert_Element <
1814 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
1817 def Extract_Element_v4f32_#Index : Extract_Element <
1818 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
1820 def Insert_Element_v4f32_#Index : Insert_Element <
1821 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
1825 foreach Index = 0-7 in {
1826 def Extract_Element_v8i32_#Index : Extract_Element <
1827 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
1829 def Insert_Element_v8i32_#Index : Insert_Element <
1830 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
1833 def Extract_Element_v8f32_#Index : Extract_Element <
1834 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
1836 def Insert_Element_v8f32_#Index : Insert_Element <
1837 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
1841 foreach Index = 0-15 in {
1842 def Extract_Element_v16i32_#Index : Extract_Element <
1843 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
1845 def Insert_Element_v16i32_#Index : Insert_Element <
1846 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
1849 def Extract_Element_v16f32_#Index : Extract_Element <
1850 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
1852 def Insert_Element_v16f32_#Index : Insert_Element <
1853 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
1857 def : BitConvert <i32, f32, SReg_32>;
1858 def : BitConvert <i32, f32, VReg_32>;
1860 def : BitConvert <f32, i32, SReg_32>;
1861 def : BitConvert <f32, i32, VReg_32>;
1863 def : BitConvert <i64, f64, VReg_64>;
1865 def : BitConvert <f64, i64, VReg_64>;
1867 def : BitConvert <v2f32, v2i32, VReg_64>;
1868 def : BitConvert <v2i32, v2f32, VReg_64>;
1869 def : BitConvert <v2i32, i64, VReg_64>;
1870 def : BitConvert <i64, v2i32, VReg_64>;
1872 def : BitConvert <v4f32, v4i32, VReg_128>;
1873 def : BitConvert <v4i32, v4f32, VReg_128>;
1875 def : BitConvert <v8f32, v8i32, SReg_256>;
1876 def : BitConvert <v8i32, v8f32, SReg_256>;
1877 def : BitConvert <v8i32, v32i8, SReg_256>;
1878 def : BitConvert <v32i8, v8i32, SReg_256>;
1879 def : BitConvert <v8i32, v32i8, VReg_256>;
1880 def : BitConvert <v8i32, v8f32, VReg_256>;
1881 def : BitConvert <v8f32, v8i32, VReg_256>;
1882 def : BitConvert <v32i8, v8i32, VReg_256>;
1884 def : BitConvert <v16i32, v16f32, VReg_512>;
1885 def : BitConvert <v16f32, v16i32, VReg_512>;
1887 /********** =================== **********/
1888 /********** Src & Dst modifiers **********/
1889 /********** =================== **********/
1891 def FCLAMP_SI : AMDGPUShaderInst <
1892 (outs VReg_32:$dst),
1893 (ins VSrc_32:$src0),
1894 "FCLAMP_SI $dst, $src0",
1897 let usesCustomInserter = 1;
1901 (int_AMDIL_clamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)),
1902 (FCLAMP_SI f32:$src)
1905 /********** ================================ **********/
1906 /********** Floating point absolute/negative **********/
1907 /********** ================================ **********/
1909 // Manipulate the sign bit directly, as e.g. using the source negation modifier
1910 // in V_ADD_F32_e64 $src, 0, [...] does not result in -0.0 for $src == +0.0,
1911 // breaking the piglit *s-floatBitsToInt-neg* tests
1913 // TODO: Look into not implementing isFNegFree/isFAbsFree for SI, and possibly
1914 // removing these patterns
1917 (fneg (fabs f32:$src)),
1918 (V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
1921 def FABS_SI : AMDGPUShaderInst <
1922 (outs VReg_32:$dst),
1923 (ins VSrc_32:$src0),
1924 "FABS_SI $dst, $src0",
1927 let usesCustomInserter = 1;
1935 def FNEG_SI : AMDGPUShaderInst <
1936 (outs VReg_32:$dst),
1937 (ins VSrc_32:$src0),
1938 "FNEG_SI $dst, $src0",
1941 let usesCustomInserter = 1;
1949 /********** ================== **********/
1950 /********** Immediate Patterns **********/
1951 /********** ================== **********/
1954 (SGPRImm<(i32 imm)>:$imm),
1955 (S_MOV_B32 imm:$imm)
1959 (SGPRImm<(f32 fpimm)>:$imm),
1960 (S_MOV_B32 fpimm:$imm)
1965 (V_MOV_B32_e32 imm:$imm)
1970 (V_MOV_B32_e32 fpimm:$imm)
1974 (i64 InlineImm<i64>:$imm),
1975 (S_MOV_B64 InlineImm<i64>:$imm)
1978 /********** ===================== **********/
1979 /********** Interpolation Paterns **********/
1980 /********** ===================== **********/
1983 (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params),
1984 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, $params)
1988 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, v2i32:$ij),
1989 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0),
1990 imm:$attr_chan, imm:$attr, i32:$params),
1991 (EXTRACT_SUBREG $ij, sub1),
1992 imm:$attr_chan, imm:$attr, $params)
1995 /********** ================== **********/
1996 /********** Intrinsic Patterns **********/
1997 /********** ================== **********/
1999 /* llvm.AMDGPU.pow */
2000 def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>;
2003 (int_AMDGPU_div f32:$src0, f32:$src1),
2004 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1))
2008 (fdiv f32:$src0, f32:$src1),
2009 (V_MUL_F32_e32 $src0, (V_RCP_F32_e32 $src1))
2013 (fdiv f64:$src0, f64:$src1),
2014 (V_MUL_F64 $src0, (V_RCP_F64_e32 $src1), (i64 0))
2019 (V_COS_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
2024 (V_SIN_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
2028 (int_AMDGPU_cube v4f32:$src),
2029 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2030 (V_CUBETC_F32 (EXTRACT_SUBREG $src, sub0),
2031 (EXTRACT_SUBREG $src, sub1),
2032 (EXTRACT_SUBREG $src, sub2)),
2034 (V_CUBESC_F32 (EXTRACT_SUBREG $src, sub0),
2035 (EXTRACT_SUBREG $src, sub1),
2036 (EXTRACT_SUBREG $src, sub2)),
2038 (V_CUBEMA_F32 (EXTRACT_SUBREG $src, sub0),
2039 (EXTRACT_SUBREG $src, sub1),
2040 (EXTRACT_SUBREG $src, sub2)),
2042 (V_CUBEID_F32 (EXTRACT_SUBREG $src, sub0),
2043 (EXTRACT_SUBREG $src, sub1),
2044 (EXTRACT_SUBREG $src, sub2)),
2049 (i32 (sext i1:$src0)),
2050 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
2053 class Ext32Pat <SDNode ext> : Pat <
2054 (i32 (ext i1:$src0)),
2055 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0)
2058 def : Ext32Pat <zext>;
2059 def : Ext32Pat <anyext>;
2061 // Offset in an 32Bit VGPR
2063 (SIload_constant v4i32:$sbase, i32:$voff),
2064 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0)
2067 // The multiplication scales from [0,1] to the unsigned integer range
2069 (AMDGPUurecip i32:$src0),
2071 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1,
2072 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
2077 (V_MBCNT_HI_U32_B32_e32 0xffffffff,
2078 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0, 0, 0))
2081 //===----------------------------------------------------------------------===//
2083 //===----------------------------------------------------------------------===//
2085 def : IMad24Pat<V_MAD_I32_I24>;
2086 def : UMad24Pat<V_MAD_U32_U24>;
2089 (fadd f64:$src0, f64:$src1),
2090 (V_ADD_F64 $src0, $src1, (i64 0))
2094 (fmul f64:$src0, f64:$src1),
2095 (V_MUL_F64 $src0, $src1, (i64 0))
2099 (mul i32:$src0, i32:$src1),
2100 (V_MUL_LO_I32 $src0, $src1, (i32 0))
2104 (mulhu i32:$src0, i32:$src1),
2105 (V_MUL_HI_U32 $src0, $src1, (i32 0))
2109 (mulhs i32:$src0, i32:$src1),
2110 (V_MUL_HI_I32 $src0, $src1, (i32 0))
2113 defm : BFIPatterns <V_BFI_B32>;
2114 def : ROTRPattern <V_ALIGNBIT_B32>;
2116 /********** ======================= **********/
2117 /********** Load/Store Patterns **********/
2118 /********** ======================= **********/
2120 multiclass DSReadPat <DS inst, ValueType vt, PatFrag frag> {
2122 (vt (frag (add i32:$ptr, (i32 IMM16bit:$offset)))),
2123 (inst (i1 0), $ptr, (as_i16imm $offset))
2128 (vt (inst 0, $src0, 0))
2132 defm : DSReadPat <DS_READ_I8, i32, sextloadi8_local>;
2133 defm : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>;
2134 defm : DSReadPat <DS_READ_I16, i32, sextloadi16_local>;
2135 defm : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>;
2136 defm : DSReadPat <DS_READ_B32, i32, local_load>;
2137 defm : DSReadPat <DS_READ_B64, i64, local_load>;
2139 multiclass DSWritePat <DS inst, ValueType vt, PatFrag frag> {
2141 (frag vt:$value, (add i32:$ptr, (i32 IMM16bit:$offset))),
2142 (inst (i1 0), $ptr, $value, (as_i16imm $offset))
2146 (frag vt:$val, i32:$ptr),
2147 (inst 0, $ptr, $val, 0)
2151 defm : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>;
2152 defm : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>;
2153 defm : DSWritePat <DS_WRITE_B32, i32, local_store>;
2154 defm : DSWritePat <DS_WRITE_B64, i64, local_store>;
2156 def : Pat <(atomic_load_add_local i32:$ptr, i32:$val),
2157 (DS_ADD_U32_RTN 0, $ptr, $val, 0)>;
2159 def : Pat <(atomic_load_sub_local i32:$ptr, i32:$val),
2160 (DS_SUB_U32_RTN 0, $ptr, $val, 0)>;
2162 //===----------------------------------------------------------------------===//
2164 //===----------------------------------------------------------------------===//
2166 multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
2167 PatFrag global_ld, PatFrag constant_ld> {
2169 (vt (global_ld (mubuf_vaddr_offset i64:$ptr, i64:$offset, IMM12bit:$imm_offset))),
2170 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, (as_i16imm $imm_offset))
2174 (vt (global_ld (add i64:$ptr, (i64 IMM12bit:$offset)))),
2175 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset))
2179 (vt (global_ld i64:$ptr)),
2180 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, 0)
2184 (vt (global_ld (add i64:$ptr, i64:$offset))),
2185 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0)
2189 (vt (constant_ld (add i64:$ptr, i64:$offset))),
2190 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0)
2194 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32,
2195 sextloadi8_global, sextloadi8_constant>;
2196 defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32,
2197 az_extloadi8_global, az_extloadi8_constant>;
2198 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32,
2199 sextloadi16_global, sextloadi16_constant>;
2200 defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32,
2201 az_extloadi16_global, az_extloadi16_constant>;
2202 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32,
2203 global_load, constant_load>;
2204 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64,
2205 global_load, constant_load>;
2206 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64,
2207 az_extloadi32_global, az_extloadi32_constant>;
2208 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32,
2209 global_load, constant_load>;
2210 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32,
2211 global_load, constant_load>;
2213 multiclass MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> {
2216 (st vt:$value, (mubuf_vaddr_offset i64:$ptr, i64:$offset, IMM12bit:$imm_offset)),
2217 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, (as_i16imm $imm_offset))
2221 (st vt:$value, (add i64:$ptr, IMM12bit:$offset)),
2222 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset))
2226 (st vt:$value, i64:$ptr),
2227 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, 0)
2231 (st vt:$value, (add i64:$ptr, i64:$offset)),
2232 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, 0)
2236 defm : MUBUFStore_Pattern <BUFFER_STORE_BYTE, i32, truncstorei8_global>;
2237 defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT, i32, truncstorei16_global>;
2238 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORD, i32, global_store>;
2239 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, i64, global_store>;
2240 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, v2i32, global_store>;
2241 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4, v4i32, global_store>;
2243 // BUFFER_LOAD_DWORD*, addr64=0
2244 multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen,
2248 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2249 imm:$offset, 0, 0, imm:$glc, imm:$slc,
2251 (offset $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2252 (as_i1imm $slc), (as_i1imm $tfe))
2256 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2257 imm, 1, 0, imm:$glc, imm:$slc,
2259 (offen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
2264 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2265 imm:$offset, 0, 1, imm:$glc, imm:$slc,
2267 (idxen $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2268 (as_i1imm $slc), (as_i1imm $tfe))
2272 (vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset,
2273 imm, 1, 1, imm:$glc, imm:$slc,
2275 (bothen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
2280 defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN,
2281 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
2282 defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN,
2283 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>;
2284 defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN,
2285 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
2287 //===----------------------------------------------------------------------===//
2289 //===----------------------------------------------------------------------===//
2291 // TBUFFER_STORE_FORMAT_*, addr64=0
2292 class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat<
2293 (SItbuffer_store v4i32:$rsrc, vt:$vdata, num_channels, i32:$vaddr,
2294 i32:$soffset, imm:$inst_offset, imm:$dfmt,
2295 imm:$nfmt, imm:$offen, imm:$idxen,
2296 imm:$glc, imm:$slc, imm:$tfe),
2298 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen),
2299 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc,
2300 (as_i1imm $slc), (as_i1imm $tfe), $soffset)
2303 def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>;
2304 def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>;
2305 def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>;
2306 def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>;
2308 let Predicates = [isCI] in {
2310 // Sea island new arithmetic instructinos
2311 let neverHasSideEffects = 1 in {
2312 defm V_TRUNC_F64 : VOP1_64 <0x00000017, "V_TRUNC_F64",
2313 [(set f64:$dst, (ftrunc f64:$src0))]
2315 defm V_CEIL_F64 : VOP1_64 <0x00000018, "V_CEIL_F64",
2316 [(set f64:$dst, (fceil f64:$src0))]
2318 defm V_FLOOR_F64 : VOP1_64 <0x0000001A, "V_FLOOR_F64",
2319 [(set f64:$dst, (ffloor f64:$src0))]
2321 defm V_RNDNE_F64 : VOP1_64 <0x00000019, "V_RNDNE_F64",
2322 [(set f64:$dst, (frint f64:$src0))]
2325 defm V_QSAD_PK_U16_U8 : VOP3_32 <0x00000173, "V_QSAD_PK_U16_U8", []>;
2326 defm V_MQSAD_U16_U8 : VOP3_32 <0x000000172, "V_MQSAD_U16_U8", []>;
2327 defm V_MQSAD_U32_U8 : VOP3_32 <0x00000175, "V_MQSAD_U32_U8", []>;
2328 def V_MAD_U64_U32 : VOP3_64 <0x00000176, "V_MAD_U64_U32", []>;
2330 // XXX - Does this set VCC?
2331 def V_MAD_I64_I32 : VOP3_64 <0x00000177, "V_MAD_I64_I32", []>;
2332 } // End neverHasSideEffects = 1
2334 // Remaining instructions:
2336 // S_CBRANCH_CDBGUSER
2337 // S_CBRANCH_CDBGSYS
2338 // S_CBRANCH_CDBGSYS_OR_USER
2339 // S_CBRANCH_CDBGSYS_AND_USER
2344 // DS_GWS_SEMA_RELEASE_ALL
2346 // DS_CNDXCHG32_RTN_B64
2349 // DS_CONDXCHG32_RTN_B128
2352 // BUFFER_LOAD_DWORDX3
2353 // BUFFER_STORE_DWORDX3
2355 } // End Predicates = [isCI]
2358 /********** ====================== **********/
2359 /********** Indirect adressing **********/
2360 /********** ====================== **********/
2362 multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, SI_INDIRECT_DST IndDst> {
2364 // 1. Extract with offset
2366 (vector_extract vt:$vec, (add i32:$idx, imm:$off)),
2367 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off))
2370 // 2. Extract without offset
2372 (vector_extract vt:$vec, i32:$idx),
2373 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0))
2376 // 3. Insert with offset
2378 (vector_insert vt:$vec, eltvt:$val, (add i32:$idx, imm:$off)),
2379 (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val)
2382 // 4. Insert without offset
2384 (vector_insert vt:$vec, eltvt:$val, i32:$idx),
2385 (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val)
2389 defm : SI_INDIRECT_Pattern <v2f32, f32, SI_INDIRECT_DST_V2>;
2390 defm : SI_INDIRECT_Pattern <v4f32, f32, SI_INDIRECT_DST_V4>;
2391 defm : SI_INDIRECT_Pattern <v8f32, f32, SI_INDIRECT_DST_V8>;
2392 defm : SI_INDIRECT_Pattern <v16f32, f32, SI_INDIRECT_DST_V16>;
2394 defm : SI_INDIRECT_Pattern <v2i32, i32, SI_INDIRECT_DST_V2>;
2395 defm : SI_INDIRECT_Pattern <v4i32, i32, SI_INDIRECT_DST_V4>;
2396 defm : SI_INDIRECT_Pattern <v8i32, i32, SI_INDIRECT_DST_V8>;
2397 defm : SI_INDIRECT_Pattern <v16i32, i32, SI_INDIRECT_DST_V16>;
2399 //===----------------------------------------------------------------------===//
2400 // Conversion Patterns
2401 //===----------------------------------------------------------------------===//
2403 def : Pat<(i32 (sext_inreg i32:$src, i1)),
2404 (S_BFE_I32 i32:$src, 65536)>; // 0 | 1 << 16
2406 // TODO: Match 64-bit BFE. SI has a 64-bit BFE, but it's scalar only so it
2407 // might not be worth the effort, and will need to expand to shifts when
2408 // fixing SGPR copies.
2410 // Handle sext_inreg in i64
2412 (i64 (sext_inreg i64:$src, i1)),
2413 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2414 (S_BFE_I32 (EXTRACT_SUBREG i64:$src, sub0), 65536), sub0), // 0 | 1 << 16
2415 (S_MOV_B32 -1), sub1)
2419 (i64 (sext_inreg i64:$src, i8)),
2420 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2421 (S_SEXT_I32_I8 (EXTRACT_SUBREG i64:$src, sub0)), sub0),
2422 (S_MOV_B32 -1), sub1)
2426 (i64 (sext_inreg i64:$src, i16)),
2427 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2428 (S_SEXT_I32_I16 (EXTRACT_SUBREG i64:$src, sub0)), sub0),
2429 (S_MOV_B32 -1), sub1)
2433 (f32 (sint_to_fp i1:$src)),
2434 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_NEG_ONE, $src)
2438 (f32 (uint_to_fp i1:$src)),
2439 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_ONE, $src)
2443 (f64 (sint_to_fp i1:$src)),
2444 (V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src))
2448 (f64 (uint_to_fp i1:$src)),
2449 (V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src))
2452 //===----------------------------------------------------------------------===//
2453 // Miscellaneous Patterns
2454 //===----------------------------------------------------------------------===//
2457 (i32 (trunc i64:$a)),
2458 (EXTRACT_SUBREG $a, sub0)
2462 (i1 (trunc i32:$a)),
2463 (V_CMP_EQ_I32_e64 (V_AND_B32_e32 (i32 1), $a), 1)
2466 // V_ADD_I32_e32/S_ADD_I32 produces carry in VCC/SCC. For the vector
2467 // case, the sgpr-copies pass will fix this to use the vector version.
2469 (i32 (addc i32:$src0, i32:$src1)),
2470 (S_ADD_I32 $src0, $src1)
2473 //============================================================================//
2474 // Miscellaneous Optimization Patterns
2475 //============================================================================//
2477 def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e32>;
2479 } // End isSI predicate