1 //===-- SIInstructions.td - SI Instruction Defintions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This file was originally auto-generated from a GPU register header file and
10 // all the instruction definitions were originally commented out. Instructions
11 // that are not yet supported remain commented out.
12 //===----------------------------------------------------------------------===//
19 def INTERP : InterpSlots;
21 def InterpSlot : Operand<i32> {
22 let PrintMethod = "printInterpSlot";
25 def SendMsgImm : Operand<i32> {
26 let PrintMethod = "printSendMsg";
29 def isSI : Predicate<"Subtarget.getGeneration() "
30 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">;
32 def isCI : Predicate<"Subtarget.getGeneration() "
33 ">= AMDGPUSubtarget::SEA_ISLANDS">;
34 def HasFlatAddressSpace : Predicate<"Subtarget.hasFlatAddressSpace()">;
36 def WAIT_FLAG : InstFlag<"printWaitFlag">;
38 let SubtargetPredicate = isSI in {
40 //===----------------------------------------------------------------------===//
42 //===----------------------------------------------------------------------===//
46 //===----------------------------------------------------------------------===//
48 //===----------------------------------------------------------------------===//
52 // We are using the SGPR_32 and not the SReg_32 register class for 32-bit
53 // SMRD instructions, because the SGPR_32 register class does not include M0
54 // and writing to M0 from an SMRD instruction will hang the GPU.
55 defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SGPR_32>;
56 defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>;
57 defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>;
58 defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>;
59 defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>;
61 defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
62 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SGPR_32
65 defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
66 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64
69 defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper <
70 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128
73 defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <
74 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256
77 defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
78 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512
83 //def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>;
84 //def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>;
86 //===----------------------------------------------------------------------===//
88 //===----------------------------------------------------------------------===//
90 let isMoveImm = 1 in {
91 def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>;
92 def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>;
93 def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>;
94 def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>;
95 } // End isMoveImm = 1
97 def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32",
98 [(set i32:$dst, (not i32:$src0))]
101 def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64",
102 [(set i64:$dst, (not i64:$src0))]
104 def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>;
105 def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>;
106 def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32",
107 [(set i32:$dst, (AMDGPUbrev i32:$src0))]
109 def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>;
111 ////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>;
112 ////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>;
113 def S_BCNT1_I32_B32 : SOP1_32 <0x0000000f, "S_BCNT1_I32_B32",
114 [(set i32:$dst, (ctpop i32:$src0))]
116 def S_BCNT1_I32_B64 : SOP1_32_64 <0x00000010, "S_BCNT1_I32_B64", []>;
118 ////def S_FF0_I32_B32 : SOP1_32 <0x00000011, "S_FF0_I32_B32", []>;
119 ////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>;
120 def S_FF1_I32_B32 : SOP1_32 <0x00000013, "S_FF1_I32_B32",
121 [(set i32:$dst, (cttz_zero_undef i32:$src0))]
123 ////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>;
125 def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32",
126 [(set i32:$dst, (ctlz_zero_undef i32:$src0))]
129 //def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>;
130 def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>;
131 //def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>;
132 def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8",
133 [(set i32:$dst, (sext_inreg i32:$src0, i8))]
135 def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16",
136 [(set i32:$dst, (sext_inreg i32:$src0, i16))]
139 ////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>;
140 ////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>;
141 ////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>;
142 ////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>;
143 def S_GETPC_B64 : SOP1 <
144 0x0000001f, (outs SReg_64:$dst), (ins), "S_GETPC_B64 $dst", []
148 def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>;
149 def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>;
150 def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>;
152 let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in {
154 def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>;
155 def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>;
156 def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>;
157 def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>;
158 def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>;
159 def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>;
160 def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>;
161 def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>;
163 } // End hasSideEffects = 1
165 def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>;
166 def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>;
167 def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>;
168 def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>;
169 def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>;
170 def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>;
171 //def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>;
172 def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>;
173 def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>;
174 def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>;
176 //===----------------------------------------------------------------------===//
178 //===----------------------------------------------------------------------===//
180 let Defs = [SCC] in { // Carry out goes to SCC
181 let isCommutable = 1 in {
182 def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>;
183 def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32",
184 [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))]
186 } // End isCommutable = 1
188 def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>;
189 def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32",
190 [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))]
193 let Uses = [SCC] in { // Carry in comes from SCC
194 let isCommutable = 1 in {
195 def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32",
196 [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
197 } // End isCommutable = 1
199 def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32",
200 [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
201 } // End Uses = [SCC]
202 } // End Defs = [SCC]
204 def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32",
205 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]
207 def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32",
208 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]
210 def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32",
211 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]
213 def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32",
214 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]
217 def S_CSELECT_B32 : SOP2 <
218 0x0000000a, (outs SReg_32:$dst),
219 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32",
223 def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>;
225 def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32",
226 [(set i32:$dst, (and i32:$src0, i32:$src1))]
229 def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64",
230 [(set i64:$dst, (and i64:$src0, i64:$src1))]
233 def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32",
234 [(set i32:$dst, (or i32:$src0, i32:$src1))]
237 def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64",
238 [(set i64:$dst, (or i64:$src0, i64:$src1))]
241 def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32",
242 [(set i32:$dst, (xor i32:$src0, i32:$src1))]
245 def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64",
246 [(set i64:$dst, (xor i64:$src0, i64:$src1))]
248 def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>;
249 def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>;
250 def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>;
251 def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>;
252 def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>;
253 def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>;
254 def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>;
255 def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>;
256 def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>;
257 def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>;
259 // Use added complexity so these patterns are preferred to the VALU patterns.
260 let AddedComplexity = 1 in {
262 def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32",
263 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
265 def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "S_LSHL_B64",
266 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
268 def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32",
269 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
271 def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "S_LSHR_B64",
272 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
274 def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32",
275 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
277 def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64",
278 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
282 def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>;
283 def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>;
284 def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32",
285 [(set i32:$dst, (mul i32:$src0, i32:$src1))]
288 } // End AddedComplexity = 1
290 def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>;
291 def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>;
292 def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>;
293 def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>;
294 //def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>;
295 def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>;
297 //===----------------------------------------------------------------------===//
299 //===----------------------------------------------------------------------===//
301 def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32">;
302 def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32">;
303 def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32">;
304 def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32">;
305 def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32">;
306 def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32">;
307 def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32">;
308 def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32">;
309 def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32">;
310 def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32">;
311 def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32">;
312 def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32">;
313 ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>;
314 ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>;
315 ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>;
316 ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>;
317 //def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>;
319 //===----------------------------------------------------------------------===//
321 //===----------------------------------------------------------------------===//
323 def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>;
324 def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>;
327 This instruction is disabled for now until we can figure out how to teach
328 the instruction selector to correctly use the S_CMP* vs V_CMP*
331 When this instruction is enabled the code generator sometimes produces this
334 SCC = S_CMPK_EQ_I32 SGPR0, imm
336 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
338 def S_CMPK_EQ_I32 : SOPK <
339 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1),
341 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))]
345 let isCompare = 1, Defs = [SCC] in {
346 def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>;
347 def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>;
348 def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>;
349 def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>;
350 def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>;
351 def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>;
352 def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>;
353 def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>;
354 def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>;
355 def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>;
356 def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>;
357 } // End isCompare = 1, Defs = [SCC]
359 let Defs = [SCC], isCommutable = 1 in {
360 def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>;
361 def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>;
364 //def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>;
365 def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>;
366 def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>;
367 def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>;
368 //def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>;
369 //def EXP : EXP_ <0x00000000, "EXP", []>;
371 //===----------------------------------------------------------------------===//
373 //===----------------------------------------------------------------------===//
375 def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "S_NOP $simm16", []>;
377 let isTerminator = 1 in {
379 def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM",
386 let isBranch = 1 in {
387 def S_BRANCH : SOPP <
388 0x00000002, (ins sopp_brtarget:$simm16), "S_BRANCH $simm16",
393 let DisableEncoding = "$scc" in {
394 def S_CBRANCH_SCC0 : SOPP <
395 0x00000004, (ins sopp_brtarget:$simm16, SCCReg:$scc),
396 "S_CBRANCH_SCC0 $simm16", []
398 def S_CBRANCH_SCC1 : SOPP <
399 0x00000005, (ins sopp_brtarget:$simm16, SCCReg:$scc),
400 "S_CBRANCH_SCC1 $simm16",
403 } // End DisableEncoding = "$scc"
405 def S_CBRANCH_VCCZ : SOPP <
406 0x00000006, (ins sopp_brtarget:$simm16, VCCReg:$vcc),
407 "S_CBRANCH_VCCZ $simm16",
410 def S_CBRANCH_VCCNZ : SOPP <
411 0x00000007, (ins sopp_brtarget:$simm16, VCCReg:$vcc),
412 "S_CBRANCH_VCCNZ $simm16",
416 let DisableEncoding = "$exec" in {
417 def S_CBRANCH_EXECZ : SOPP <
418 0x00000008, (ins sopp_brtarget:$simm16, EXECReg:$exec),
419 "S_CBRANCH_EXECZ $simm16",
422 def S_CBRANCH_EXECNZ : SOPP <
423 0x00000009, (ins sopp_brtarget:$simm16, EXECReg:$exec),
424 "S_CBRANCH_EXECNZ $simm16",
427 } // End DisableEncoding = "$exec"
430 } // End isBranch = 1
431 } // End isTerminator = 1
433 let hasSideEffects = 1 in {
434 def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER",
435 [(int_AMDGPU_barrier_local)]
444 def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16",
447 //def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>;
448 //def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>;
449 //def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>;
451 let Uses = [EXEC] in {
452 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "S_SENDMSG $simm16",
453 [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)]
455 let DisableEncoding = "$m0";
457 } // End Uses = [EXEC]
459 //def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>;
460 //def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>;
461 //def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>;
462 //def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>;
463 //def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>;
464 //def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
465 } // End hasSideEffects
467 //===----------------------------------------------------------------------===//
469 //===----------------------------------------------------------------------===//
471 let isCompare = 1 in {
473 defm V_CMP_F_F32 : VOPC_F32 <vopc<0x0>, "V_CMP_F_F32">;
474 defm V_CMP_LT_F32 : VOPC_F32 <vopc<0x1>, "V_CMP_LT_F32", COND_OLT>;
475 defm V_CMP_EQ_F32 : VOPC_F32 <vopc<0x2>, "V_CMP_EQ_F32", COND_OEQ>;
476 defm V_CMP_LE_F32 : VOPC_F32 <vopc<0x3>, "V_CMP_LE_F32", COND_OLE>;
477 defm V_CMP_GT_F32 : VOPC_F32 <vopc<0x4>, "V_CMP_GT_F32", COND_OGT>;
478 defm V_CMP_LG_F32 : VOPC_F32 <vopc<0x5>, "V_CMP_LG_F32">;
479 defm V_CMP_GE_F32 : VOPC_F32 <vopc<0x6>, "V_CMP_GE_F32", COND_OGE>;
480 defm V_CMP_O_F32 : VOPC_F32 <vopc<0x7>, "V_CMP_O_F32", COND_O>;
481 defm V_CMP_U_F32 : VOPC_F32 <vopc<0x8>, "V_CMP_U_F32", COND_UO>;
482 defm V_CMP_NGE_F32 : VOPC_F32 <vopc<0x9>, "V_CMP_NGE_F32">;
483 defm V_CMP_NLG_F32 : VOPC_F32 <vopc<0xa>, "V_CMP_NLG_F32">;
484 defm V_CMP_NGT_F32 : VOPC_F32 <vopc<0xb>, "V_CMP_NGT_F32">;
485 defm V_CMP_NLE_F32 : VOPC_F32 <vopc<0xc>, "V_CMP_NLE_F32">;
486 defm V_CMP_NEQ_F32 : VOPC_F32 <vopc<0xd>, "V_CMP_NEQ_F32", COND_UNE>;
487 defm V_CMP_NLT_F32 : VOPC_F32 <vopc<0xe>, "V_CMP_NLT_F32">;
488 defm V_CMP_TRU_F32 : VOPC_F32 <vopc<0xf>, "V_CMP_TRU_F32">;
490 let hasSideEffects = 1 in {
492 defm V_CMPX_F_F32 : VOPCX_F32 <vopc<0x10>, "V_CMPX_F_F32">;
493 defm V_CMPX_LT_F32 : VOPCX_F32 <vopc<0x11>, "V_CMPX_LT_F32">;
494 defm V_CMPX_EQ_F32 : VOPCX_F32 <vopc<0x12>, "V_CMPX_EQ_F32">;
495 defm V_CMPX_LE_F32 : VOPCX_F32 <vopc<0x13>, "V_CMPX_LE_F32">;
496 defm V_CMPX_GT_F32 : VOPCX_F32 <vopc<0x14>, "V_CMPX_GT_F32">;
497 defm V_CMPX_LG_F32 : VOPCX_F32 <vopc<0x15>, "V_CMPX_LG_F32">;
498 defm V_CMPX_GE_F32 : VOPCX_F32 <vopc<0x16>, "V_CMPX_GE_F32">;
499 defm V_CMPX_O_F32 : VOPCX_F32 <vopc<0x17>, "V_CMPX_O_F32">;
500 defm V_CMPX_U_F32 : VOPCX_F32 <vopc<0x18>, "V_CMPX_U_F32">;
501 defm V_CMPX_NGE_F32 : VOPCX_F32 <vopc<0x19>, "V_CMPX_NGE_F32">;
502 defm V_CMPX_NLG_F32 : VOPCX_F32 <vopc<0x1a>, "V_CMPX_NLG_F32">;
503 defm V_CMPX_NGT_F32 : VOPCX_F32 <vopc<0x1b>, "V_CMPX_NGT_F32">;
504 defm V_CMPX_NLE_F32 : VOPCX_F32 <vopc<0x1c>, "V_CMPX_NLE_F32">;
505 defm V_CMPX_NEQ_F32 : VOPCX_F32 <vopc<0x1d>, "V_CMPX_NEQ_F32">;
506 defm V_CMPX_NLT_F32 : VOPCX_F32 <vopc<0x1e>, "V_CMPX_NLT_F32">;
507 defm V_CMPX_TRU_F32 : VOPCX_F32 <vopc<0x1f>, "V_CMPX_TRU_F32">;
509 } // End hasSideEffects = 1
511 defm V_CMP_F_F64 : VOPC_F64 <vopc<0x20>, "V_CMP_F_F64">;
512 defm V_CMP_LT_F64 : VOPC_F64 <vopc<0x21>, "V_CMP_LT_F64", COND_OLT>;
513 defm V_CMP_EQ_F64 : VOPC_F64 <vopc<0x22>, "V_CMP_EQ_F64", COND_OEQ>;
514 defm V_CMP_LE_F64 : VOPC_F64 <vopc<0x23>, "V_CMP_LE_F64", COND_OLE>;
515 defm V_CMP_GT_F64 : VOPC_F64 <vopc<0x24>, "V_CMP_GT_F64", COND_OGT>;
516 defm V_CMP_LG_F64 : VOPC_F64 <vopc<0x25>, "V_CMP_LG_F64">;
517 defm V_CMP_GE_F64 : VOPC_F64 <vopc<0x26>, "V_CMP_GE_F64", COND_OGE>;
518 defm V_CMP_O_F64 : VOPC_F64 <vopc<0x27>, "V_CMP_O_F64", COND_O>;
519 defm V_CMP_U_F64 : VOPC_F64 <vopc<0x28>, "V_CMP_U_F64", COND_UO>;
520 defm V_CMP_NGE_F64 : VOPC_F64 <vopc<0x29>, "V_CMP_NGE_F64">;
521 defm V_CMP_NLG_F64 : VOPC_F64 <vopc<0x2a>, "V_CMP_NLG_F64">;
522 defm V_CMP_NGT_F64 : VOPC_F64 <vopc<0x2b>, "V_CMP_NGT_F64">;
523 defm V_CMP_NLE_F64 : VOPC_F64 <vopc<0x2c>, "V_CMP_NLE_F64">;
524 defm V_CMP_NEQ_F64 : VOPC_F64 <vopc<0x2d>, "V_CMP_NEQ_F64", COND_UNE>;
525 defm V_CMP_NLT_F64 : VOPC_F64 <vopc<0x2e>, "V_CMP_NLT_F64">;
526 defm V_CMP_TRU_F64 : VOPC_F64 <vopc<0x2f>, "V_CMP_TRU_F64">;
528 let hasSideEffects = 1 in {
530 defm V_CMPX_F_F64 : VOPCX_F64 <vopc<0x30>, "V_CMPX_F_F64">;
531 defm V_CMPX_LT_F64 : VOPCX_F64 <vopc<0x31>, "V_CMPX_LT_F64">;
532 defm V_CMPX_EQ_F64 : VOPCX_F64 <vopc<0x32>, "V_CMPX_EQ_F64">;
533 defm V_CMPX_LE_F64 : VOPCX_F64 <vopc<0x33>, "V_CMPX_LE_F64">;
534 defm V_CMPX_GT_F64 : VOPCX_F64 <vopc<0x34>, "V_CMPX_GT_F64">;
535 defm V_CMPX_LG_F64 : VOPCX_F64 <vopc<0x35>, "V_CMPX_LG_F64">;
536 defm V_CMPX_GE_F64 : VOPCX_F64 <vopc<0x36>, "V_CMPX_GE_F64">;
537 defm V_CMPX_O_F64 : VOPCX_F64 <vopc<0x37>, "V_CMPX_O_F64">;
538 defm V_CMPX_U_F64 : VOPCX_F64 <vopc<0x38>, "V_CMPX_U_F64">;
539 defm V_CMPX_NGE_F64 : VOPCX_F64 <vopc<0x39>, "V_CMPX_NGE_F64">;
540 defm V_CMPX_NLG_F64 : VOPCX_F64 <vopc<0x3a>, "V_CMPX_NLG_F64">;
541 defm V_CMPX_NGT_F64 : VOPCX_F64 <vopc<0x3b>, "V_CMPX_NGT_F64">;
542 defm V_CMPX_NLE_F64 : VOPCX_F64 <vopc<0x3c>, "V_CMPX_NLE_F64">;
543 defm V_CMPX_NEQ_F64 : VOPCX_F64 <vopc<0x3d>, "V_CMPX_NEQ_F64">;
544 defm V_CMPX_NLT_F64 : VOPCX_F64 <vopc<0x3e>, "V_CMPX_NLT_F64">;
545 defm V_CMPX_TRU_F64 : VOPCX_F64 <vopc<0x3f>, "V_CMPX_TRU_F64">;
547 } // End hasSideEffects = 1
549 defm V_CMPS_F_F32 : VOPC_F32 <vopc<0x40>, "V_CMPS_F_F32">;
550 defm V_CMPS_LT_F32 : VOPC_F32 <vopc<0x41>, "V_CMPS_LT_F32">;
551 defm V_CMPS_EQ_F32 : VOPC_F32 <vopc<0x42>, "V_CMPS_EQ_F32">;
552 defm V_CMPS_LE_F32 : VOPC_F32 <vopc<0x43>, "V_CMPS_LE_F32">;
553 defm V_CMPS_GT_F32 : VOPC_F32 <vopc<0x44>, "V_CMPS_GT_F32">;
554 defm V_CMPS_LG_F32 : VOPC_F32 <vopc<0x45>, "V_CMPS_LG_F32">;
555 defm V_CMPS_GE_F32 : VOPC_F32 <vopc<0x46>, "V_CMPS_GE_F32">;
556 defm V_CMPS_O_F32 : VOPC_F32 <vopc<0x47>, "V_CMPS_O_F32">;
557 defm V_CMPS_U_F32 : VOPC_F32 <vopc<0x48>, "V_CMPS_U_F32">;
558 defm V_CMPS_NGE_F32 : VOPC_F32 <vopc<0x49>, "V_CMPS_NGE_F32">;
559 defm V_CMPS_NLG_F32 : VOPC_F32 <vopc<0x4a>, "V_CMPS_NLG_F32">;
560 defm V_CMPS_NGT_F32 : VOPC_F32 <vopc<0x4b>, "V_CMPS_NGT_F32">;
561 defm V_CMPS_NLE_F32 : VOPC_F32 <vopc<0x4c>, "V_CMPS_NLE_F32">;
562 defm V_CMPS_NEQ_F32 : VOPC_F32 <vopc<0x4d>, "V_CMPS_NEQ_F32">;
563 defm V_CMPS_NLT_F32 : VOPC_F32 <vopc<0x4e>, "V_CMPS_NLT_F32">;
564 defm V_CMPS_TRU_F32 : VOPC_F32 <vopc<0x4f>, "V_CMPS_TRU_F32">;
566 let hasSideEffects = 1 in {
568 defm V_CMPSX_F_F32 : VOPCX_F32 <vopc<0x50>, "V_CMPSX_F_F32">;
569 defm V_CMPSX_LT_F32 : VOPCX_F32 <vopc<0x51>, "V_CMPSX_LT_F32">;
570 defm V_CMPSX_EQ_F32 : VOPCX_F32 <vopc<0x52>, "V_CMPSX_EQ_F32">;
571 defm V_CMPSX_LE_F32 : VOPCX_F32 <vopc<0x53>, "V_CMPSX_LE_F32">;
572 defm V_CMPSX_GT_F32 : VOPCX_F32 <vopc<0x54>, "V_CMPSX_GT_F32">;
573 defm V_CMPSX_LG_F32 : VOPCX_F32 <vopc<0x55>, "V_CMPSX_LG_F32">;
574 defm V_CMPSX_GE_F32 : VOPCX_F32 <vopc<0x56>, "V_CMPSX_GE_F32">;
575 defm V_CMPSX_O_F32 : VOPCX_F32 <vopc<0x57>, "V_CMPSX_O_F32">;
576 defm V_CMPSX_U_F32 : VOPCX_F32 <vopc<0x58>, "V_CMPSX_U_F32">;
577 defm V_CMPSX_NGE_F32 : VOPCX_F32 <vopc<0x59>, "V_CMPSX_NGE_F32">;
578 defm V_CMPSX_NLG_F32 : VOPCX_F32 <vopc<0x5a>, "V_CMPSX_NLG_F32">;
579 defm V_CMPSX_NGT_F32 : VOPCX_F32 <vopc<0x5b>, "V_CMPSX_NGT_F32">;
580 defm V_CMPSX_NLE_F32 : VOPCX_F32 <vopc<0x5c>, "V_CMPSX_NLE_F32">;
581 defm V_CMPSX_NEQ_F32 : VOPCX_F32 <vopc<0x5d>, "V_CMPSX_NEQ_F32">;
582 defm V_CMPSX_NLT_F32 : VOPCX_F32 <vopc<0x5e>, "V_CMPSX_NLT_F32">;
583 defm V_CMPSX_TRU_F32 : VOPCX_F32 <vopc<0x5f>, "V_CMPSX_TRU_F32">;
585 } // End hasSideEffects = 1
587 defm V_CMPS_F_F64 : VOPC_F64 <vopc<0x60>, "V_CMPS_F_F64">;
588 defm V_CMPS_LT_F64 : VOPC_F64 <vopc<0x61>, "V_CMPS_LT_F64">;
589 defm V_CMPS_EQ_F64 : VOPC_F64 <vopc<0x62>, "V_CMPS_EQ_F64">;
590 defm V_CMPS_LE_F64 : VOPC_F64 <vopc<0x63>, "V_CMPS_LE_F64">;
591 defm V_CMPS_GT_F64 : VOPC_F64 <vopc<0x64>, "V_CMPS_GT_F64">;
592 defm V_CMPS_LG_F64 : VOPC_F64 <vopc<0x65>, "V_CMPS_LG_F64">;
593 defm V_CMPS_GE_F64 : VOPC_F64 <vopc<0x66>, "V_CMPS_GE_F64">;
594 defm V_CMPS_O_F64 : VOPC_F64 <vopc<0x67>, "V_CMPS_O_F64">;
595 defm V_CMPS_U_F64 : VOPC_F64 <vopc<0x68>, "V_CMPS_U_F64">;
596 defm V_CMPS_NGE_F64 : VOPC_F64 <vopc<0x69>, "V_CMPS_NGE_F64">;
597 defm V_CMPS_NLG_F64 : VOPC_F64 <vopc<0x6a>, "V_CMPS_NLG_F64">;
598 defm V_CMPS_NGT_F64 : VOPC_F64 <vopc<0x6b>, "V_CMPS_NGT_F64">;
599 defm V_CMPS_NLE_F64 : VOPC_F64 <vopc<0x6c>, "V_CMPS_NLE_F64">;
600 defm V_CMPS_NEQ_F64 : VOPC_F64 <vopc<0x6d>, "V_CMPS_NEQ_F64">;
601 defm V_CMPS_NLT_F64 : VOPC_F64 <vopc<0x6e>, "V_CMPS_NLT_F64">;
602 defm V_CMPS_TRU_F64 : VOPC_F64 <vopc<0x6f>, "V_CMPS_TRU_F64">;
604 let hasSideEffects = 1, Defs = [EXEC] in {
606 defm V_CMPSX_F_F64 : VOPC_F64 <vopc<0x70>, "V_CMPSX_F_F64">;
607 defm V_CMPSX_LT_F64 : VOPC_F64 <vopc<0x71>, "V_CMPSX_LT_F64">;
608 defm V_CMPSX_EQ_F64 : VOPC_F64 <vopc<0x72>, "V_CMPSX_EQ_F64">;
609 defm V_CMPSX_LE_F64 : VOPC_F64 <vopc<0x73>, "V_CMPSX_LE_F64">;
610 defm V_CMPSX_GT_F64 : VOPC_F64 <vopc<0x74>, "V_CMPSX_GT_F64">;
611 defm V_CMPSX_LG_F64 : VOPC_F64 <vopc<0x75>, "V_CMPSX_LG_F64">;
612 defm V_CMPSX_GE_F64 : VOPC_F64 <vopc<0x76>, "V_CMPSX_GE_F64">;
613 defm V_CMPSX_O_F64 : VOPC_F64 <vopc<0x77>, "V_CMPSX_O_F64">;
614 defm V_CMPSX_U_F64 : VOPC_F64 <vopc<0x78>, "V_CMPSX_U_F64">;
615 defm V_CMPSX_NGE_F64 : VOPC_F64 <vopc<0x79>, "V_CMPSX_NGE_F64">;
616 defm V_CMPSX_NLG_F64 : VOPC_F64 <vopc<0x7a>, "V_CMPSX_NLG_F64">;
617 defm V_CMPSX_NGT_F64 : VOPC_F64 <vopc<0x7b>, "V_CMPSX_NGT_F64">;
618 defm V_CMPSX_NLE_F64 : VOPC_F64 <vopc<0x7c>, "V_CMPSX_NLE_F64">;
619 defm V_CMPSX_NEQ_F64 : VOPC_F64 <vopc<0x7d>, "V_CMPSX_NEQ_F64">;
620 defm V_CMPSX_NLT_F64 : VOPC_F64 <vopc<0x7e>, "V_CMPSX_NLT_F64">;
621 defm V_CMPSX_TRU_F64 : VOPC_F64 <vopc<0x7f>, "V_CMPSX_TRU_F64">;
623 } // End hasSideEffects = 1, Defs = [EXEC]
625 defm V_CMP_F_I32 : VOPC_I32 <vopc<0x80>, "V_CMP_F_I32">;
626 defm V_CMP_LT_I32 : VOPC_I32 <vopc<0x81>, "V_CMP_LT_I32", COND_SLT>;
627 defm V_CMP_EQ_I32 : VOPC_I32 <vopc<0x82>, "V_CMP_EQ_I32", COND_EQ>;
628 defm V_CMP_LE_I32 : VOPC_I32 <vopc<0x83>, "V_CMP_LE_I32", COND_SLE>;
629 defm V_CMP_GT_I32 : VOPC_I32 <vopc<0x84>, "V_CMP_GT_I32", COND_SGT>;
630 defm V_CMP_NE_I32 : VOPC_I32 <vopc<0x85>, "V_CMP_NE_I32", COND_NE>;
631 defm V_CMP_GE_I32 : VOPC_I32 <vopc<0x86>, "V_CMP_GE_I32", COND_SGE>;
632 defm V_CMP_T_I32 : VOPC_I32 <vopc<0x87>, "V_CMP_T_I32">;
634 let hasSideEffects = 1 in {
636 defm V_CMPX_F_I32 : VOPCX_I32 <vopc<0x90>, "V_CMPX_F_I32">;
637 defm V_CMPX_LT_I32 : VOPCX_I32 <vopc<0x91>, "V_CMPX_LT_I32">;
638 defm V_CMPX_EQ_I32 : VOPCX_I32 <vopc<0x92>, "V_CMPX_EQ_I32">;
639 defm V_CMPX_LE_I32 : VOPCX_I32 <vopc<0x93>, "V_CMPX_LE_I32">;
640 defm V_CMPX_GT_I32 : VOPCX_I32 <vopc<0x94>, "V_CMPX_GT_I32">;
641 defm V_CMPX_NE_I32 : VOPCX_I32 <vopc<0x95>, "V_CMPX_NE_I32">;
642 defm V_CMPX_GE_I32 : VOPCX_I32 <vopc<0x96>, "V_CMPX_GE_I32">;
643 defm V_CMPX_T_I32 : VOPCX_I32 <vopc<0x97>, "V_CMPX_T_I32">;
645 } // End hasSideEffects = 1
647 defm V_CMP_F_I64 : VOPC_I64 <vopc<0xa0>, "V_CMP_F_I64">;
648 defm V_CMP_LT_I64 : VOPC_I64 <vopc<0xa1>, "V_CMP_LT_I64", COND_SLT>;
649 defm V_CMP_EQ_I64 : VOPC_I64 <vopc<0xa2>, "V_CMP_EQ_I64", COND_EQ>;
650 defm V_CMP_LE_I64 : VOPC_I64 <vopc<0xa3>, "V_CMP_LE_I64", COND_SLE>;
651 defm V_CMP_GT_I64 : VOPC_I64 <vopc<0xa4>, "V_CMP_GT_I64", COND_SGT>;
652 defm V_CMP_NE_I64 : VOPC_I64 <vopc<0xa5>, "V_CMP_NE_I64", COND_NE>;
653 defm V_CMP_GE_I64 : VOPC_I64 <vopc<0xa6>, "V_CMP_GE_I64", COND_SGE>;
654 defm V_CMP_T_I64 : VOPC_I64 <vopc<0xa7>, "V_CMP_T_I64">;
656 let hasSideEffects = 1 in {
658 defm V_CMPX_F_I64 : VOPCX_I64 <vopc<0xb0>, "V_CMPX_F_I64">;
659 defm V_CMPX_LT_I64 : VOPCX_I64 <vopc<0xb1>, "V_CMPX_LT_I64">;
660 defm V_CMPX_EQ_I64 : VOPCX_I64 <vopc<0xb2>, "V_CMPX_EQ_I64">;
661 defm V_CMPX_LE_I64 : VOPCX_I64 <vopc<0xb3>, "V_CMPX_LE_I64">;
662 defm V_CMPX_GT_I64 : VOPCX_I64 <vopc<0xb4>, "V_CMPX_GT_I64">;
663 defm V_CMPX_NE_I64 : VOPCX_I64 <vopc<0xb5>, "V_CMPX_NE_I64">;
664 defm V_CMPX_GE_I64 : VOPCX_I64 <vopc<0xb6>, "V_CMPX_GE_I64">;
665 defm V_CMPX_T_I64 : VOPCX_I64 <vopc<0xb7>, "V_CMPX_T_I64">;
667 } // End hasSideEffects = 1
669 defm V_CMP_F_U32 : VOPC_I32 <vopc<0xc0>, "V_CMP_F_U32">;
670 defm V_CMP_LT_U32 : VOPC_I32 <vopc<0xc1>, "V_CMP_LT_U32", COND_ULT>;
671 defm V_CMP_EQ_U32 : VOPC_I32 <vopc<0xc2>, "V_CMP_EQ_U32", COND_EQ>;
672 defm V_CMP_LE_U32 : VOPC_I32 <vopc<0xc3>, "V_CMP_LE_U32", COND_ULE>;
673 defm V_CMP_GT_U32 : VOPC_I32 <vopc<0xc4>, "V_CMP_GT_U32", COND_UGT>;
674 defm V_CMP_NE_U32 : VOPC_I32 <vopc<0xc5>, "V_CMP_NE_U32", COND_NE>;
675 defm V_CMP_GE_U32 : VOPC_I32 <vopc<0xc6>, "V_CMP_GE_U32", COND_UGE>;
676 defm V_CMP_T_U32 : VOPC_I32 <vopc<0xc7>, "V_CMP_T_U32">;
678 let hasSideEffects = 1 in {
680 defm V_CMPX_F_U32 : VOPCX_I32 <vopc<0xd0>, "V_CMPX_F_U32">;
681 defm V_CMPX_LT_U32 : VOPCX_I32 <vopc<0xd1>, "V_CMPX_LT_U32">;
682 defm V_CMPX_EQ_U32 : VOPCX_I32 <vopc<0xd2>, "V_CMPX_EQ_U32">;
683 defm V_CMPX_LE_U32 : VOPCX_I32 <vopc<0xd3>, "V_CMPX_LE_U32">;
684 defm V_CMPX_GT_U32 : VOPCX_I32 <vopc<0xd4>, "V_CMPX_GT_U32">;
685 defm V_CMPX_NE_U32 : VOPCX_I32 <vopc<0xd5>, "V_CMPX_NE_U32">;
686 defm V_CMPX_GE_U32 : VOPCX_I32 <vopc<0xd6>, "V_CMPX_GE_U32">;
687 defm V_CMPX_T_U32 : VOPCX_I32 <vopc<0xd7>, "V_CMPX_T_U32">;
689 } // End hasSideEffects = 1
691 defm V_CMP_F_U64 : VOPC_I64 <vopc<0xe0>, "V_CMP_F_U64">;
692 defm V_CMP_LT_U64 : VOPC_I64 <vopc<0xe1>, "V_CMP_LT_U64", COND_ULT>;
693 defm V_CMP_EQ_U64 : VOPC_I64 <vopc<0xe2>, "V_CMP_EQ_U64", COND_EQ>;
694 defm V_CMP_LE_U64 : VOPC_I64 <vopc<0xe3>, "V_CMP_LE_U64", COND_ULE>;
695 defm V_CMP_GT_U64 : VOPC_I64 <vopc<0xe4>, "V_CMP_GT_U64", COND_UGT>;
696 defm V_CMP_NE_U64 : VOPC_I64 <vopc<0xe5>, "V_CMP_NE_U64", COND_NE>;
697 defm V_CMP_GE_U64 : VOPC_I64 <vopc<0xe6>, "V_CMP_GE_U64", COND_UGE>;
698 defm V_CMP_T_U64 : VOPC_I64 <vopc<0xe7>, "V_CMP_T_U64">;
700 let hasSideEffects = 1 in {
702 defm V_CMPX_F_U64 : VOPCX_I64 <vopc<0xf0>, "V_CMPX_F_U64">;
703 defm V_CMPX_LT_U64 : VOPCX_I64 <vopc<0xf1>, "V_CMPX_LT_U64">;
704 defm V_CMPX_EQ_U64 : VOPCX_I64 <vopc<0xf2>, "V_CMPX_EQ_U64">;
705 defm V_CMPX_LE_U64 : VOPCX_I64 <vopc<0xf3>, "V_CMPX_LE_U64">;
706 defm V_CMPX_GT_U64 : VOPCX_I64 <vopc<0xf4>, "V_CMPX_GT_U64">;
707 defm V_CMPX_NE_U64 : VOPCX_I64 <vopc<0xf5>, "V_CMPX_NE_U64">;
708 defm V_CMPX_GE_U64 : VOPCX_I64 <vopc<0xf6>, "V_CMPX_GE_U64">;
709 defm V_CMPX_T_U64 : VOPCX_I64 <vopc<0xf7>, "V_CMPX_T_U64">;
711 } // End hasSideEffects = 1
713 defm V_CMP_CLASS_F32 : VOPC_F32 <vopc<0x88>, "V_CMP_CLASS_F32">;
715 let hasSideEffects = 1 in {
716 defm V_CMPX_CLASS_F32 : VOPCX_F32 <vopc<0x98>, "V_CMPX_CLASS_F32">;
717 } // End hasSideEffects = 1
719 defm V_CMP_CLASS_F64 : VOPC_F64 <vopc<0xa8>, "V_CMP_CLASS_F64">;
721 let hasSideEffects = 1 in {
722 defm V_CMPX_CLASS_F64 : VOPCX_F64 <vopc<0xb8>, "V_CMPX_CLASS_F64">;
723 } // End hasSideEffects = 1
725 } // End isCompare = 1
727 //===----------------------------------------------------------------------===//
729 //===----------------------------------------------------------------------===//
732 def DS_ADD_U32 : DS_1A1D_NORET <0x0, "DS_ADD_U32", VReg_32>;
733 def DS_SUB_U32 : DS_1A1D_NORET <0x1, "DS_SUB_U32", VReg_32>;
734 def DS_RSUB_U32 : DS_1A1D_NORET <0x2, "DS_RSUB_U32", VReg_32>;
735 def DS_INC_U32 : DS_1A1D_NORET <0x3, "DS_INC_U32", VReg_32>;
736 def DS_DEC_U32 : DS_1A1D_NORET <0x4, "DS_DEC_U32", VReg_32>;
737 def DS_MIN_I32 : DS_1A1D_NORET <0x5, "DS_MIN_I32", VReg_32>;
738 def DS_MAX_I32 : DS_1A1D_NORET <0x6, "DS_MAX_I32", VReg_32>;
739 def DS_MIN_U32 : DS_1A1D_NORET <0x7, "DS_MIN_U32", VReg_32>;
740 def DS_MAX_U32 : DS_1A1D_NORET <0x8, "DS_MAX_U32", VReg_32>;
741 def DS_AND_B32 : DS_1A1D_NORET <0x9, "DS_AND_B32", VReg_32>;
742 def DS_OR_B32 : DS_1A1D_NORET <0xa, "DS_OR_B32", VReg_32>;
743 def DS_XOR_B32 : DS_1A1D_NORET <0xb, "DS_XOR_B32", VReg_32>;
744 def DS_MSKOR_B32 : DS_1A1D_NORET <0xc, "DS_MSKOR_B32", VReg_32>;
745 def DS_CMPST_B32 : DS_1A2D_NORET <0x10, "DS_CMPST_B32", VReg_32>;
746 def DS_CMPST_F32 : DS_1A2D_NORET <0x11, "DS_CMPST_F32", VReg_32>;
747 def DS_MIN_F32 : DS_1A1D_NORET <0x12, "DS_MIN_F32", VReg_32>;
748 def DS_MAX_F32 : DS_1A1D_NORET <0x13, "DS_MAX_F32", VReg_32>;
750 def DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "DS_ADD_RTN_U32", VReg_32, "DS_ADD_U32">;
751 def DS_SUB_RTN_U32 : DS_1A1D_RET <0x21, "DS_SUB_RTN_U32", VReg_32, "DS_SUB_U32">;
752 def DS_RSUB_RTN_U32 : DS_1A1D_RET <0x22, "DS_RSUB_RTN_U32", VReg_32, "DS_RSUB_U32">;
753 def DS_INC_RTN_U32 : DS_1A1D_RET <0x23, "DS_INC_RTN_U32", VReg_32, "DS_INC_U32">;
754 def DS_DEC_RTN_U32 : DS_1A1D_RET <0x24, "DS_DEC_RTN_U32", VReg_32, "DS_DEC_U32">;
755 def DS_MIN_RTN_I32 : DS_1A1D_RET <0x25, "DS_MIN_RTN_I32", VReg_32, "DS_MIN_I32">;
756 def DS_MAX_RTN_I32 : DS_1A1D_RET <0x26, "DS_MAX_RTN_I32", VReg_32, "DS_MAX_I32">;
757 def DS_MIN_RTN_U32 : DS_1A1D_RET <0x27, "DS_MIN_RTN_U32", VReg_32, "DS_MIN_U32">;
758 def DS_MAX_RTN_U32 : DS_1A1D_RET <0x28, "DS_MAX_RTN_U32", VReg_32, "DS_MAX_U32">;
759 def DS_AND_RTN_B32 : DS_1A1D_RET <0x29, "DS_AND_RTN_B32", VReg_32, "DS_AND_B32">;
760 def DS_OR_RTN_B32 : DS_1A1D_RET <0x2a, "DS_OR_RTN_B32", VReg_32, "DS_OR_B32">;
761 def DS_XOR_RTN_B32 : DS_1A1D_RET <0x2b, "DS_XOR_RTN_B32", VReg_32, "DS_XOR_B32">;
762 def DS_MSKOR_RTN_B32 : DS_1A1D_RET <0x2c, "DS_MSKOR_RTN_B32", VReg_32, "DS_MSKOR_B32">;
763 def DS_WRXCHG_RTN_B32 : DS_1A1D_RET <0x2d, "DS_WRXCHG_RTN_B32", VReg_32>;
764 //def DS_WRXCHG2_RTN_B32 : DS_2A0D_RET <0x2e, "DS_WRXCHG2_RTN_B32", VReg_32, "DS_WRXCHG2_B32">;
765 //def DS_WRXCHG2ST64_RTN_B32 : DS_2A0D_RET <0x2f, "DS_WRXCHG2_RTN_B32", VReg_32, "DS_WRXCHG2ST64_B32">;
766 def DS_CMPST_RTN_B32 : DS_1A2D_RET <0x30, "DS_CMPST_RTN_B32", VReg_32, "DS_CMPST_B32">;
767 def DS_CMPST_RTN_F32 : DS_1A2D_RET <0x31, "DS_CMPST_RTN_F32", VReg_32, "DS_CMPST_F32">;
768 def DS_MIN_RTN_F32 : DS_1A1D_RET <0x32, "DS_MIN_RTN_F32", VReg_32, "DS_MIN_F32">;
769 def DS_MAX_RTN_F32 : DS_1A1D_RET <0x33, "DS_MAX_RTN_F32", VReg_32, "DS_MAX_F32">;
771 let SubtargetPredicate = isCI in {
772 def DS_WRAP_RTN_F32 : DS_1A1D_RET <0x34, "DS_WRAP_RTN_F32", VReg_32, "DS_WRAP_F32">;
776 def DS_ADD_U64 : DS_1A1D_NORET <0x40, "DS_ADD_U64", VReg_64>;
777 def DS_SUB_U64 : DS_1A1D_NORET <0x41, "DS_SUB_U64", VReg_64>;
778 def DS_RSUB_U64 : DS_1A1D_NORET <0x42, "DS_RSUB_U64", VReg_64>;
779 def DS_INC_U64 : DS_1A1D_NORET <0x43, "DS_INC_U64", VReg_64>;
780 def DS_DEC_U64 : DS_1A1D_NORET <0x44, "DS_DEC_U64", VReg_64>;
781 def DS_MIN_I64 : DS_1A1D_NORET <0x45, "DS_MIN_I64", VReg_64>;
782 def DS_MAX_I64 : DS_1A1D_NORET <0x46, "DS_MAX_I64", VReg_64>;
783 def DS_MIN_U64 : DS_1A1D_NORET <0x47, "DS_MIN_U64", VReg_64>;
784 def DS_MAX_U64 : DS_1A1D_NORET <0x48, "DS_MAX_U64", VReg_64>;
785 def DS_AND_B64 : DS_1A1D_NORET <0x49, "DS_AND_B64", VReg_64>;
786 def DS_OR_B64 : DS_1A1D_NORET <0x4a, "DS_OR_B64", VReg_64>;
787 def DS_XOR_B64 : DS_1A1D_NORET <0x4b, "DS_XOR_B64", VReg_64>;
788 def DS_MSKOR_B64 : DS_1A1D_NORET <0x4c, "DS_MSKOR_B64", VReg_64>;
789 def DS_CMPST_B64 : DS_1A2D_NORET <0x50, "DS_CMPST_B64", VReg_64>;
790 def DS_CMPST_F64 : DS_1A2D_NORET <0x51, "DS_CMPST_F64", VReg_64>;
791 def DS_MIN_F64 : DS_1A1D_NORET <0x52, "DS_MIN_F64", VReg_64>;
792 def DS_MAX_F64 : DS_1A1D_NORET <0x53, "DS_MAX_F64", VReg_64>;
794 def DS_ADD_RTN_U64 : DS_1A1D_RET <0x60, "DS_ADD_RTN_U64", VReg_64, "DS_ADD_U64">;
795 def DS_SUB_RTN_U64 : DS_1A1D_RET <0x61, "DS_SUB_RTN_U64", VReg_64, "DS_SUB_U64">;
796 def DS_RSUB_RTN_U64 : DS_1A1D_RET <0x62, "DS_RSUB_RTN_U64", VReg_64, "DS_RSUB_U64">;
797 def DS_INC_RTN_U64 : DS_1A1D_RET <0x63, "DS_INC_RTN_U64", VReg_64, "DS_INC_U64">;
798 def DS_DEC_RTN_U64 : DS_1A1D_RET <0x64, "DS_DEC_RTN_U64", VReg_64, "DS_DEC_U64">;
799 def DS_MIN_RTN_I64 : DS_1A1D_RET <0x65, "DS_MIN_RTN_I64", VReg_64, "DS_MIN_I64">;
800 def DS_MAX_RTN_I64 : DS_1A1D_RET <0x66, "DS_MAX_RTN_I64", VReg_64, "DS_MAX_I64">;
801 def DS_MIN_RTN_U64 : DS_1A1D_RET <0x67, "DS_MIN_RTN_U64", VReg_64, "DS_MIN_U64">;
802 def DS_MAX_RTN_U64 : DS_1A1D_RET <0x68, "DS_MAX_RTN_U64", VReg_64, "DS_MAX_U64">;
803 def DS_AND_RTN_B64 : DS_1A1D_RET <0x69, "DS_AND_RTN_B64", VReg_64, "DS_AND_B64">;
804 def DS_OR_RTN_B64 : DS_1A1D_RET <0x6a, "DS_OR_RTN_B64", VReg_64, "DS_OR_B64">;
805 def DS_XOR_RTN_B64 : DS_1A1D_RET <0x6b, "DS_XOR_RTN_B64", VReg_64, "DS_XOR_B64">;
806 def DS_MSKOR_RTN_B64 : DS_1A1D_RET <0x6c, "DS_MSKOR_RTN_B64", VReg_64, "DS_MSKOR_B64">;
807 def DS_WRXCHG_RTN_B64 : DS_1A1D_RET <0x6d, "DS_WRXCHG_RTN_B64", VReg_64, "DS_WRXCHG_B64">;
808 //def DS_WRXCHG2_RTN_B64 : DS_2A0D_RET <0x6e, "DS_WRXCHG2_RTN_B64", VReg_64, "DS_WRXCHG2_B64">;
809 //def DS_WRXCHG2ST64_RTN_B64 : DS_2A0D_RET <0x6f, "DS_WRXCHG2_RTN_B64", VReg_64, "DS_WRXCHG2ST64_B64">;
810 def DS_CMPST_RTN_B64 : DS_1A2D_RET <0x70, "DS_CMPST_RTN_B64", VReg_64, "DS_CMPST_B64">;
811 def DS_CMPST_RTN_F64 : DS_1A2D_RET <0x71, "DS_CMPST_RTN_F64", VReg_64, "DS_CMPST_F64">;
812 def DS_MIN_RTN_F64 : DS_1A1D_RET <0x72, "DS_MIN_F64", VReg_64, "DS_MIN_F64">;
813 def DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "DS_MAX_F64", VReg_64, "DS_MAX_F64">;
815 //let SubtargetPredicate = isCI in {
816 // DS_CONDXCHG32_RTN_B64
817 // DS_CONDXCHG32_RTN_B128
820 // TODO: _SRC2_* forms
822 def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>;
823 def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "DS_WRITE_B8", VReg_32>;
824 def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "DS_WRITE_B16", VReg_32>;
825 def DS_WRITE_B64 : DS_Store_Helper <0x00000004d, "DS_WRITE_B64", VReg_64>;
827 def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>;
828 def DS_READ_I8 : DS_Load_Helper <0x00000039, "DS_READ_I8", VReg_32>;
829 def DS_READ_U8 : DS_Load_Helper <0x0000003a, "DS_READ_U8", VReg_32>;
830 def DS_READ_I16 : DS_Load_Helper <0x0000003b, "DS_READ_I16", VReg_32>;
831 def DS_READ_U16 : DS_Load_Helper <0x0000003c, "DS_READ_U16", VReg_32>;
832 def DS_READ_B64 : DS_Load_Helper <0x00000076, "DS_READ_B64", VReg_64>;
835 def DS_WRITE2_B32 : DS_Store2_Helper <0x0000000E, "DS_WRITE2_B32", VReg_32>;
836 def DS_WRITE2ST64_B32 : DS_Store2_Helper <0x0000000F, "DS_WRITE2ST64_B32", VReg_32>;
837 def DS_WRITE2_B64 : DS_Store2_Helper <0x0000004E, "DS_WRITE2_B64", VReg_64>;
838 def DS_WRITE2ST64_B64 : DS_Store2_Helper <0x0000004F, "DS_WRITE2ST64_B64", VReg_64>;
840 def DS_READ2_B32 : DS_Load2_Helper <0x00000037, "DS_READ2_B32", VReg_64>;
841 def DS_READ2ST64_B32 : DS_Load2_Helper <0x00000038, "DS_READ2ST64_B32", VReg_64>;
842 def DS_READ2_B64 : DS_Load2_Helper <0x00000075, "DS_READ2_B64", VReg_128>;
843 def DS_READ2ST64_B64 : DS_Load2_Helper <0x00000076, "DS_READ2ST64_B64", VReg_128>;
845 //===----------------------------------------------------------------------===//
846 // MUBUF Instructions
847 //===----------------------------------------------------------------------===//
849 //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>;
850 //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>;
851 //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>;
852 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>;
853 //def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>;
854 //def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>;
855 //def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>;
856 //def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>;
857 defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <
858 0x00000008, "BUFFER_LOAD_UBYTE", VReg_32, i32, az_extloadi8_global
860 defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <
861 0x00000009, "BUFFER_LOAD_SBYTE", VReg_32, i32, sextloadi8_global
863 defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <
864 0x0000000a, "BUFFER_LOAD_USHORT", VReg_32, i32, az_extloadi16_global
866 defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <
867 0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32, i32, sextloadi16_global
869 defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <
870 0x0000000c, "BUFFER_LOAD_DWORD", VReg_32, i32, global_load
872 defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <
873 0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64, v2i32, global_load
875 defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <
876 0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128, v4i32, global_load
879 defm BUFFER_STORE_BYTE : MUBUF_Store_Helper <
880 0x00000018, "BUFFER_STORE_BYTE", VReg_32, i32, truncstorei8_global
883 defm BUFFER_STORE_SHORT : MUBUF_Store_Helper <
884 0x0000001a, "BUFFER_STORE_SHORT", VReg_32, i32, truncstorei16_global
887 defm BUFFER_STORE_DWORD : MUBUF_Store_Helper <
888 0x0000001c, "BUFFER_STORE_DWORD", VReg_32, i32, global_store
891 defm BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper <
892 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64, v2i32, global_store
895 defm BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper <
896 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128, v4i32, global_store
898 //def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>;
899 //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>;
900 defm BUFFER_ATOMIC_ADD : MUBUF_Atomic <
901 0x00000032, "BUFFER_ATOMIC_ADD", VReg_32, i32, atomic_add_global
903 //def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>;
904 //def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>;
905 //def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>;
906 //def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>;
907 //def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>;
908 //def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>;
909 //def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>;
910 //def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>;
911 //def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>;
912 //def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>;
913 //def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>;
914 //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>;
915 //def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>;
916 //def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>;
917 //def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>;
918 //def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>;
919 //def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>;
920 //def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>;
921 //def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>;
922 //def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>;
923 //def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>;
924 //def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>;
925 //def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>;
926 //def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>;
927 //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>;
928 //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>;
929 //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>;
930 //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>;
931 //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>;
932 //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>;
933 //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>;
934 //def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>;
935 //def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>;
937 //===----------------------------------------------------------------------===//
938 // MTBUF Instructions
939 //===----------------------------------------------------------------------===//
941 //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>;
942 //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>;
943 //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>;
944 defm TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>;
945 defm TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "TBUFFER_STORE_FORMAT_X", VReg_32>;
946 defm TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FORMAT_XY", VReg_64>;
947 defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>;
948 defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>;
950 //===----------------------------------------------------------------------===//
952 //===----------------------------------------------------------------------===//
954 defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "IMAGE_LOAD">;
955 defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "IMAGE_LOAD_MIP">;
956 //def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>;
957 //def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>;
958 //def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>;
959 //def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>;
960 //def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>;
961 //def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>;
962 //def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>;
963 //def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>;
964 defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "IMAGE_GET_RESINFO">;
965 //def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>;
966 //def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>;
967 //def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>;
968 //def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>;
969 //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>;
970 //def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>;
971 //def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>;
972 //def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>;
973 //def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>;
974 //def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>;
975 //def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>;
976 //def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>;
977 //def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>;
978 //def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>;
979 //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>;
980 //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>;
981 //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>;
982 defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">;
983 defm IMAGE_SAMPLE_CL : MIMG_Sampler <0x00000021, "IMAGE_SAMPLE_CL">;
984 defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">;
985 defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, "IMAGE_SAMPLE_D_CL">;
986 defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">;
987 defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">;
988 defm IMAGE_SAMPLE_B_CL : MIMG_Sampler <0x00000026, "IMAGE_SAMPLE_B_CL">;
989 defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, "IMAGE_SAMPLE_LZ">;
990 defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">;
991 defm IMAGE_SAMPLE_C_CL : MIMG_Sampler <0x00000029, "IMAGE_SAMPLE_C_CL">;
992 defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">;
993 defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, "IMAGE_SAMPLE_C_D_CL">;
994 defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">;
995 defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">;
996 defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler <0x0000002e, "IMAGE_SAMPLE_C_B_CL">;
997 defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, "IMAGE_SAMPLE_C_LZ">;
998 defm IMAGE_SAMPLE_O : MIMG_Sampler <0x00000030, "IMAGE_SAMPLE_O">;
999 defm IMAGE_SAMPLE_CL_O : MIMG_Sampler <0x00000031, "IMAGE_SAMPLE_CL_O">;
1000 defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, "IMAGE_SAMPLE_D_O">;
1001 defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, "IMAGE_SAMPLE_D_CL_O">;
1002 defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, "IMAGE_SAMPLE_L_O">;
1003 defm IMAGE_SAMPLE_B_O : MIMG_Sampler <0x00000035, "IMAGE_SAMPLE_B_O">;
1004 defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler <0x00000036, "IMAGE_SAMPLE_B_CL_O">;
1005 defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, "IMAGE_SAMPLE_LZ_O">;
1006 defm IMAGE_SAMPLE_C_O : MIMG_Sampler <0x00000038, "IMAGE_SAMPLE_C_O">;
1007 defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler <0x00000039, "IMAGE_SAMPLE_C_CL_O">;
1008 defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, "IMAGE_SAMPLE_C_D_O">;
1009 defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, "IMAGE_SAMPLE_C_D_CL_O">;
1010 defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, "IMAGE_SAMPLE_C_L_O">;
1011 defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler <0x0000003d, "IMAGE_SAMPLE_C_B_O">;
1012 defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler <0x0000003e, "IMAGE_SAMPLE_C_B_CL_O">;
1013 defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, "IMAGE_SAMPLE_C_LZ_O">;
1014 defm IMAGE_GATHER4 : MIMG_Gather <0x00000040, "IMAGE_GATHER4">;
1015 defm IMAGE_GATHER4_CL : MIMG_Gather <0x00000041, "IMAGE_GATHER4_CL">;
1016 defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, "IMAGE_GATHER4_L">;
1017 defm IMAGE_GATHER4_B : MIMG_Gather <0x00000045, "IMAGE_GATHER4_B">;
1018 defm IMAGE_GATHER4_B_CL : MIMG_Gather <0x00000046, "IMAGE_GATHER4_B_CL">;
1019 defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, "IMAGE_GATHER4_LZ">;
1020 defm IMAGE_GATHER4_C : MIMG_Gather <0x00000048, "IMAGE_GATHER4_C">;
1021 defm IMAGE_GATHER4_C_CL : MIMG_Gather <0x00000049, "IMAGE_GATHER4_C_CL">;
1022 defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, "IMAGE_GATHER4_C_L">;
1023 defm IMAGE_GATHER4_C_B : MIMG_Gather <0x0000004d, "IMAGE_GATHER4_C_B">;
1024 defm IMAGE_GATHER4_C_B_CL : MIMG_Gather <0x0000004e, "IMAGE_GATHER4_C_B_CL">;
1025 defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, "IMAGE_GATHER4_C_LZ">;
1026 defm IMAGE_GATHER4_O : MIMG_Gather <0x00000050, "IMAGE_GATHER4_O">;
1027 defm IMAGE_GATHER4_CL_O : MIMG_Gather <0x00000051, "IMAGE_GATHER4_CL_O">;
1028 defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, "IMAGE_GATHER4_L_O">;
1029 defm IMAGE_GATHER4_B_O : MIMG_Gather <0x00000055, "IMAGE_GATHER4_B_O">;
1030 defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, "IMAGE_GATHER4_B_CL_O">;
1031 defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, "IMAGE_GATHER4_LZ_O">;
1032 defm IMAGE_GATHER4_C_O : MIMG_Gather <0x00000058, "IMAGE_GATHER4_C_O">;
1033 defm IMAGE_GATHER4_C_CL_O : MIMG_Gather <0x00000059, "IMAGE_GATHER4_C_CL_O">;
1034 defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, "IMAGE_GATHER4_C_L_O">;
1035 defm IMAGE_GATHER4_C_B_O : MIMG_Gather <0x0000005d, "IMAGE_GATHER4_C_B_O">;
1036 defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather <0x0000005e, "IMAGE_GATHER4_C_B_CL_O">;
1037 defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, "IMAGE_GATHER4_C_LZ_O">;
1038 defm IMAGE_GET_LOD : MIMG_Sampler <0x00000060, "IMAGE_GET_LOD">;
1039 defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, "IMAGE_SAMPLE_CD">;
1040 defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, "IMAGE_SAMPLE_CD_CL">;
1041 defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, "IMAGE_SAMPLE_C_CD">;
1042 defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, "IMAGE_SAMPLE_C_CD_CL">;
1043 defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, "IMAGE_SAMPLE_CD_O">;
1044 defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, "IMAGE_SAMPLE_CD_CL_O">;
1045 defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, "IMAGE_SAMPLE_C_CD_O">;
1046 defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, "IMAGE_SAMPLE_C_CD_CL_O">;
1047 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>;
1048 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>;
1050 //===----------------------------------------------------------------------===//
1051 // Flat Instructions
1052 //===----------------------------------------------------------------------===//
1054 let Predicates = [HasFlatAddressSpace] in {
1055 def FLAT_LOAD_UBYTE : FLAT_Load_Helper <0x00000008, "FLAT_LOAD_UBYTE", VReg_32>;
1056 def FLAT_LOAD_SBYTE : FLAT_Load_Helper <0x00000009, "FLAT_LOAD_SBYTE", VReg_32>;
1057 def FLAT_LOAD_USHORT : FLAT_Load_Helper <0x0000000a, "FLAT_LOAD_USHORT", VReg_32>;
1058 def FLAT_LOAD_SSHORT : FLAT_Load_Helper <0x0000000b, "FLAT_LOAD_SSHORT", VReg_32>;
1059 def FLAT_LOAD_DWORD : FLAT_Load_Helper <0x0000000c, "FLAT_LOAD_DWORD", VReg_32>;
1060 def FLAT_LOAD_DWORDX2 : FLAT_Load_Helper <0x0000000d, "FLAT_LOAD_DWORDX2", VReg_64>;
1061 def FLAT_LOAD_DWORDX4 : FLAT_Load_Helper <0x0000000e, "FLAT_LOAD_DWORDX4", VReg_128>;
1062 def FLAT_LOAD_DWORDX3 : FLAT_Load_Helper <0x00000010, "FLAT_LOAD_DWORDX3", VReg_96>;
1064 def FLAT_STORE_BYTE : FLAT_Store_Helper <
1065 0x00000018, "FLAT_STORE_BYTE", VReg_32
1068 def FLAT_STORE_SHORT : FLAT_Store_Helper <
1069 0x0000001a, "FLAT_STORE_SHORT", VReg_32
1072 def FLAT_STORE_DWORD : FLAT_Store_Helper <
1073 0x0000001c, "FLAT_STORE_DWORD", VReg_32
1076 def FLAT_STORE_DWORDX2 : FLAT_Store_Helper <
1077 0x0000001d, "FLAT_STORE_DWORDX2", VReg_64
1080 def FLAT_STORE_DWORDX4 : FLAT_Store_Helper <
1081 0x0000001e, "FLAT_STORE_DWORDX4", VReg_128
1084 def FLAT_STORE_DWORDX3 : FLAT_Store_Helper <
1085 0x0000001e, "FLAT_STORE_DWORDX3", VReg_96
1088 //def FLAT_ATOMIC_SWAP : FLAT_ <0x00000030, "FLAT_ATOMIC_SWAP", []>;
1089 //def FLAT_ATOMIC_CMPSWAP : FLAT_ <0x00000031, "FLAT_ATOMIC_CMPSWAP", []>;
1090 //def FLAT_ATOMIC_ADD : FLAT_ <0x00000032, "FLAT_ATOMIC_ADD", []>;
1091 //def FLAT_ATOMIC_SUB : FLAT_ <0x00000033, "FLAT_ATOMIC_SUB", []>;
1092 //def FLAT_ATOMIC_RSUB : FLAT_ <0x00000034, "FLAT_ATOMIC_RSUB", []>;
1093 //def FLAT_ATOMIC_SMIN : FLAT_ <0x00000035, "FLAT_ATOMIC_SMIN", []>;
1094 //def FLAT_ATOMIC_UMIN : FLAT_ <0x00000036, "FLAT_ATOMIC_UMIN", []>;
1095 //def FLAT_ATOMIC_SMAX : FLAT_ <0x00000037, "FLAT_ATOMIC_SMAX", []>;
1096 //def FLAT_ATOMIC_UMAX : FLAT_ <0x00000038, "FLAT_ATOMIC_UMAX", []>;
1097 //def FLAT_ATOMIC_AND : FLAT_ <0x00000039, "FLAT_ATOMIC_AND", []>;
1098 //def FLAT_ATOMIC_OR : FLAT_ <0x0000003a, "FLAT_ATOMIC_OR", []>;
1099 //def FLAT_ATOMIC_XOR : FLAT_ <0x0000003b, "FLAT_ATOMIC_XOR", []>;
1100 //def FLAT_ATOMIC_INC : FLAT_ <0x0000003c, "FLAT_ATOMIC_INC", []>;
1101 //def FLAT_ATOMIC_DEC : FLAT_ <0x0000003d, "FLAT_ATOMIC_DEC", []>;
1102 //def FLAT_ATOMIC_FCMPSWAP : FLAT_ <0x0000003e, "FLAT_ATOMIC_FCMPSWAP", []>;
1103 //def FLAT_ATOMIC_FMIN : FLAT_ <0x0000003f, "FLAT_ATOMIC_FMIN", []>;
1104 //def FLAT_ATOMIC_FMAX : FLAT_ <0x00000040, "FLAT_ATOMIC_FMAX", []>;
1105 //def FLAT_ATOMIC_SWAP_X2 : FLAT_X2 <0x00000050, "FLAT_ATOMIC_SWAP_X2", []>;
1106 //def FLAT_ATOMIC_CMPSWAP_X2 : FLAT_X2 <0x00000051, "FLAT_ATOMIC_CMPSWAP_X2", []>;
1107 //def FLAT_ATOMIC_ADD_X2 : FLAT_X2 <0x00000052, "FLAT_ATOMIC_ADD_X2", []>;
1108 //def FLAT_ATOMIC_SUB_X2 : FLAT_X2 <0x00000053, "FLAT_ATOMIC_SUB_X2", []>;
1109 //def FLAT_ATOMIC_RSUB_X2 : FLAT_X2 <0x00000054, "FLAT_ATOMIC_RSUB_X2", []>;
1110 //def FLAT_ATOMIC_SMIN_X2 : FLAT_X2 <0x00000055, "FLAT_ATOMIC_SMIN_X2", []>;
1111 //def FLAT_ATOMIC_UMIN_X2 : FLAT_X2 <0x00000056, "FLAT_ATOMIC_UMIN_X2", []>;
1112 //def FLAT_ATOMIC_SMAX_X2 : FLAT_X2 <0x00000057, "FLAT_ATOMIC_SMAX_X2", []>;
1113 //def FLAT_ATOMIC_UMAX_X2 : FLAT_X2 <0x00000058, "FLAT_ATOMIC_UMAX_X2", []>;
1114 //def FLAT_ATOMIC_AND_X2 : FLAT_X2 <0x00000059, "FLAT_ATOMIC_AND_X2", []>;
1115 //def FLAT_ATOMIC_OR_X2 : FLAT_X2 <0x0000005a, "FLAT_ATOMIC_OR_X2", []>;
1116 //def FLAT_ATOMIC_XOR_X2 : FLAT_X2 <0x0000005b, "FLAT_ATOMIC_XOR_X2", []>;
1117 //def FLAT_ATOMIC_INC_X2 : FLAT_X2 <0x0000005c, "FLAT_ATOMIC_INC_X2", []>;
1118 //def FLAT_ATOMIC_DEC_X2 : FLAT_X2 <0x0000005d, "FLAT_ATOMIC_DEC_X2", []>;
1119 //def FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_X2 <0x0000005e, "FLAT_ATOMIC_FCMPSWAP_X2", []>;
1120 //def FLAT_ATOMIC_FMIN_X2 : FLAT_X2 <0x0000005f, "FLAT_ATOMIC_FMIN_X2", []>;
1121 //def FLAT_ATOMIC_FMAX_X2 : FLAT_X2 <0x00000060, "FLAT_ATOMIC_FMAX_X2", []>;
1123 } // End HasFlatAddressSpace predicate
1124 //===----------------------------------------------------------------------===//
1125 // VOP1 Instructions
1126 //===----------------------------------------------------------------------===//
1128 //def V_NOP : VOP1_ <0x00000000, "V_NOP", []>;
1130 let isMoveImm = 1 in {
1131 defm V_MOV_B32 : VOP1Inst <vop1<0x1>, "V_MOV_B32", VOP_I32_I32>;
1132 } // End isMoveImm = 1
1134 let Uses = [EXEC] in {
1136 def V_READFIRSTLANE_B32 : VOP1 <
1138 (outs SReg_32:$vdst),
1139 (ins VReg_32:$src0),
1140 "V_READFIRSTLANE_B32 $vdst, $src0",
1146 defm V_CVT_I32_F64 : VOP1Inst <vop1<0x3>, "V_CVT_I32_F64",
1147 VOP_I32_F64, fp_to_sint
1149 defm V_CVT_F64_I32 : VOP1Inst <vop1<0x4>, "V_CVT_F64_I32",
1150 VOP_F64_I32, sint_to_fp
1152 defm V_CVT_F32_I32 : VOP1Inst <vop1<0x5>, "V_CVT_F32_I32",
1153 VOP_F32_I32, sint_to_fp
1155 defm V_CVT_F32_U32 : VOP1Inst <vop1<0x6>, "V_CVT_F32_U32",
1156 VOP_F32_I32, uint_to_fp
1158 defm V_CVT_U32_F32 : VOP1Inst <vop1<0x7>, "V_CVT_U32_F32",
1159 VOP_I32_F32, fp_to_uint
1161 defm V_CVT_I32_F32 : VOP1Inst <vop1<0x8>, "V_CVT_I32_F32",
1162 VOP_I32_F32, fp_to_sint
1164 defm V_MOV_FED_B32 : VOP1Inst <vop1<0x9>, "V_MOV_FED_B32", VOP_I32_I32>;
1165 defm V_CVT_F16_F32 : VOP1Inst <vop1<0xa>, "V_CVT_F16_F32",
1166 VOP_I32_F32, fp_to_f16
1168 defm V_CVT_F32_F16 : VOP1Inst <vop1<0xb>, "V_CVT_F32_F16",
1169 VOP_F32_I32, f16_to_fp
1171 //defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>;
1172 //defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>;
1173 //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>;
1174 defm V_CVT_F32_F64 : VOP1Inst <vop1<0xf>, "V_CVT_F32_F64",
1177 defm V_CVT_F64_F32 : VOP1Inst <vop1<0x10>, "V_CVT_F64_F32",
1178 VOP_F64_F32, fextend
1180 defm V_CVT_F32_UBYTE0 : VOP1Inst <vop1<0x11>, "V_CVT_F32_UBYTE0",
1181 VOP_F32_I32, AMDGPUcvt_f32_ubyte0
1183 defm V_CVT_F32_UBYTE1 : VOP1Inst <vop1<0x12>, "V_CVT_F32_UBYTE1",
1184 VOP_F32_I32, AMDGPUcvt_f32_ubyte1
1186 defm V_CVT_F32_UBYTE2 : VOP1Inst <vop1<0x13>, "V_CVT_F32_UBYTE2",
1187 VOP_F32_I32, AMDGPUcvt_f32_ubyte2
1189 defm V_CVT_F32_UBYTE3 : VOP1Inst <vop1<0x14>, "V_CVT_F32_UBYTE3",
1190 VOP_F32_I32, AMDGPUcvt_f32_ubyte3
1192 defm V_CVT_U32_F64 : VOP1Inst <vop1<0x15>, "V_CVT_U32_F64",
1193 VOP_I32_F64, fp_to_uint
1195 defm V_CVT_F64_U32 : VOP1Inst <vop1<0x16>, "V_CVT_F64_U32",
1196 VOP_F64_I32, uint_to_fp
1199 defm V_FRACT_F32 : VOP1Inst <vop1<0x20>, "V_FRACT_F32",
1200 VOP_F32_F32, AMDGPUfract
1202 defm V_TRUNC_F32 : VOP1Inst <vop1<0x21>, "V_TRUNC_F32",
1205 defm V_CEIL_F32 : VOP1Inst <vop1<0x22>, "V_CEIL_F32",
1208 defm V_RNDNE_F32 : VOP1Inst <vop1<0x23>, "V_RNDNE_F32",
1211 defm V_FLOOR_F32 : VOP1Inst <vop1<0x24>, "V_FLOOR_F32",
1214 defm V_EXP_F32 : VOP1Inst <vop1<0x25>, "V_EXP_F32",
1217 defm V_LOG_CLAMP_F32 : VOP1Inst <vop1<0x26>, "V_LOG_CLAMP_F32", VOP_F32_F32>;
1218 defm V_LOG_F32 : VOP1Inst <vop1<0x27>, "V_LOG_F32",
1222 defm V_RCP_CLAMP_F32 : VOP1Inst <vop1<0x28>, "V_RCP_CLAMP_F32", VOP_F32_F32>;
1223 defm V_RCP_LEGACY_F32 : VOP1Inst <vop1<0x29>, "V_RCP_LEGACY_F32", VOP_F32_F32>;
1224 defm V_RCP_F32 : VOP1Inst <vop1<0x2a>, "V_RCP_F32",
1225 VOP_F32_F32, AMDGPUrcp
1227 defm V_RCP_IFLAG_F32 : VOP1Inst <vop1<0x2b>, "V_RCP_IFLAG_F32", VOP_F32_F32>;
1228 defm V_RSQ_CLAMP_F32 : VOP1Inst <vop1<0x2c>, "V_RSQ_CLAMP_F32",
1229 VOP_F32_F32, AMDGPUrsq_clamped
1231 defm V_RSQ_LEGACY_F32 : VOP1Inst <vop1<0x2d>, "V_RSQ_LEGACY_F32",
1232 VOP_F32_F32, AMDGPUrsq_legacy
1234 defm V_RSQ_F32 : VOP1Inst <vop1<0x2e>, "V_RSQ_F32",
1235 VOP_F32_F32, AMDGPUrsq
1237 defm V_RCP_F64 : VOP1Inst <vop1<0x2f>, "V_RCP_F64",
1238 VOP_F64_F64, AMDGPUrcp
1240 defm V_RCP_CLAMP_F64 : VOP1Inst <vop1<0x30>, "V_RCP_CLAMP_F64", VOP_F64_F64>;
1241 defm V_RSQ_F64 : VOP1Inst <vop1<0x31>, "V_RSQ_F64",
1242 VOP_F64_F64, AMDGPUrsq
1244 defm V_RSQ_CLAMP_F64 : VOP1Inst <vop1<0x32>, "V_RSQ_CLAMP_F64",
1245 VOP_F64_F64, AMDGPUrsq_clamped
1247 defm V_SQRT_F32 : VOP1Inst <vop1<0x33>, "V_SQRT_F32",
1250 defm V_SQRT_F64 : VOP1Inst <vop1<0x34>, "V_SQRT_F64",
1253 defm V_SIN_F32 : VOP1Inst <vop1<0x35>, "V_SIN_F32",
1254 VOP_F32_F32, AMDGPUsin
1256 defm V_COS_F32 : VOP1Inst <vop1<0x36>, "V_COS_F32",
1257 VOP_F32_F32, AMDGPUcos
1259 defm V_NOT_B32 : VOP1Inst <vop1<0x37>, "V_NOT_B32", VOP_I32_I32>;
1260 defm V_BFREV_B32 : VOP1Inst <vop1<0x38>, "V_BFREV_B32", VOP_I32_I32>;
1261 defm V_FFBH_U32 : VOP1Inst <vop1<0x39>, "V_FFBH_U32", VOP_I32_I32>;
1262 defm V_FFBL_B32 : VOP1Inst <vop1<0x3a>, "V_FFBL_B32", VOP_I32_I32>;
1263 defm V_FFBH_I32 : VOP1Inst <vop1<0x3b>, "V_FFBH_I32", VOP_I32_I32>;
1264 //defm V_FREXP_EXP_I32_F64 : VOPInst <0x0000003c, "V_FREXP_EXP_I32_F64", VOP_I32_F32>;
1265 defm V_FREXP_MANT_F64 : VOP1Inst <vop1<0x3d>, "V_FREXP_MANT_F64", VOP_F64_F64>;
1266 defm V_FRACT_F64 : VOP1Inst <vop1<0x3e>, "V_FRACT_F64", VOP_F64_F64>;
1267 //defm V_FREXP_EXP_I32_F32 : VOPInst <0x0000003f, "V_FREXP_EXP_I32_F32", VOP_I32_F32>;
1268 defm V_FREXP_MANT_F32 : VOP1Inst <vop1<0x40>, "V_FREXP_MANT_F32", VOP_F32_F32>;
1269 //def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>;
1270 defm V_MOVRELD_B32 : VOP1Inst <vop1<0x42>, "V_MOVRELD_B32", VOP_I32_I32>;
1271 defm V_MOVRELS_B32 : VOP1Inst <vop1<0x43>, "V_MOVRELS_B32", VOP_I32_I32>;
1272 defm V_MOVRELSD_B32 : VOP1Inst <vop1<0x44>, "V_MOVRELSD_B32", VOP_I32_I32>;
1275 //===----------------------------------------------------------------------===//
1276 // VINTRP Instructions
1277 //===----------------------------------------------------------------------===//
1279 def V_INTERP_P1_F32 : VINTRP <
1281 (outs VReg_32:$dst),
1282 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1283 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]",
1285 let DisableEncoding = "$m0";
1288 def V_INTERP_P2_F32 : VINTRP <
1290 (outs VReg_32:$dst),
1291 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1292 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]",
1295 let Constraints = "$src0 = $dst";
1296 let DisableEncoding = "$src0,$m0";
1300 def V_INTERP_MOV_F32 : VINTRP <
1302 (outs VReg_32:$dst),
1303 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1304 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]",
1306 let DisableEncoding = "$m0";
1309 //===----------------------------------------------------------------------===//
1310 // VOP2 Instructions
1311 //===----------------------------------------------------------------------===//
1313 def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
1314 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc),
1315 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]",
1318 let DisableEncoding = "$vcc";
1321 def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst),
1322 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2),
1323 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2",
1324 [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))]
1326 let src0_modifiers = 0;
1327 let src1_modifiers = 0;
1328 let src2_modifiers = 0;
1331 def V_READLANE_B32 : VOP2 <
1333 (outs SReg_32:$vdst),
1334 (ins VReg_32:$src0, SSrc_32:$vsrc1),
1335 "V_READLANE_B32 $vdst, $src0, $vsrc1",
1339 def V_WRITELANE_B32 : VOP2 <
1341 (outs VReg_32:$vdst),
1342 (ins SReg_32:$src0, SSrc_32:$vsrc1),
1343 "V_WRITELANE_B32 $vdst, $src0, $vsrc1",
1347 let isCommutable = 1 in {
1348 defm V_ADD_F32 : VOP2Inst <vop2<0x3>, "V_ADD_F32",
1349 VOP_F32_F32_F32, fadd
1352 defm V_SUB_F32 : VOP2Inst <vop2<0x4>, "V_SUB_F32", VOP_F32_F32_F32, fsub>;
1353 defm V_SUBREV_F32 : VOP2Inst <vop2<0x5>, "V_SUBREV_F32",
1354 VOP_F32_F32_F32, null_frag, "V_SUB_F32"
1356 } // End isCommutable = 1
1358 defm V_MAC_LEGACY_F32 : VOP2Inst <vop2<0x6>, "V_MAC_LEGACY_F32",
1362 let isCommutable = 1 in {
1364 defm V_MUL_LEGACY_F32 : VOP2Inst <vop2<0x7>, "V_MUL_LEGACY_F32",
1365 VOP_F32_F32_F32, int_AMDGPU_mul
1368 defm V_MUL_F32 : VOP2Inst <vop2<0x8>, "V_MUL_F32",
1369 VOP_F32_F32_F32, fmul
1373 defm V_MUL_I32_I24 : VOP2Inst <vop2<0x9>, "V_MUL_I32_I24",
1374 VOP_I32_I32_I32, AMDGPUmul_i24
1376 //defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>;
1377 defm V_MUL_U32_U24 : VOP2Inst <vop2<0xb>, "V_MUL_U32_U24",
1378 VOP_I32_I32_I32, AMDGPUmul_u24
1380 //defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>;
1383 defm V_MIN_LEGACY_F32 : VOP2Inst <vop2<0xd>, "V_MIN_LEGACY_F32",
1384 VOP_F32_F32_F32, AMDGPUfmin
1387 defm V_MAX_LEGACY_F32 : VOP2Inst <vop2<0xe>, "V_MAX_LEGACY_F32",
1388 VOP_F32_F32_F32, AMDGPUfmax
1391 defm V_MIN_F32 : VOP2Inst <vop2<0xf>, "V_MIN_F32", VOP_F32_F32_F32>;
1392 defm V_MAX_F32 : VOP2Inst <vop2<0x10>, "V_MAX_F32", VOP_F32_F32_F32>;
1393 defm V_MIN_I32 : VOP2Inst <vop2<0x11>, "V_MIN_I32", VOP_I32_I32_I32, AMDGPUsmin>;
1394 defm V_MAX_I32 : VOP2Inst <vop2<0x12>, "V_MAX_I32", VOP_I32_I32_I32, AMDGPUsmax>;
1395 defm V_MIN_U32 : VOP2Inst <vop2<0x13>, "V_MIN_U32", VOP_I32_I32_I32, AMDGPUumin>;
1396 defm V_MAX_U32 : VOP2Inst <vop2<0x14>, "V_MAX_U32", VOP_I32_I32_I32, AMDGPUumax>;
1398 defm V_LSHR_B32 : VOP2Inst <vop2<0x15>, "V_LSHR_B32", VOP_I32_I32_I32, srl>;
1400 defm V_LSHRREV_B32 : VOP2Inst <
1401 vop2<0x16>, "V_LSHRREV_B32", VOP_I32_I32_I32, null_frag, "V_LSHR_B32"
1404 defm V_ASHR_I32 : VOP2Inst <vop2<0x17>, "V_ASHR_I32",
1405 VOP_I32_I32_I32, sra
1407 defm V_ASHRREV_I32 : VOP2Inst <
1408 vop2<0x18>, "V_ASHRREV_I32", VOP_I32_I32_I32, null_frag, "V_ASHR_I32"
1411 let hasPostISelHook = 1 in {
1413 defm V_LSHL_B32 : VOP2Inst <vop2<0x19>, "V_LSHL_B32", VOP_I32_I32_I32, shl>;
1416 defm V_LSHLREV_B32 : VOP2Inst <
1417 vop2<0x1a>, "V_LSHLREV_B32", VOP_I32_I32_I32, null_frag, "V_LSHL_B32"
1420 defm V_AND_B32 : VOP2Inst <vop2<0x1b>, "V_AND_B32",
1421 VOP_I32_I32_I32, and>;
1422 defm V_OR_B32 : VOP2Inst <vop2<0x1c>, "V_OR_B32",
1425 defm V_XOR_B32 : VOP2Inst <vop2<0x1d>, "V_XOR_B32",
1426 VOP_I32_I32_I32, xor
1429 } // End isCommutable = 1
1431 defm V_BFM_B32 : VOP2Inst <vop2<0x1e>, "V_BFM_B32",
1432 VOP_I32_I32_I32, AMDGPUbfm>;
1433 defm V_MAC_F32 : VOP2Inst <vop2<0x1f>, "V_MAC_F32", VOP_F32_F32_F32>;
1434 defm V_MADMK_F32 : VOP2Inst <vop2<0x20>, "V_MADMK_F32", VOP_F32_F32_F32>;
1435 defm V_MADAK_F32 : VOP2Inst <vop2<0x21>, "V_MADAK_F32", VOP_F32_F32_F32>;
1436 defm V_BCNT_U32_B32 : VOP2Inst <vop2<0x22>, "V_BCNT_U32_B32", VOP_I32_I32_I32>;
1437 defm V_MBCNT_LO_U32_B32 : VOP2Inst <vop2<0x23>, "V_MBCNT_LO_U32_B32",
1440 defm V_MBCNT_HI_U32_B32 : VOP2Inst <vop2<0x24>, "V_MBCNT_HI_U32_B32",
1444 let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC
1445 // No patterns so that the scalar instructions are always selected.
1446 // The scalar versions will be replaced with vector when needed later.
1447 defm V_ADD_I32 : VOP2bInst <vop2<0x25>, "V_ADD_I32",
1448 VOP_I32_I32_I32, add
1450 defm V_SUB_I32 : VOP2bInst <vop2<0x26>, "V_SUB_I32",
1451 VOP_I32_I32_I32, sub
1453 defm V_SUBREV_I32 : VOP2bInst <vop2<0x27>, "V_SUBREV_I32",
1454 VOP_I32_I32_I32, null_frag, "V_SUB_I32"
1457 let Uses = [VCC] in { // Carry-in comes from VCC
1458 defm V_ADDC_U32 : VOP2bInst <vop2<0x28>, "V_ADDC_U32",
1459 VOP_I32_I32_I32_VCC, adde
1461 defm V_SUBB_U32 : VOP2bInst <vop2<0x29>, "V_SUBB_U32",
1462 VOP_I32_I32_I32_VCC, sube
1464 defm V_SUBBREV_U32 : VOP2bInst <vop2<0x2a>, "V_SUBBREV_U32",
1465 VOP_I32_I32_I32_VCC, null_frag, "V_SUBB_U32"
1468 } // End Uses = [VCC]
1469 } // End isCommutable = 1, Defs = [VCC]
1471 defm V_LDEXP_F32 : VOP2Inst <vop2<0x2b>, "V_LDEXP_F32",
1472 VOP_F32_F32_I32, AMDGPUldexp
1474 ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>;
1475 ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>;
1476 ////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>;
1477 defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <vop2<0x2f>, "V_CVT_PKRTZ_F16_F32",
1478 VOP_I32_F32_F32, int_SI_packf16
1480 ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>;
1481 ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>;
1483 //===----------------------------------------------------------------------===//
1484 // VOP3 Instructions
1485 //===----------------------------------------------------------------------===//
1487 defm V_MAD_LEGACY_F32 : VOP3Inst <vop3<0x140>, "V_MAD_LEGACY_F32",
1490 defm V_MAD_F32 : VOP3Inst <vop3<0x141>, "V_MAD_F32",
1491 VOP_F32_F32_F32_F32, fmad
1493 defm V_MAD_I32_I24 : VOP3Inst <vop3<0x142>, "V_MAD_I32_I24",
1494 VOP_I32_I32_I32_I32, AMDGPUmad_i24
1496 defm V_MAD_U32_U24 : VOP3Inst <vop3<0x143>, "V_MAD_U32_U24",
1497 VOP_I32_I32_I32_I32, AMDGPUmad_u24
1500 defm V_CUBEID_F32 : VOP3Inst <vop3<0x144>, "V_CUBEID_F32",
1503 defm V_CUBESC_F32 : VOP3Inst <vop3<0x145>, "V_CUBESC_F32",
1506 defm V_CUBETC_F32 : VOP3Inst <vop3<0x146>, "V_CUBETC_F32",
1509 defm V_CUBEMA_F32 : VOP3Inst <vop3<0x147>, "V_CUBEMA_F32",
1513 let neverHasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
1514 defm V_BFE_U32 : VOP3Inst <vop3<0x148>, "V_BFE_U32",
1515 VOP_I32_I32_I32_I32, AMDGPUbfe_u32
1517 defm V_BFE_I32 : VOP3Inst <vop3<0x149>, "V_BFE_I32",
1518 VOP_I32_I32_I32_I32, AMDGPUbfe_i32
1522 defm V_BFI_B32 : VOP3Inst <vop3<0x14a>, "V_BFI_B32",
1523 VOP_I32_I32_I32_I32, AMDGPUbfi
1525 defm V_FMA_F32 : VOP3Inst <vop3<0x14b>, "V_FMA_F32",
1526 VOP_F32_F32_F32_F32, fma
1528 defm V_FMA_F64 : VOP3Inst <vop3<0x14c>, "V_FMA_F64",
1529 VOP_F64_F64_F64_F64, fma
1531 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>;
1532 defm V_ALIGNBIT_B32 : VOP3Inst <vop3<0x14e>, "V_ALIGNBIT_B32",
1535 defm V_ALIGNBYTE_B32 : VOP3Inst <vop3<0x14f>, "V_ALIGNBYTE_B32",
1538 defm V_MULLIT_F32 : VOP3Inst <vop3<0x150>, "V_MULLIT_F32",
1539 VOP_F32_F32_F32_F32>;
1540 ////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>;
1541 ////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>;
1542 ////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>;
1543 ////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>;
1544 ////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>;
1545 ////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>;
1546 ////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>;
1547 ////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>;
1548 ////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>;
1549 //def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>;
1550 //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>;
1551 //def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>;
1552 defm V_SAD_U32 : VOP3Inst <vop3<0x15d>, "V_SAD_U32",
1555 ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>;
1556 defm V_DIV_FIXUP_F32 : VOP3Inst <
1557 vop3<0x15f>, "V_DIV_FIXUP_F32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup
1559 defm V_DIV_FIXUP_F64 : VOP3Inst <
1560 vop3<0x160>, "V_DIV_FIXUP_F64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup
1563 defm V_LSHL_B64 : VOP3Inst <vop3<0x161>, "V_LSHL_B64",
1564 VOP_I64_I64_I32, shl
1566 defm V_LSHR_B64 : VOP3Inst <vop3<0x162>, "V_LSHR_B64",
1567 VOP_I64_I64_I32, srl
1569 defm V_ASHR_I64 : VOP3Inst <vop3<0x163>, "V_ASHR_I64",
1570 VOP_I64_I64_I32, sra
1573 let isCommutable = 1 in {
1575 defm V_ADD_F64 : VOP3Inst <vop3<0x164>, "V_ADD_F64",
1576 VOP_F64_F64_F64, fadd
1578 defm V_MUL_F64 : VOP3Inst <vop3<0x165>, "V_MUL_F64",
1579 VOP_F64_F64_F64, fmul
1581 defm V_MIN_F64 : VOP3Inst <vop3<0x166>, "V_MIN_F64",
1584 defm V_MAX_F64 : VOP3Inst <vop3<0x167>, "V_MAX_F64",
1588 } // isCommutable = 1
1590 defm V_LDEXP_F64 : VOP3Inst <vop3<0x168>, "V_LDEXP_F64",
1591 VOP_F64_F64_I32, AMDGPUldexp
1594 let isCommutable = 1 in {
1596 defm V_MUL_LO_U32 : VOP3Inst <vop3<0x169>, "V_MUL_LO_U32",
1599 defm V_MUL_HI_U32 : VOP3Inst <vop3<0x16a>, "V_MUL_HI_U32",
1602 defm V_MUL_LO_I32 : VOP3Inst <vop3<0x16b>, "V_MUL_LO_I32",
1605 defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c>, "V_MUL_HI_I32",
1609 } // isCommutable = 1
1611 defm V_DIV_SCALE_F32 : VOP3b_32 <vop3<0x16d>, "V_DIV_SCALE_F32", []>;
1613 // Double precision division pre-scale.
1614 defm V_DIV_SCALE_F64 : VOP3b_64 <vop3<0x16e>, "V_DIV_SCALE_F64", []>;
1616 defm V_DIV_FMAS_F32 : VOP3Inst <vop3<0x16f>, "V_DIV_FMAS_F32",
1617 VOP_F32_F32_F32_F32, AMDGPUdiv_fmas
1619 defm V_DIV_FMAS_F64 : VOP3Inst <vop3<0x170>, "V_DIV_FMAS_F64",
1620 VOP_F64_F64_F64_F64, AMDGPUdiv_fmas
1622 //def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>;
1623 //def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>;
1624 //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>;
1625 defm V_TRIG_PREOP_F64 : VOP3Inst <
1626 vop3<0x174>, "V_TRIG_PREOP_F64", VOP_F64_F64_I32, AMDGPUtrig_preop
1629 //===----------------------------------------------------------------------===//
1630 // Pseudo Instructions
1631 //===----------------------------------------------------------------------===//
1633 let isCodeGenOnly = 1, isPseudo = 1 in {
1635 def V_MOV_I1 : InstSI <
1638 "", [(set i1:$dst, (imm:$src))]
1641 def V_AND_I1 : InstSI <
1642 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1643 [(set i1:$dst, (and i1:$src0, i1:$src1))]
1646 def V_OR_I1 : InstSI <
1647 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1648 [(set i1:$dst, (or i1:$src0, i1:$src1))]
1651 def V_XOR_I1 : InstSI <
1652 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1653 [(set i1:$dst, (xor i1:$src0, i1:$src1))]
1656 let hasSideEffects = 1 in {
1657 def SGPR_USE : InstSI <(outs),(ins), "", []>;
1660 // SI pseudo instructions. These are used by the CFG structurizer pass
1661 // and should be lowered to ISA instructions prior to codegen.
1663 let mayLoad = 1, mayStore = 1, hasSideEffects = 1,
1664 Uses = [EXEC], Defs = [EXEC] in {
1666 let isBranch = 1, isTerminator = 1 in {
1669 (outs SReg_64:$dst),
1670 (ins SReg_64:$vcc, brtarget:$target),
1672 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))]
1675 def SI_ELSE : InstSI <
1676 (outs SReg_64:$dst),
1677 (ins SReg_64:$src, brtarget:$target),
1679 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]
1681 let Constraints = "$src = $dst";
1684 def SI_LOOP : InstSI <
1686 (ins SReg_64:$saved, brtarget:$target),
1687 "SI_LOOP $saved, $target",
1688 [(int_SI_loop i64:$saved, bb:$target)]
1691 } // end isBranch = 1, isTerminator = 1
1693 def SI_BREAK : InstSI <
1694 (outs SReg_64:$dst),
1696 "SI_ELSE $dst, $src",
1697 [(set i64:$dst, (int_SI_break i64:$src))]
1700 def SI_IF_BREAK : InstSI <
1701 (outs SReg_64:$dst),
1702 (ins SReg_64:$vcc, SReg_64:$src),
1703 "SI_IF_BREAK $dst, $vcc, $src",
1704 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))]
1707 def SI_ELSE_BREAK : InstSI <
1708 (outs SReg_64:$dst),
1709 (ins SReg_64:$src0, SReg_64:$src1),
1710 "SI_ELSE_BREAK $dst, $src0, $src1",
1711 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))]
1714 def SI_END_CF : InstSI <
1716 (ins SReg_64:$saved),
1718 [(int_SI_end_cf i64:$saved)]
1721 def SI_KILL : InstSI <
1725 [(int_AMDGPU_kill f32:$src)]
1728 } // end mayLoad = 1, mayStore = 1, hasSideEffects = 1
1729 // Uses = [EXEC], Defs = [EXEC]
1731 let Uses = [EXEC], Defs = [EXEC,VCC,M0] in {
1733 //defm SI_ : RegisterLoadStore <VReg_32, FRAMEri, ADDRIndirect>;
1735 let UseNamedOperandTable = 1 in {
1737 def SI_RegisterLoad : InstSI <
1738 (outs VReg_32:$dst, SReg_64:$temp),
1739 (ins FRAMEri32:$addr, i32imm:$chan),
1742 let isRegisterLoad = 1;
1746 class SIRegStore<dag outs> : InstSI <
1748 (ins VReg_32:$val, FRAMEri32:$addr, i32imm:$chan),
1751 let isRegisterStore = 1;
1755 let usesCustomInserter = 1 in {
1756 def SI_RegisterStorePseudo : SIRegStore<(outs)>;
1757 } // End usesCustomInserter = 1
1758 def SI_RegisterStore : SIRegStore<(outs SReg_64:$temp)>;
1761 } // End UseNamedOperandTable = 1
1763 def SI_INDIRECT_SRC : InstSI <
1764 (outs VReg_32:$dst, SReg_64:$temp),
1765 (ins unknown:$src, VSrc_32:$idx, i32imm:$off),
1766 "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off",
1770 class SI_INDIRECT_DST<RegisterClass rc> : InstSI <
1771 (outs rc:$dst, SReg_64:$temp),
1772 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val),
1773 "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val",
1776 let Constraints = "$src = $dst";
1779 def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VReg_32>;
1780 def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
1781 def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
1782 def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
1783 def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
1785 } // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0]
1787 let usesCustomInserter = 1 in {
1789 // This pseudo instruction takes a pointer as input and outputs a resource
1790 // constant that can be used with the ADDR64 MUBUF instructions.
1791 def SI_ADDR64_RSRC : InstSI <
1792 (outs SReg_128:$srsrc),
1797 def V_SUB_F64 : InstSI <
1798 (outs VReg_64:$dst),
1799 (ins VReg_64:$src0, VReg_64:$src1),
1800 "V_SUB_F64 $dst, $src0, $src1",
1801 [(set f64:$dst, (fsub f64:$src0, f64:$src1))]
1804 } // end usesCustomInserter
1806 multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
1808 def _SAVE : InstSI <
1810 (ins sgpr_class:$src, i32imm:$frame_idx),
1814 def _RESTORE : InstSI <
1815 (outs sgpr_class:$dst),
1816 (ins i32imm:$frame_idx),
1822 defm SI_SPILL_S32 : SI_SPILL_SGPR <SReg_32>;
1823 defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>;
1824 defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>;
1825 defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>;
1826 defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;
1828 multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> {
1829 def _SAVE : InstSI <
1831 (ins vgpr_class:$src, i32imm:$frame_idx),
1835 def _RESTORE : InstSI <
1836 (outs vgpr_class:$dst),
1837 (ins i32imm:$frame_idx),
1842 defm SI_SPILL_V32 : SI_SPILL_VGPR <VReg_32>;
1843 defm SI_SPILL_V64 : SI_SPILL_VGPR <VReg_64>;
1844 defm SI_SPILL_V96 : SI_SPILL_VGPR <VReg_96>;
1845 defm SI_SPILL_V128 : SI_SPILL_VGPR <VReg_128>;
1846 defm SI_SPILL_V256 : SI_SPILL_VGPR <VReg_256>;
1847 defm SI_SPILL_V512 : SI_SPILL_VGPR <VReg_512>;
1849 let Defs = [SCC] in {
1851 def SI_CONSTDATA_PTR : InstSI <
1852 (outs SReg_64:$dst),
1854 "", [(set SReg_64:$dst, (i64 SIconstdata_ptr))]
1857 } // End Defs = [SCC]
1859 } // end IsCodeGenOnly, isPseudo
1861 } // end SubtargetPredicate = SI
1863 let Predicates = [isSI] in {
1866 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2),
1867 (V_CNDMASK_B32_e64 $src2, $src1,
1868 (V_CMP_GT_F32_e64 SRCMODS.NONE, 0, SRCMODS.NONE, $src0,
1869 DSTCLAMP.NONE, DSTOMOD.NONE))
1874 (SI_KILL 0xbf800000)
1877 /* int_SI_vs_load_input */
1879 (SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr),
1880 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0)
1885 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
1886 f32:$src0, f32:$src1, f32:$src2, f32:$src3),
1887 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
1888 $src0, $src1, $src2, $src3)
1891 //===----------------------------------------------------------------------===//
1893 //===----------------------------------------------------------------------===//
1895 multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
1897 // 1. Offset as 8bit DWORD immediate
1899 (constant_load (add i64:$sbase, (i64 IMM8bitDWORD:$offset))),
1900 (vt (Instr_IMM $sbase, (as_dword_i32imm $offset)))
1903 // 2. Offset loaded in an 32bit SGPR
1905 (constant_load (add i64:$sbase, (i64 IMM32bit:$offset))),
1906 (vt (Instr_SGPR $sbase, (S_MOV_B32 (i32 (as_i32imm $offset)))))
1909 // 3. No offset at all
1911 (constant_load i64:$sbase),
1912 (vt (Instr_IMM $sbase, 0))
1916 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>;
1917 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
1918 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>;
1919 defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>;
1920 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
1921 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>;
1922 defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
1924 // 1. Offset as 8bit DWORD immediate
1926 (SIload_constant v4i32:$sbase, IMM8bitDWORD:$offset),
1927 (S_BUFFER_LOAD_DWORD_IMM $sbase, (as_dword_i32imm $offset))
1930 // 2. Offset loaded in an 32bit SGPR
1932 (SIload_constant v4i32:$sbase, imm:$offset),
1933 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset))
1936 } // Predicates = [isSI] in {
1938 //===----------------------------------------------------------------------===//
1940 //===----------------------------------------------------------------------===//
1943 (i64 (ctpop i64:$src)),
1944 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1945 (S_BCNT1_I32_B64 $src), sub0),
1946 (S_MOV_B32 0), sub1)
1949 //===----------------------------------------------------------------------===//
1951 //===----------------------------------------------------------------------===//
1953 // V_ADD_I32_e32/S_ADD_U32 produces carry in VCC/SCC. For the vector
1954 // case, the sgpr-copies pass will fix this to use the vector version.
1956 (i32 (addc i32:$src0, i32:$src1)),
1957 (S_ADD_U32 $src0, $src1)
1960 let Predicates = [isSI] in {
1962 //===----------------------------------------------------------------------===//
1964 //===----------------------------------------------------------------------===//
1967 (int_AMDGPU_barrier_global),
1971 //===----------------------------------------------------------------------===//
1973 //===----------------------------------------------------------------------===//
1975 let Predicates = [UnsafeFPMath] in {
1976 def : RcpPat<V_RCP_F64_e32, f64>;
1977 defm : RsqPat<V_RSQ_F64_e32, f64>;
1978 defm : RsqPat<V_RSQ_F32_e32, f32>;
1981 //===----------------------------------------------------------------------===//
1983 //===----------------------------------------------------------------------===//
1986 (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)),
1987 (V_BCNT_U32_B32_e64 $popcnt, $val)
1990 /********** ======================= **********/
1991 /********** Image sampling patterns **********/
1992 /********** ======================= **********/
1995 class SampleRawPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
1996 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i32:$unorm,
1997 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
1998 (opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da),
1999 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc),
2000 $addr, $rsrc, $sampler)
2003 multiclass SampleRawPatterns<SDPatternOperator name, string opcode> {
2004 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
2005 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
2006 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
2007 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V8), v8i32>;
2008 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V16), v16i32>;
2012 class ImagePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
2013 (name vt:$addr, v8i32:$rsrc, i32:$dmask, i32:$unorm,
2014 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
2015 (opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da),
2016 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc),
2020 multiclass ImagePatterns<SDPatternOperator name, string opcode> {
2021 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
2022 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
2023 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
2027 defm : SampleRawPatterns<int_SI_image_sample, "IMAGE_SAMPLE">;
2028 defm : SampleRawPatterns<int_SI_image_sample_cl, "IMAGE_SAMPLE_CL">;
2029 defm : SampleRawPatterns<int_SI_image_sample_d, "IMAGE_SAMPLE_D">;
2030 defm : SampleRawPatterns<int_SI_image_sample_d_cl, "IMAGE_SAMPLE_D_CL">;
2031 defm : SampleRawPatterns<int_SI_image_sample_l, "IMAGE_SAMPLE_L">;
2032 defm : SampleRawPatterns<int_SI_image_sample_b, "IMAGE_SAMPLE_B">;
2033 defm : SampleRawPatterns<int_SI_image_sample_b_cl, "IMAGE_SAMPLE_B_CL">;
2034 defm : SampleRawPatterns<int_SI_image_sample_lz, "IMAGE_SAMPLE_LZ">;
2035 defm : SampleRawPatterns<int_SI_image_sample_cd, "IMAGE_SAMPLE_CD">;
2036 defm : SampleRawPatterns<int_SI_image_sample_cd_cl, "IMAGE_SAMPLE_CD_CL">;
2038 // Sample with comparison
2039 defm : SampleRawPatterns<int_SI_image_sample_c, "IMAGE_SAMPLE_C">;
2040 defm : SampleRawPatterns<int_SI_image_sample_c_cl, "IMAGE_SAMPLE_C_CL">;
2041 defm : SampleRawPatterns<int_SI_image_sample_c_d, "IMAGE_SAMPLE_C_D">;
2042 defm : SampleRawPatterns<int_SI_image_sample_c_d_cl, "IMAGE_SAMPLE_C_D_CL">;
2043 defm : SampleRawPatterns<int_SI_image_sample_c_l, "IMAGE_SAMPLE_C_L">;
2044 defm : SampleRawPatterns<int_SI_image_sample_c_b, "IMAGE_SAMPLE_C_B">;
2045 defm : SampleRawPatterns<int_SI_image_sample_c_b_cl, "IMAGE_SAMPLE_C_B_CL">;
2046 defm : SampleRawPatterns<int_SI_image_sample_c_lz, "IMAGE_SAMPLE_C_LZ">;
2047 defm : SampleRawPatterns<int_SI_image_sample_c_cd, "IMAGE_SAMPLE_C_CD">;
2048 defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl, "IMAGE_SAMPLE_C_CD_CL">;
2050 // Sample with offsets
2051 defm : SampleRawPatterns<int_SI_image_sample_o, "IMAGE_SAMPLE_O">;
2052 defm : SampleRawPatterns<int_SI_image_sample_cl_o, "IMAGE_SAMPLE_CL_O">;
2053 defm : SampleRawPatterns<int_SI_image_sample_d_o, "IMAGE_SAMPLE_D_O">;
2054 defm : SampleRawPatterns<int_SI_image_sample_d_cl_o, "IMAGE_SAMPLE_D_CL_O">;
2055 defm : SampleRawPatterns<int_SI_image_sample_l_o, "IMAGE_SAMPLE_L_O">;
2056 defm : SampleRawPatterns<int_SI_image_sample_b_o, "IMAGE_SAMPLE_B_O">;
2057 defm : SampleRawPatterns<int_SI_image_sample_b_cl_o, "IMAGE_SAMPLE_B_CL_O">;
2058 defm : SampleRawPatterns<int_SI_image_sample_lz_o, "IMAGE_SAMPLE_LZ_O">;
2059 defm : SampleRawPatterns<int_SI_image_sample_cd_o, "IMAGE_SAMPLE_CD_O">;
2060 defm : SampleRawPatterns<int_SI_image_sample_cd_cl_o, "IMAGE_SAMPLE_CD_CL_O">;
2062 // Sample with comparison and offsets
2063 defm : SampleRawPatterns<int_SI_image_sample_c_o, "IMAGE_SAMPLE_C_O">;
2064 defm : SampleRawPatterns<int_SI_image_sample_c_cl_o, "IMAGE_SAMPLE_C_CL_O">;
2065 defm : SampleRawPatterns<int_SI_image_sample_c_d_o, "IMAGE_SAMPLE_C_D_O">;
2066 defm : SampleRawPatterns<int_SI_image_sample_c_d_cl_o, "IMAGE_SAMPLE_C_D_CL_O">;
2067 defm : SampleRawPatterns<int_SI_image_sample_c_l_o, "IMAGE_SAMPLE_C_L_O">;
2068 defm : SampleRawPatterns<int_SI_image_sample_c_b_o, "IMAGE_SAMPLE_C_B_O">;
2069 defm : SampleRawPatterns<int_SI_image_sample_c_b_cl_o, "IMAGE_SAMPLE_C_B_CL_O">;
2070 defm : SampleRawPatterns<int_SI_image_sample_c_lz_o, "IMAGE_SAMPLE_C_LZ_O">;
2071 defm : SampleRawPatterns<int_SI_image_sample_c_cd_o, "IMAGE_SAMPLE_C_CD_O">;
2072 defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl_o, "IMAGE_SAMPLE_C_CD_CL_O">;
2075 // Only the variants which make sense are defined.
2076 def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V2, v2i32>;
2077 def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V4, v4i32>;
2078 def : SampleRawPattern<int_SI_gather4_cl, IMAGE_GATHER4_CL_V4_V4, v4i32>;
2079 def : SampleRawPattern<int_SI_gather4_l, IMAGE_GATHER4_L_V4_V4, v4i32>;
2080 def : SampleRawPattern<int_SI_gather4_b, IMAGE_GATHER4_B_V4_V4, v4i32>;
2081 def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V4, v4i32>;
2082 def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V8, v8i32>;
2083 def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V2, v2i32>;
2084 def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V4, v4i32>;
2086 def : SampleRawPattern<int_SI_gather4_c, IMAGE_GATHER4_C_V4_V4, v4i32>;
2087 def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V4, v4i32>;
2088 def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V8, v8i32>;
2089 def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V4, v4i32>;
2090 def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V8, v8i32>;
2091 def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V4, v4i32>;
2092 def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V8, v8i32>;
2093 def : SampleRawPattern<int_SI_gather4_c_b_cl, IMAGE_GATHER4_C_B_CL_V4_V8, v8i32>;
2094 def : SampleRawPattern<int_SI_gather4_c_lz, IMAGE_GATHER4_C_LZ_V4_V4, v4i32>;
2096 def : SampleRawPattern<int_SI_gather4_o, IMAGE_GATHER4_O_V4_V4, v4i32>;
2097 def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V4, v4i32>;
2098 def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V8, v8i32>;
2099 def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V4, v4i32>;
2100 def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V8, v8i32>;
2101 def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V4, v4i32>;
2102 def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V8, v8i32>;
2103 def : SampleRawPattern<int_SI_gather4_b_cl_o, IMAGE_GATHER4_B_CL_O_V4_V8, v8i32>;
2104 def : SampleRawPattern<int_SI_gather4_lz_o, IMAGE_GATHER4_LZ_O_V4_V4, v4i32>;
2106 def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V4, v4i32>;
2107 def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V8, v8i32>;
2108 def : SampleRawPattern<int_SI_gather4_c_cl_o, IMAGE_GATHER4_C_CL_O_V4_V8, v8i32>;
2109 def : SampleRawPattern<int_SI_gather4_c_l_o, IMAGE_GATHER4_C_L_O_V4_V8, v8i32>;
2110 def : SampleRawPattern<int_SI_gather4_c_b_o, IMAGE_GATHER4_C_B_O_V4_V8, v8i32>;
2111 def : SampleRawPattern<int_SI_gather4_c_b_cl_o, IMAGE_GATHER4_C_B_CL_O_V4_V8, v8i32>;
2112 def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V4, v4i32>;
2113 def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V8, v8i32>;
2115 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V1, i32>;
2116 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V2, v2i32>;
2117 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V4, v4i32>;
2119 def : ImagePattern<int_SI_getresinfo, IMAGE_GET_RESINFO_V4_V1, i32>;
2120 defm : ImagePatterns<int_SI_image_load, "IMAGE_LOAD">;
2121 defm : ImagePatterns<int_SI_image_load_mip, "IMAGE_LOAD_MIP">;
2123 /* SIsample for simple 1D texture lookup */
2125 (SIsample i32:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
2126 (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2129 class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
2130 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
2131 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2134 class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
2135 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_RECT),
2136 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2139 class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
2140 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_ARRAY),
2141 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2144 class SampleShadowPattern<SDNode name, MIMG opcode,
2145 ValueType vt> : Pat <
2146 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW),
2147 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2150 class SampleShadowArrayPattern<SDNode name, MIMG opcode,
2151 ValueType vt> : Pat <
2152 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
2153 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2156 /* SIsample* for texture lookups consuming more address parameters */
2157 multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l,
2158 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b,
2159 MIMG sample_d, MIMG sample_c_d, ValueType addr_type> {
2160 def : SamplePattern <SIsample, sample, addr_type>;
2161 def : SampleRectPattern <SIsample, sample, addr_type>;
2162 def : SampleArrayPattern <SIsample, sample, addr_type>;
2163 def : SampleShadowPattern <SIsample, sample_c, addr_type>;
2164 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>;
2166 def : SamplePattern <SIsamplel, sample_l, addr_type>;
2167 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>;
2168 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>;
2169 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>;
2171 def : SamplePattern <SIsampleb, sample_b, addr_type>;
2172 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>;
2173 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>;
2174 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>;
2176 def : SamplePattern <SIsampled, sample_d, addr_type>;
2177 def : SampleArrayPattern <SIsampled, sample_d, addr_type>;
2178 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>;
2179 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>;
2182 defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2,
2183 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2,
2184 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2,
2185 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2,
2187 defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4,
2188 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4,
2189 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4,
2190 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4,
2192 defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8,
2193 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8,
2194 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8,
2195 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8,
2197 defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16,
2198 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16,
2199 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16,
2200 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16,
2203 /* int_SI_imageload for texture fetches consuming varying address parameters */
2204 class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2205 (name addr_type:$addr, v32i8:$rsrc, imm),
2206 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
2209 class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2210 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY),
2211 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
2214 class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2215 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA),
2216 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
2219 class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2220 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA),
2221 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
2224 multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> {
2225 def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>;
2226 def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>;
2229 multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> {
2230 def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>;
2231 def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>;
2234 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V2, v2i32>;
2235 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V4, v4i32>;
2237 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V2, v2i32>;
2238 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V4, v4i32>;
2240 /* Image resource information */
2242 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm),
2243 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
2247 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY),
2248 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
2252 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA),
2253 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
2256 /********** ============================================ **********/
2257 /********** Extraction, Insertion, Building and Casting **********/
2258 /********** ============================================ **********/
2260 foreach Index = 0-2 in {
2261 def Extract_Element_v2i32_#Index : Extract_Element <
2262 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
2264 def Insert_Element_v2i32_#Index : Insert_Element <
2265 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
2268 def Extract_Element_v2f32_#Index : Extract_Element <
2269 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
2271 def Insert_Element_v2f32_#Index : Insert_Element <
2272 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
2276 foreach Index = 0-3 in {
2277 def Extract_Element_v4i32_#Index : Extract_Element <
2278 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
2280 def Insert_Element_v4i32_#Index : Insert_Element <
2281 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
2284 def Extract_Element_v4f32_#Index : Extract_Element <
2285 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
2287 def Insert_Element_v4f32_#Index : Insert_Element <
2288 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
2292 foreach Index = 0-7 in {
2293 def Extract_Element_v8i32_#Index : Extract_Element <
2294 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
2296 def Insert_Element_v8i32_#Index : Insert_Element <
2297 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
2300 def Extract_Element_v8f32_#Index : Extract_Element <
2301 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
2303 def Insert_Element_v8f32_#Index : Insert_Element <
2304 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
2308 foreach Index = 0-15 in {
2309 def Extract_Element_v16i32_#Index : Extract_Element <
2310 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
2312 def Insert_Element_v16i32_#Index : Insert_Element <
2313 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
2316 def Extract_Element_v16f32_#Index : Extract_Element <
2317 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
2319 def Insert_Element_v16f32_#Index : Insert_Element <
2320 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
2324 def : BitConvert <i32, f32, SReg_32>;
2325 def : BitConvert <i32, f32, VReg_32>;
2327 def : BitConvert <f32, i32, SReg_32>;
2328 def : BitConvert <f32, i32, VReg_32>;
2330 def : BitConvert <i64, f64, VReg_64>;
2332 def : BitConvert <f64, i64, VReg_64>;
2334 def : BitConvert <v2f32, v2i32, VReg_64>;
2335 def : BitConvert <v2i32, v2f32, VReg_64>;
2336 def : BitConvert <v2i32, i64, VReg_64>;
2337 def : BitConvert <i64, v2i32, VReg_64>;
2338 def : BitConvert <v2f32, i64, VReg_64>;
2339 def : BitConvert <i64, v2f32, VReg_64>;
2340 def : BitConvert <v2i32, f64, VReg_64>;
2341 def : BitConvert <f64, v2i32, VReg_64>;
2342 def : BitConvert <v4f32, v4i32, VReg_128>;
2343 def : BitConvert <v4i32, v4f32, VReg_128>;
2345 def : BitConvert <v8f32, v8i32, SReg_256>;
2346 def : BitConvert <v8i32, v8f32, SReg_256>;
2347 def : BitConvert <v8i32, v32i8, SReg_256>;
2348 def : BitConvert <v32i8, v8i32, SReg_256>;
2349 def : BitConvert <v8i32, v32i8, VReg_256>;
2350 def : BitConvert <v8i32, v8f32, VReg_256>;
2351 def : BitConvert <v8f32, v8i32, VReg_256>;
2352 def : BitConvert <v32i8, v8i32, VReg_256>;
2354 def : BitConvert <v16i32, v16f32, VReg_512>;
2355 def : BitConvert <v16f32, v16i32, VReg_512>;
2357 /********** =================== **********/
2358 /********** Src & Dst modifiers **********/
2359 /********** =================== **********/
2361 def FCLAMP_SI : AMDGPUShaderInst <
2362 (outs VReg_32:$dst),
2363 (ins VSrc_32:$src0),
2364 "FCLAMP_SI $dst, $src0",
2367 let usesCustomInserter = 1;
2371 (AMDGPUclamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)),
2372 (FCLAMP_SI f32:$src)
2375 /********** ================================ **********/
2376 /********** Floating point absolute/negative **********/
2377 /********** ================================ **********/
2379 // Prevent expanding both fneg and fabs.
2381 // FIXME: Should use S_OR_B32
2383 (fneg (fabs f32:$src)),
2384 (V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
2387 // FIXME: Should use S_OR_B32
2389 (fneg (fabs f64:$src)),
2391 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2392 (i32 (EXTRACT_SUBREG f64:$src, sub0)), sub0),
2393 (V_OR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
2394 (V_MOV_B32_e32 0x80000000)), sub1)) // Set sign bit.
2399 (V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff))
2404 (V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000))
2410 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2411 (i32 (EXTRACT_SUBREG f64:$src, sub0)), sub0),
2412 (V_AND_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
2413 (V_MOV_B32_e32 0x7fffffff)), sub1)) // Set sign bit.
2419 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2420 (i32 (EXTRACT_SUBREG f64:$src, sub0)), sub0),
2421 (V_XOR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
2422 (V_MOV_B32_e32 0x80000000)), sub1))
2425 /********** ================== **********/
2426 /********** Immediate Patterns **********/
2427 /********** ================== **********/
2430 (SGPRImm<(i32 imm)>:$imm),
2431 (S_MOV_B32 imm:$imm)
2435 (SGPRImm<(f32 fpimm)>:$imm),
2436 (S_MOV_B32 fpimm:$imm)
2441 (V_MOV_B32_e32 imm:$imm)
2446 (V_MOV_B32_e32 fpimm:$imm)
2450 (i64 InlineImm<i64>:$imm),
2451 (S_MOV_B64 InlineImm<i64>:$imm)
2454 /********** ===================== **********/
2455 /********** Interpolation Paterns **********/
2456 /********** ===================== **********/
2459 (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params),
2460 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, $params)
2464 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, v2i32:$ij),
2465 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0),
2466 imm:$attr_chan, imm:$attr, i32:$params),
2467 (EXTRACT_SUBREG $ij, sub1),
2468 imm:$attr_chan, imm:$attr, $params)
2471 /********** ================== **********/
2472 /********** Intrinsic Patterns **********/
2473 /********** ================== **********/
2475 /* llvm.AMDGPU.pow */
2476 def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>;
2479 (int_AMDGPU_div f32:$src0, f32:$src1),
2480 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1))
2484 (fdiv f64:$src0, f64:$src1),
2485 (V_MUL_F64 0 /* src0_modifiers */, $src0,
2486 0 /* src1_modifiers */, (V_RCP_F64_e32 $src1),
2487 0 /* clamp */, 0 /* omod */)
2491 (int_AMDGPU_cube v4f32:$src),
2492 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2493 (V_CUBETC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
2494 0 /* src1_modifiers */, (EXTRACT_SUBREG $src, sub1),
2495 0 /* src2_modifiers */, (EXTRACT_SUBREG $src, sub2),
2496 0 /* clamp */, 0 /* omod */),
2498 (V_CUBESC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
2499 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2500 0 /* src2_modifiers */,(EXTRACT_SUBREG $src, sub2),
2501 0 /* clamp */, 0 /* omod */),
2503 (V_CUBEMA_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0),
2504 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2505 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2),
2506 0 /* clamp */, 0 /* omod */),
2508 (V_CUBEID_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0),
2509 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2510 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2),
2511 0 /* clamp */, 0 /* omod */),
2516 (i32 (sext i1:$src0)),
2517 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
2520 class Ext32Pat <SDNode ext> : Pat <
2521 (i32 (ext i1:$src0)),
2522 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0)
2525 def : Ext32Pat <zext>;
2526 def : Ext32Pat <anyext>;
2528 // Offset in an 32Bit VGPR
2530 (SIload_constant v4i32:$sbase, i32:$voff),
2531 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0, 0)
2534 // The multiplication scales from [0,1] to the unsigned integer range
2536 (AMDGPUurecip i32:$src0),
2538 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1,
2539 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
2544 (V_MBCNT_HI_U32_B32_e32 0xffffffff,
2545 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0))
2548 //===----------------------------------------------------------------------===//
2550 //===----------------------------------------------------------------------===//
2552 def : IMad24Pat<V_MAD_I32_I24>;
2553 def : UMad24Pat<V_MAD_U32_U24>;
2556 (mulhu i32:$src0, i32:$src1),
2557 (V_MUL_HI_U32 $src0, $src1)
2561 (mulhs i32:$src0, i32:$src1),
2562 (V_MUL_HI_I32 $src0, $src1)
2565 def : Vop3ModPat<V_MAD_F32, VOP_F32_F32_F32_F32, AMDGPUmad>;
2568 defm : BFIPatterns <V_BFI_B32, S_MOV_B32>;
2569 def : ROTRPattern <V_ALIGNBIT_B32>;
2571 /********** ======================= **********/
2572 /********** Load/Store Patterns **********/
2573 /********** ======================= **********/
2575 class DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat <
2576 (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
2577 (inst (i1 0), $ptr, (as_i16imm $offset))
2580 def : DSReadPat <DS_READ_I8, i32, sextloadi8_local>;
2581 def : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>;
2582 def : DSReadPat <DS_READ_I16, i32, sextloadi16_local>;
2583 def : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>;
2584 def : DSReadPat <DS_READ_B32, i32, local_load>;
2586 let AddedComplexity = 100 in {
2588 def : DSReadPat <DS_READ_B64, v2i32, local_load_aligned8bytes>;
2590 } // End AddedComplexity = 100
2593 (v2i32 (local_load (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
2595 (DS_READ2_B32 (i1 0), $ptr, $offset0, $offset1)
2598 class DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat <
2599 (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
2600 (inst (i1 0), $ptr, $value, (as_i16imm $offset))
2603 def : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>;
2604 def : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>;
2605 def : DSWritePat <DS_WRITE_B32, i32, local_store>;
2607 let AddedComplexity = 100 in {
2609 def : DSWritePat <DS_WRITE_B64, v2i32, local_store_aligned8bytes>;
2610 } // End AddedComplexity = 100
2613 (local_store v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
2615 (DS_WRITE2_B32 (i1 0), $ptr, (EXTRACT_SUBREG $value, sub0),
2616 (EXTRACT_SUBREG $value, sub1), $offset0, $offset1)
2619 class DSAtomicRetPat<DS inst, ValueType vt, PatFrag frag> : Pat <
2620 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
2621 (inst (i1 0), $ptr, $value, (as_i16imm $offset))
2624 // Special case of DSAtomicRetPat for add / sub 1 -> inc / dec
2626 // We need to use something for the data0, so we set a register to
2627 // -1. For the non-rtn variants, the manual says it does
2628 // DS[A] = (DS[A] >= D0) ? 0 : DS[A] + 1, and setting D0 to uint_max
2629 // will always do the increment so I'm assuming it's the same.
2631 // We also load this -1 with s_mov_b32 / s_mov_b64 even though this
2632 // needs to be a VGPR. The SGPR copy pass will fix this, and it's
2633 // easier since there is no v_mov_b64.
2634 class DSAtomicIncRetPat<DS inst, ValueType vt,
2635 Instruction LoadImm, PatFrag frag> : Pat <
2636 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), (vt 1)),
2637 (inst (i1 0), $ptr, (LoadImm (vt -1)), (as_i16imm $offset))
2641 class DSAtomicCmpXChg <DS inst, ValueType vt, PatFrag frag> : Pat <
2642 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
2643 (inst (i1 0), $ptr, $cmp, $swap, (as_i16imm $offset))
2648 def : DSAtomicIncRetPat<DS_INC_RTN_U32, i32,
2649 S_MOV_B32, atomic_load_add_local>;
2650 def : DSAtomicIncRetPat<DS_DEC_RTN_U32, i32,
2651 S_MOV_B32, atomic_load_sub_local>;
2653 def : DSAtomicRetPat<DS_WRXCHG_RTN_B32, i32, atomic_swap_local>;
2654 def : DSAtomicRetPat<DS_ADD_RTN_U32, i32, atomic_load_add_local>;
2655 def : DSAtomicRetPat<DS_SUB_RTN_U32, i32, atomic_load_sub_local>;
2656 def : DSAtomicRetPat<DS_AND_RTN_B32, i32, atomic_load_and_local>;
2657 def : DSAtomicRetPat<DS_OR_RTN_B32, i32, atomic_load_or_local>;
2658 def : DSAtomicRetPat<DS_XOR_RTN_B32, i32, atomic_load_xor_local>;
2659 def : DSAtomicRetPat<DS_MIN_RTN_I32, i32, atomic_load_min_local>;
2660 def : DSAtomicRetPat<DS_MAX_RTN_I32, i32, atomic_load_max_local>;
2661 def : DSAtomicRetPat<DS_MIN_RTN_U32, i32, atomic_load_umin_local>;
2662 def : DSAtomicRetPat<DS_MAX_RTN_U32, i32, atomic_load_umax_local>;
2664 def : DSAtomicCmpXChg<DS_CMPST_RTN_B32, i32, atomic_cmp_swap_32_local>;
2667 def : DSAtomicIncRetPat<DS_INC_RTN_U64, i64,
2668 S_MOV_B64, atomic_load_add_local>;
2669 def : DSAtomicIncRetPat<DS_DEC_RTN_U64, i64,
2670 S_MOV_B64, atomic_load_sub_local>;
2672 def : DSAtomicRetPat<DS_WRXCHG_RTN_B64, i64, atomic_swap_local>;
2673 def : DSAtomicRetPat<DS_ADD_RTN_U64, i64, atomic_load_add_local>;
2674 def : DSAtomicRetPat<DS_SUB_RTN_U64, i64, atomic_load_sub_local>;
2675 def : DSAtomicRetPat<DS_AND_RTN_B64, i64, atomic_load_and_local>;
2676 def : DSAtomicRetPat<DS_OR_RTN_B64, i64, atomic_load_or_local>;
2677 def : DSAtomicRetPat<DS_XOR_RTN_B64, i64, atomic_load_xor_local>;
2678 def : DSAtomicRetPat<DS_MIN_RTN_I64, i64, atomic_load_min_local>;
2679 def : DSAtomicRetPat<DS_MAX_RTN_I64, i64, atomic_load_max_local>;
2680 def : DSAtomicRetPat<DS_MIN_RTN_U64, i64, atomic_load_umin_local>;
2681 def : DSAtomicRetPat<DS_MAX_RTN_U64, i64, atomic_load_umax_local>;
2683 def : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, atomic_cmp_swap_64_local>;
2686 //===----------------------------------------------------------------------===//
2688 //===----------------------------------------------------------------------===//
2690 multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
2691 PatFrag constant_ld> {
2693 (vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))),
2694 (Instr_ADDR64 $srsrc, $vaddr, $offset)
2698 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, sextloadi8_constant>;
2699 defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, az_extloadi8_constant>;
2700 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_constant>;
2701 defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, az_extloadi16_constant>;
2702 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32, constant_load>;
2703 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32, constant_load>;
2704 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32, constant_load>;
2706 class MUBUFScratchLoadPat <MUBUF Instr, ValueType vt, PatFrag ld> : Pat <
2707 (vt (ld (MUBUFScratch v4i32:$srsrc, i32:$vaddr,
2708 i32:$soffset, u16imm:$offset))),
2709 (Instr $srsrc, $vaddr, $soffset, $offset, 0, 0, 0)
2712 def : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, i32, sextloadi8_private>;
2713 def : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, i32, extloadi8_private>;
2714 def : MUBUFScratchLoadPat <BUFFER_LOAD_SSHORT_OFFEN, i32, sextloadi16_private>;
2715 def : MUBUFScratchLoadPat <BUFFER_LOAD_USHORT_OFFEN, i32, extloadi16_private>;
2716 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORD_OFFEN, i32, load_private>;
2717 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX2_OFFEN, v2i32, load_private>;
2718 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX4_OFFEN, v4i32, load_private>;
2720 // BUFFER_LOAD_DWORD*, addr64=0
2721 multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen,
2725 (vt (int_SI_buffer_load_dword v4i32:$rsrc, (i32 imm), i32:$soffset,
2726 imm:$offset, 0, 0, imm:$glc, imm:$slc,
2728 (offset $rsrc, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2729 (as_i1imm $slc), (as_i1imm $tfe))
2733 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2734 imm:$offset, 1, 0, imm:$glc, imm:$slc,
2736 (offen $rsrc, $vaddr, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc),
2741 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2742 imm:$offset, 0, 1, imm:$glc, imm:$slc,
2744 (idxen $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2745 (as_i1imm $slc), (as_i1imm $tfe))
2749 (vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset,
2750 imm, 1, 1, imm:$glc, imm:$slc,
2752 (bothen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
2757 defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN,
2758 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
2759 defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN,
2760 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>;
2761 defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN,
2762 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
2764 class MUBUFScratchStorePat <MUBUF Instr, ValueType vt, PatFrag st> : Pat <
2765 (st vt:$value, (MUBUFScratch v4i32:$srsrc, i32:$vaddr, i32:$soffset,
2767 (Instr $value, $srsrc, $vaddr, $soffset, $offset, 0, 0, 0)
2770 def : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, i32, truncstorei8_private>;
2771 def : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, i32, truncstorei16_private>;
2772 def : MUBUFScratchStorePat <BUFFER_STORE_DWORD_OFFEN, i32, store_private>;
2773 def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX2_OFFEN, v2i32, store_private>;
2774 def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, v4i32, store_private>;
2777 class MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> : Pat <
2778 (st vt:$value, (MUBUFScratch v4i32:$srsrc, i64:$vaddr, u16imm:$offset)),
2779 (Instr $value, $srsrc, $vaddr, $offset)
2782 def : MUBUFStore_Pattern <BUFFER_STORE_BYTE_ADDR64, i32, truncstorei8_private>;
2783 def : MUBUFStore_Pattern <BUFFER_STORE_SHORT_ADDR64, i32, truncstorei16_private>;
2784 def : MUBUFStore_Pattern <BUFFER_STORE_DWORD_ADDR64, i32, store_private>;
2785 def : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2_ADDR64, v2i32, store_private>;
2786 def : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4_ADDR64, v4i32, store_private>;
2790 //===----------------------------------------------------------------------===//
2792 //===----------------------------------------------------------------------===//
2794 // TBUFFER_STORE_FORMAT_*, addr64=0
2795 class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat<
2796 (SItbuffer_store v4i32:$rsrc, vt:$vdata, num_channels, i32:$vaddr,
2797 i32:$soffset, imm:$inst_offset, imm:$dfmt,
2798 imm:$nfmt, imm:$offen, imm:$idxen,
2799 imm:$glc, imm:$slc, imm:$tfe),
2801 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen),
2802 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc,
2803 (as_i1imm $slc), (as_i1imm $tfe), $soffset)
2806 def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>;
2807 def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>;
2808 def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>;
2809 def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>;
2811 let SubtargetPredicate = isCI in {
2813 // Sea island new arithmetic instructinos
2814 defm V_TRUNC_F64 : VOP1Inst <vop1<0x17>, "V_TRUNC_F64",
2817 defm V_CEIL_F64 : VOP1Inst <vop1<0x18>, "V_CEIL_F64",
2820 defm V_FLOOR_F64 : VOP1Inst <vop1<0x1A>, "V_FLOOR_F64",
2823 defm V_RNDNE_F64 : VOP1Inst <vop1<0x19>, "V_RNDNE_F64",
2827 defm V_QSAD_PK_U16_U8 : VOP3Inst <vop3<0x173>, "V_QSAD_PK_U16_U8",
2830 defm V_MQSAD_U16_U8 : VOP3Inst <vop3<0x172>, "V_MQSAD_U16_U8",
2833 defm V_MQSAD_U32_U8 : VOP3Inst <vop3<0x175>, "V_MQSAD_U32_U8",
2836 defm V_MAD_U64_U32 : VOP3Inst <vop3<0x176>, "V_MAD_U64_U32",
2840 // XXX - Does this set VCC?
2841 defm V_MAD_I64_I32 : VOP3Inst <vop3<0x177>, "V_MAD_I64_I32",
2845 // Remaining instructions:
2847 // S_CBRANCH_CDBGUSER
2848 // S_CBRANCH_CDBGSYS
2849 // S_CBRANCH_CDBGSYS_OR_USER
2850 // S_CBRANCH_CDBGSYS_AND_USER
2855 // DS_GWS_SEMA_RELEASE_ALL
2857 // DS_CNDXCHG32_RTN_B64
2860 // DS_CONDXCHG32_RTN_B128
2863 // BUFFER_LOAD_DWORDX3
2864 // BUFFER_STORE_DWORDX3
2868 //===----------------------------------------------------------------------===//
2870 //===----------------------------------------------------------------------===//
2872 class FLATLoad_Pattern <FLAT Instr_ADDR64, ValueType vt,
2874 Pat <(vt (flat_ld i64:$ptr)),
2878 def : FLATLoad_Pattern <FLAT_LOAD_SBYTE, i32, sextloadi8_flat>;
2879 def : FLATLoad_Pattern <FLAT_LOAD_UBYTE, i32, az_extloadi8_flat>;
2880 def : FLATLoad_Pattern <FLAT_LOAD_SSHORT, i32, sextloadi16_flat>;
2881 def : FLATLoad_Pattern <FLAT_LOAD_USHORT, i32, az_extloadi16_flat>;
2882 def : FLATLoad_Pattern <FLAT_LOAD_DWORD, i32, flat_load>;
2883 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX2, i64, flat_load>;
2884 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX2, i64, az_extloadi32_flat>;
2885 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX2, v2i32, flat_load>;
2886 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX4, v4i32, flat_load>;
2888 class FLATStore_Pattern <FLAT Instr, ValueType vt, PatFrag st> :
2889 Pat <(st vt:$value, i64:$ptr),
2890 (Instr $value, $ptr)
2893 def : FLATStore_Pattern <FLAT_STORE_BYTE, i32, truncstorei8_flat>;
2894 def : FLATStore_Pattern <FLAT_STORE_SHORT, i32, truncstorei16_flat>;
2895 def : FLATStore_Pattern <FLAT_STORE_DWORD, i32, flat_store>;
2896 def : FLATStore_Pattern <FLAT_STORE_DWORDX2, i64, flat_store>;
2897 def : FLATStore_Pattern <FLAT_STORE_DWORDX2, v2i32, flat_store>;
2898 def : FLATStore_Pattern <FLAT_STORE_DWORDX4, v4i32, flat_store>;
2900 /********** ====================== **********/
2901 /********** Indirect adressing **********/
2902 /********** ====================== **********/
2904 multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, SI_INDIRECT_DST IndDst> {
2906 // 1. Extract with offset
2908 (vector_extract vt:$vec, (add i32:$idx, imm:$off)),
2909 (eltvt (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off))
2912 // 2. Extract without offset
2914 (vector_extract vt:$vec, i32:$idx),
2915 (eltvt (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0))
2918 // 3. Insert with offset
2920 (vector_insert vt:$vec, eltvt:$val, (add i32:$idx, imm:$off)),
2921 (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val)
2924 // 4. Insert without offset
2926 (vector_insert vt:$vec, eltvt:$val, i32:$idx),
2927 (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val)
2931 defm : SI_INDIRECT_Pattern <v2f32, f32, SI_INDIRECT_DST_V2>;
2932 defm : SI_INDIRECT_Pattern <v4f32, f32, SI_INDIRECT_DST_V4>;
2933 defm : SI_INDIRECT_Pattern <v8f32, f32, SI_INDIRECT_DST_V8>;
2934 defm : SI_INDIRECT_Pattern <v16f32, f32, SI_INDIRECT_DST_V16>;
2936 defm : SI_INDIRECT_Pattern <v2i32, i32, SI_INDIRECT_DST_V2>;
2937 defm : SI_INDIRECT_Pattern <v4i32, i32, SI_INDIRECT_DST_V4>;
2938 defm : SI_INDIRECT_Pattern <v8i32, i32, SI_INDIRECT_DST_V8>;
2939 defm : SI_INDIRECT_Pattern <v16i32, i32, SI_INDIRECT_DST_V16>;
2941 //===----------------------------------------------------------------------===//
2942 // Conversion Patterns
2943 //===----------------------------------------------------------------------===//
2945 def : Pat<(i32 (sext_inreg i32:$src, i1)),
2946 (S_BFE_I32 i32:$src, 65536)>; // 0 | 1 << 16
2948 // TODO: Match 64-bit BFE. SI has a 64-bit BFE, but it's scalar only so it
2949 // might not be worth the effort, and will need to expand to shifts when
2950 // fixing SGPR copies.
2952 // Handle sext_inreg in i64
2954 (i64 (sext_inreg i64:$src, i1)),
2955 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2956 (S_BFE_I32 (EXTRACT_SUBREG i64:$src, sub0), 65536), sub0), // 0 | 1 << 16
2957 (S_MOV_B32 -1), sub1)
2961 (i64 (sext_inreg i64:$src, i8)),
2962 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2963 (S_SEXT_I32_I8 (EXTRACT_SUBREG i64:$src, sub0)), sub0),
2964 (S_MOV_B32 -1), sub1)
2968 (i64 (sext_inreg i64:$src, i16)),
2969 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2970 (S_SEXT_I32_I16 (EXTRACT_SUBREG i64:$src, sub0)), sub0),
2971 (S_MOV_B32 -1), sub1)
2974 class ZExt_i64_i32_Pat <SDNode ext> : Pat <
2975 (i64 (ext i32:$src)),
2976 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $src, sub0),
2977 (S_MOV_B32 0), sub1)
2980 class ZExt_i64_i1_Pat <SDNode ext> : Pat <
2981 (i64 (ext i1:$src)),
2983 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2984 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src), sub0),
2985 (S_MOV_B32 0), sub1)
2989 def : ZExt_i64_i32_Pat<zext>;
2990 def : ZExt_i64_i32_Pat<anyext>;
2991 def : ZExt_i64_i1_Pat<zext>;
2992 def : ZExt_i64_i1_Pat<anyext>;
2995 (i64 (sext i32:$src)),
2997 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $src, sub0),
2998 (S_ASHR_I32 $src, 31), sub1)
3002 (i64 (sext i1:$src)),
3005 (i64 (IMPLICIT_DEF)),
3006 (V_CNDMASK_B32_e64 0, -1, $src), sub0),
3007 (V_CNDMASK_B32_e64 0, -1, $src), sub1)
3011 (f32 (sint_to_fp i1:$src)),
3012 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_NEG_ONE, $src)
3016 (f32 (uint_to_fp i1:$src)),
3017 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_ONE, $src)
3021 (f64 (sint_to_fp i1:$src)),
3022 (V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src))
3026 (f64 (uint_to_fp i1:$src)),
3027 (V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src))
3030 //===----------------------------------------------------------------------===//
3031 // Miscellaneous Patterns
3032 //===----------------------------------------------------------------------===//
3035 (i32 (trunc i64:$a)),
3036 (EXTRACT_SUBREG $a, sub0)
3040 (i1 (trunc i32:$a)),
3041 (V_CMP_EQ_I32_e64 (V_AND_B32_e64 (i32 1), $a), 1)
3044 //============================================================================//
3045 // Miscellaneous Optimization Patterns
3046 //============================================================================//
3048 def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e64>;
3050 } // End isSI predicate