1 //===-- SIInstructions.td - SI Instruction Defintions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This file was originally auto-generated from a GPU register header file and
10 // all the instruction definitions were originally commented out. Instructions
11 // that are not yet supported remain commented out.
12 //===----------------------------------------------------------------------===//
19 def INTERP : InterpSlots;
21 def InterpSlot : Operand<i32> {
22 let PrintMethod = "printInterpSlot";
25 def SendMsgImm : Operand<i32> {
26 let PrintMethod = "printSendMsg";
29 def isSI : Predicate<"Subtarget.getGeneration() "
30 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">;
32 def isCI : Predicate<"Subtarget.getGeneration() "
33 ">= AMDGPUSubtarget::SEA_ISLANDS">;
35 def isCFDepth0 : Predicate<"isCFDepth0()">;
37 def WAIT_FLAG : InstFlag<"printWaitFlag">;
39 let SubtargetPredicate = isSI in {
40 let OtherPredicates = [isCFDepth0] in {
42 //===----------------------------------------------------------------------===//
44 //===----------------------------------------------------------------------===//
48 // We are using the SGPR_32 and not the SReg_32 register class for 32-bit
49 // SMRD instructions, because the SGPR_32 register class does not include M0
50 // and writing to M0 from an SMRD instruction will hang the GPU.
51 defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SGPR_32>;
52 defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>;
53 defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>;
54 defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>;
55 defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>;
57 defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
58 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SGPR_32
61 defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
62 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64
65 defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper <
66 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128
69 defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <
70 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256
73 defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
74 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512
79 //def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>;
80 //def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>;
82 //===----------------------------------------------------------------------===//
84 //===----------------------------------------------------------------------===//
86 let isMoveImm = 1 in {
87 def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>;
88 def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>;
89 def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>;
90 def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>;
91 } // End isMoveImm = 1
93 def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32",
94 [(set i32:$dst, (not i32:$src0))]
97 def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64",
98 [(set i64:$dst, (not i64:$src0))]
100 def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>;
101 def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>;
102 def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32",
103 [(set i32:$dst, (AMDGPUbrev i32:$src0))]
105 def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>;
107 ////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>;
108 ////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>;
109 def S_BCNT1_I32_B32 : SOP1_32 <0x0000000f, "S_BCNT1_I32_B32",
110 [(set i32:$dst, (ctpop i32:$src0))]
112 def S_BCNT1_I32_B64 : SOP1_32_64 <0x00000010, "S_BCNT1_I32_B64", []>;
114 ////def S_FF0_I32_B32 : SOP1_32 <0x00000011, "S_FF0_I32_B32", []>;
115 ////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>;
116 def S_FF1_I32_B32 : SOP1_32 <0x00000013, "S_FF1_I32_B32",
117 [(set i32:$dst, (cttz_zero_undef i32:$src0))]
119 ////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>;
121 def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32",
122 [(set i32:$dst, (ctlz_zero_undef i32:$src0))]
125 //def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>;
126 def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>;
127 //def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>;
128 def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8",
129 [(set i32:$dst, (sext_inreg i32:$src0, i8))]
131 def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16",
132 [(set i32:$dst, (sext_inreg i32:$src0, i16))]
135 ////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>;
136 ////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>;
137 ////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>;
138 ////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>;
139 def S_GETPC_B64 : SOP1 <
140 0x0000001f, (outs SReg_64:$dst), (ins), "S_GETPC_B64 $dst", []
144 def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>;
145 def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>;
146 def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>;
148 let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in {
150 def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>;
151 def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>;
152 def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>;
153 def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>;
154 def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>;
155 def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>;
156 def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>;
157 def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>;
159 } // End hasSideEffects = 1
161 def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>;
162 def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>;
163 def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>;
164 def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>;
165 def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>;
166 def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>;
167 //def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>;
168 def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>;
169 def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>;
170 def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>;
172 //===----------------------------------------------------------------------===//
174 //===----------------------------------------------------------------------===//
176 let Defs = [SCC] in { // Carry out goes to SCC
177 let isCommutable = 1 in {
178 def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>;
179 def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32",
180 [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))]
182 } // End isCommutable = 1
184 def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>;
185 def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32",
186 [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))]
189 let Uses = [SCC] in { // Carry in comes from SCC
190 let isCommutable = 1 in {
191 def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32",
192 [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
193 } // End isCommutable = 1
195 def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32",
196 [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
197 } // End Uses = [SCC]
198 } // End Defs = [SCC]
200 def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32",
201 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]
203 def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32",
204 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]
206 def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32",
207 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]
209 def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32",
210 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]
213 def S_CSELECT_B32 : SOP2 <
214 0x0000000a, (outs SReg_32:$dst),
215 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32",
219 def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>;
221 def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32",
222 [(set i32:$dst, (and i32:$src0, i32:$src1))]
225 def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64",
226 [(set i64:$dst, (and i64:$src0, i64:$src1))]
229 def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32",
230 [(set i32:$dst, (or i32:$src0, i32:$src1))]
233 def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64",
234 [(set i64:$dst, (or i64:$src0, i64:$src1))]
237 def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32",
238 [(set i32:$dst, (xor i32:$src0, i32:$src1))]
241 def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64",
242 [(set i64:$dst, (xor i64:$src0, i64:$src1))]
244 def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>;
245 def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>;
246 def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>;
247 def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>;
248 def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>;
249 def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>;
250 def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>;
251 def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>;
252 def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>;
253 def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>;
255 // Use added complexity so these patterns are preferred to the VALU patterns.
256 let AddedComplexity = 1 in {
258 def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32",
259 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
261 def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "S_LSHL_B64",
262 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
264 def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32",
265 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
267 def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "S_LSHR_B64",
268 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
270 def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32",
271 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
273 def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64",
274 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
277 } // End AddedComplexity = 1
279 def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>;
280 def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>;
281 def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>;
282 def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>;
283 def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>;
284 def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>;
285 def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>;
286 //def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>;
287 def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>;
289 //===----------------------------------------------------------------------===//
291 //===----------------------------------------------------------------------===//
293 def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32">;
294 def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32">;
295 def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32">;
296 def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32">;
297 def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32">;
298 def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32">;
299 def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32">;
300 def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32">;
301 def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32">;
302 def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32">;
303 def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32">;
304 def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32">;
305 ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>;
306 ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>;
307 ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>;
308 ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>;
309 //def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>;
311 //===----------------------------------------------------------------------===//
313 //===----------------------------------------------------------------------===//
315 def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>;
316 def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>;
319 This instruction is disabled for now until we can figure out how to teach
320 the instruction selector to correctly use the S_CMP* vs V_CMP*
323 When this instruction is enabled the code generator sometimes produces this
326 SCC = S_CMPK_EQ_I32 SGPR0, imm
328 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
330 def S_CMPK_EQ_I32 : SOPK <
331 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1),
333 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))]
337 let isCompare = 1, Defs = [SCC] in {
338 def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>;
339 def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>;
340 def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>;
341 def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>;
342 def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>;
343 def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>;
344 def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>;
345 def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>;
346 def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>;
347 def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>;
348 def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>;
349 } // End isCompare = 1, Defs = [SCC]
351 let Defs = [SCC], isCommutable = 1 in {
352 def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>;
353 def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>;
356 //def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>;
357 def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>;
358 def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>;
359 def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>;
360 //def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>;
361 //def EXP : EXP_ <0x00000000, "EXP", []>;
363 } // End let OtherPredicates = [isCFDepth0]
365 //===----------------------------------------------------------------------===//
367 //===----------------------------------------------------------------------===//
369 def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "S_NOP $simm16", []>;
371 let isTerminator = 1 in {
373 def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM",
380 let isBranch = 1 in {
381 def S_BRANCH : SOPP <
382 0x00000002, (ins sopp_brtarget:$simm16), "S_BRANCH $simm16",
387 let DisableEncoding = "$scc" in {
388 def S_CBRANCH_SCC0 : SOPP <
389 0x00000004, (ins sopp_brtarget:$simm16, SCCReg:$scc),
390 "S_CBRANCH_SCC0 $simm16", []
392 def S_CBRANCH_SCC1 : SOPP <
393 0x00000005, (ins sopp_brtarget:$simm16, SCCReg:$scc),
394 "S_CBRANCH_SCC1 $simm16",
397 } // End DisableEncoding = "$scc"
399 def S_CBRANCH_VCCZ : SOPP <
400 0x00000006, (ins sopp_brtarget:$simm16, VCCReg:$vcc),
401 "S_CBRANCH_VCCZ $simm16",
404 def S_CBRANCH_VCCNZ : SOPP <
405 0x00000007, (ins sopp_brtarget:$simm16, VCCReg:$vcc),
406 "S_CBRANCH_VCCNZ $simm16",
410 let DisableEncoding = "$exec" in {
411 def S_CBRANCH_EXECZ : SOPP <
412 0x00000008, (ins sopp_brtarget:$simm16, EXECReg:$exec),
413 "S_CBRANCH_EXECZ $simm16",
416 def S_CBRANCH_EXECNZ : SOPP <
417 0x00000009, (ins sopp_brtarget:$simm16, EXECReg:$exec),
418 "S_CBRANCH_EXECNZ $simm16",
421 } // End DisableEncoding = "$exec"
424 } // End isBranch = 1
425 } // End isTerminator = 1
427 let hasSideEffects = 1 in {
428 def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER",
429 [(int_AMDGPU_barrier_local)]
438 def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16",
441 //def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>;
442 //def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>;
443 //def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>;
445 let Uses = [EXEC] in {
446 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "S_SENDMSG $simm16",
447 [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)]
449 let DisableEncoding = "$m0";
451 } // End Uses = [EXEC]
453 //def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>;
454 //def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>;
455 //def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>;
456 //def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>;
457 //def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>;
458 //def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
459 } // End hasSideEffects
461 //===----------------------------------------------------------------------===//
463 //===----------------------------------------------------------------------===//
465 let isCompare = 1 in {
467 defm V_CMP_F_F32 : VOPC_F32 <0x00000000, "V_CMP_F_F32">;
468 defm V_CMP_LT_F32 : VOPC_F32 <0x00000001, "V_CMP_LT_F32", COND_OLT>;
469 defm V_CMP_EQ_F32 : VOPC_F32 <0x00000002, "V_CMP_EQ_F32", COND_OEQ>;
470 defm V_CMP_LE_F32 : VOPC_F32 <0x00000003, "V_CMP_LE_F32", COND_OLE>;
471 defm V_CMP_GT_F32 : VOPC_F32 <0x00000004, "V_CMP_GT_F32", COND_OGT>;
472 defm V_CMP_LG_F32 : VOPC_F32 <0x00000005, "V_CMP_LG_F32">;
473 defm V_CMP_GE_F32 : VOPC_F32 <0x00000006, "V_CMP_GE_F32", COND_OGE>;
474 defm V_CMP_O_F32 : VOPC_F32 <0x00000007, "V_CMP_O_F32", COND_O>;
475 defm V_CMP_U_F32 : VOPC_F32 <0x00000008, "V_CMP_U_F32", COND_UO>;
476 defm V_CMP_NGE_F32 : VOPC_F32 <0x00000009, "V_CMP_NGE_F32">;
477 defm V_CMP_NLG_F32 : VOPC_F32 <0x0000000a, "V_CMP_NLG_F32">;
478 defm V_CMP_NGT_F32 : VOPC_F32 <0x0000000b, "V_CMP_NGT_F32">;
479 defm V_CMP_NLE_F32 : VOPC_F32 <0x0000000c, "V_CMP_NLE_F32">;
480 defm V_CMP_NEQ_F32 : VOPC_F32 <0x0000000d, "V_CMP_NEQ_F32", COND_UNE>;
481 defm V_CMP_NLT_F32 : VOPC_F32 <0x0000000e, "V_CMP_NLT_F32">;
482 defm V_CMP_TRU_F32 : VOPC_F32 <0x0000000f, "V_CMP_TRU_F32">;
484 let hasSideEffects = 1 in {
486 defm V_CMPX_F_F32 : VOPCX_F32 <0x00000010, "V_CMPX_F_F32">;
487 defm V_CMPX_LT_F32 : VOPCX_F32 <0x00000011, "V_CMPX_LT_F32">;
488 defm V_CMPX_EQ_F32 : VOPCX_F32 <0x00000012, "V_CMPX_EQ_F32">;
489 defm V_CMPX_LE_F32 : VOPCX_F32 <0x00000013, "V_CMPX_LE_F32">;
490 defm V_CMPX_GT_F32 : VOPCX_F32 <0x00000014, "V_CMPX_GT_F32">;
491 defm V_CMPX_LG_F32 : VOPCX_F32 <0x00000015, "V_CMPX_LG_F32">;
492 defm V_CMPX_GE_F32 : VOPCX_F32 <0x00000016, "V_CMPX_GE_F32">;
493 defm V_CMPX_O_F32 : VOPCX_F32 <0x00000017, "V_CMPX_O_F32">;
494 defm V_CMPX_U_F32 : VOPCX_F32 <0x00000018, "V_CMPX_U_F32">;
495 defm V_CMPX_NGE_F32 : VOPCX_F32 <0x00000019, "V_CMPX_NGE_F32">;
496 defm V_CMPX_NLG_F32 : VOPCX_F32 <0x0000001a, "V_CMPX_NLG_F32">;
497 defm V_CMPX_NGT_F32 : VOPCX_F32 <0x0000001b, "V_CMPX_NGT_F32">;
498 defm V_CMPX_NLE_F32 : VOPCX_F32 <0x0000001c, "V_CMPX_NLE_F32">;
499 defm V_CMPX_NEQ_F32 : VOPCX_F32 <0x0000001d, "V_CMPX_NEQ_F32">;
500 defm V_CMPX_NLT_F32 : VOPCX_F32 <0x0000001e, "V_CMPX_NLT_F32">;
501 defm V_CMPX_TRU_F32 : VOPCX_F32 <0x0000001f, "V_CMPX_TRU_F32">;
503 } // End hasSideEffects = 1
505 defm V_CMP_F_F64 : VOPC_F64 <0x00000020, "V_CMP_F_F64">;
506 defm V_CMP_LT_F64 : VOPC_F64 <0x00000021, "V_CMP_LT_F64", COND_OLT>;
507 defm V_CMP_EQ_F64 : VOPC_F64 <0x00000022, "V_CMP_EQ_F64", COND_OEQ>;
508 defm V_CMP_LE_F64 : VOPC_F64 <0x00000023, "V_CMP_LE_F64", COND_OLE>;
509 defm V_CMP_GT_F64 : VOPC_F64 <0x00000024, "V_CMP_GT_F64", COND_OGT>;
510 defm V_CMP_LG_F64 : VOPC_F64 <0x00000025, "V_CMP_LG_F64">;
511 defm V_CMP_GE_F64 : VOPC_F64 <0x00000026, "V_CMP_GE_F64", COND_OGE>;
512 defm V_CMP_O_F64 : VOPC_F64 <0x00000027, "V_CMP_O_F64", COND_O>;
513 defm V_CMP_U_F64 : VOPC_F64 <0x00000028, "V_CMP_U_F64", COND_UO>;
514 defm V_CMP_NGE_F64 : VOPC_F64 <0x00000029, "V_CMP_NGE_F64">;
515 defm V_CMP_NLG_F64 : VOPC_F64 <0x0000002a, "V_CMP_NLG_F64">;
516 defm V_CMP_NGT_F64 : VOPC_F64 <0x0000002b, "V_CMP_NGT_F64">;
517 defm V_CMP_NLE_F64 : VOPC_F64 <0x0000002c, "V_CMP_NLE_F64">;
518 defm V_CMP_NEQ_F64 : VOPC_F64 <0x0000002d, "V_CMP_NEQ_F64", COND_UNE>;
519 defm V_CMP_NLT_F64 : VOPC_F64 <0x0000002e, "V_CMP_NLT_F64">;
520 defm V_CMP_TRU_F64 : VOPC_F64 <0x0000002f, "V_CMP_TRU_F64">;
522 let hasSideEffects = 1 in {
524 defm V_CMPX_F_F64 : VOPCX_F64 <0x00000030, "V_CMPX_F_F64">;
525 defm V_CMPX_LT_F64 : VOPCX_F64 <0x00000031, "V_CMPX_LT_F64">;
526 defm V_CMPX_EQ_F64 : VOPCX_F64 <0x00000032, "V_CMPX_EQ_F64">;
527 defm V_CMPX_LE_F64 : VOPCX_F64 <0x00000033, "V_CMPX_LE_F64">;
528 defm V_CMPX_GT_F64 : VOPCX_F64 <0x00000034, "V_CMPX_GT_F64">;
529 defm V_CMPX_LG_F64 : VOPCX_F64 <0x00000035, "V_CMPX_LG_F64">;
530 defm V_CMPX_GE_F64 : VOPCX_F64 <0x00000036, "V_CMPX_GE_F64">;
531 defm V_CMPX_O_F64 : VOPCX_F64 <0x00000037, "V_CMPX_O_F64">;
532 defm V_CMPX_U_F64 : VOPCX_F64 <0x00000038, "V_CMPX_U_F64">;
533 defm V_CMPX_NGE_F64 : VOPCX_F64 <0x00000039, "V_CMPX_NGE_F64">;
534 defm V_CMPX_NLG_F64 : VOPCX_F64 <0x0000003a, "V_CMPX_NLG_F64">;
535 defm V_CMPX_NGT_F64 : VOPCX_F64 <0x0000003b, "V_CMPX_NGT_F64">;
536 defm V_CMPX_NLE_F64 : VOPCX_F64 <0x0000003c, "V_CMPX_NLE_F64">;
537 defm V_CMPX_NEQ_F64 : VOPCX_F64 <0x0000003d, "V_CMPX_NEQ_F64">;
538 defm V_CMPX_NLT_F64 : VOPCX_F64 <0x0000003e, "V_CMPX_NLT_F64">;
539 defm V_CMPX_TRU_F64 : VOPCX_F64 <0x0000003f, "V_CMPX_TRU_F64">;
541 } // End hasSideEffects = 1
543 defm V_CMPS_F_F32 : VOPC_F32 <0x00000040, "V_CMPS_F_F32">;
544 defm V_CMPS_LT_F32 : VOPC_F32 <0x00000041, "V_CMPS_LT_F32">;
545 defm V_CMPS_EQ_F32 : VOPC_F32 <0x00000042, "V_CMPS_EQ_F32">;
546 defm V_CMPS_LE_F32 : VOPC_F32 <0x00000043, "V_CMPS_LE_F32">;
547 defm V_CMPS_GT_F32 : VOPC_F32 <0x00000044, "V_CMPS_GT_F32">;
548 defm V_CMPS_LG_F32 : VOPC_F32 <0x00000045, "V_CMPS_LG_F32">;
549 defm V_CMPS_GE_F32 : VOPC_F32 <0x00000046, "V_CMPS_GE_F32">;
550 defm V_CMPS_O_F32 : VOPC_F32 <0x00000047, "V_CMPS_O_F32">;
551 defm V_CMPS_U_F32 : VOPC_F32 <0x00000048, "V_CMPS_U_F32">;
552 defm V_CMPS_NGE_F32 : VOPC_F32 <0x00000049, "V_CMPS_NGE_F32">;
553 defm V_CMPS_NLG_F32 : VOPC_F32 <0x0000004a, "V_CMPS_NLG_F32">;
554 defm V_CMPS_NGT_F32 : VOPC_F32 <0x0000004b, "V_CMPS_NGT_F32">;
555 defm V_CMPS_NLE_F32 : VOPC_F32 <0x0000004c, "V_CMPS_NLE_F32">;
556 defm V_CMPS_NEQ_F32 : VOPC_F32 <0x0000004d, "V_CMPS_NEQ_F32">;
557 defm V_CMPS_NLT_F32 : VOPC_F32 <0x0000004e, "V_CMPS_NLT_F32">;
558 defm V_CMPS_TRU_F32 : VOPC_F32 <0x0000004f, "V_CMPS_TRU_F32">;
560 let hasSideEffects = 1 in {
562 defm V_CMPSX_F_F32 : VOPCX_F32 <0x00000050, "V_CMPSX_F_F32">;
563 defm V_CMPSX_LT_F32 : VOPCX_F32 <0x00000051, "V_CMPSX_LT_F32">;
564 defm V_CMPSX_EQ_F32 : VOPCX_F32 <0x00000052, "V_CMPSX_EQ_F32">;
565 defm V_CMPSX_LE_F32 : VOPCX_F32 <0x00000053, "V_CMPSX_LE_F32">;
566 defm V_CMPSX_GT_F32 : VOPCX_F32 <0x00000054, "V_CMPSX_GT_F32">;
567 defm V_CMPSX_LG_F32 : VOPCX_F32 <0x00000055, "V_CMPSX_LG_F32">;
568 defm V_CMPSX_GE_F32 : VOPCX_F32 <0x00000056, "V_CMPSX_GE_F32">;
569 defm V_CMPSX_O_F32 : VOPCX_F32 <0x00000057, "V_CMPSX_O_F32">;
570 defm V_CMPSX_U_F32 : VOPCX_F32 <0x00000058, "V_CMPSX_U_F32">;
571 defm V_CMPSX_NGE_F32 : VOPCX_F32 <0x00000059, "V_CMPSX_NGE_F32">;
572 defm V_CMPSX_NLG_F32 : VOPCX_F32 <0x0000005a, "V_CMPSX_NLG_F32">;
573 defm V_CMPSX_NGT_F32 : VOPCX_F32 <0x0000005b, "V_CMPSX_NGT_F32">;
574 defm V_CMPSX_NLE_F32 : VOPCX_F32 <0x0000005c, "V_CMPSX_NLE_F32">;
575 defm V_CMPSX_NEQ_F32 : VOPCX_F32 <0x0000005d, "V_CMPSX_NEQ_F32">;
576 defm V_CMPSX_NLT_F32 : VOPCX_F32 <0x0000005e, "V_CMPSX_NLT_F32">;
577 defm V_CMPSX_TRU_F32 : VOPCX_F32 <0x0000005f, "V_CMPSX_TRU_F32">;
579 } // End hasSideEffects = 1
581 defm V_CMPS_F_F64 : VOPC_F64 <0x00000060, "V_CMPS_F_F64">;
582 defm V_CMPS_LT_F64 : VOPC_F64 <0x00000061, "V_CMPS_LT_F64">;
583 defm V_CMPS_EQ_F64 : VOPC_F64 <0x00000062, "V_CMPS_EQ_F64">;
584 defm V_CMPS_LE_F64 : VOPC_F64 <0x00000063, "V_CMPS_LE_F64">;
585 defm V_CMPS_GT_F64 : VOPC_F64 <0x00000064, "V_CMPS_GT_F64">;
586 defm V_CMPS_LG_F64 : VOPC_F64 <0x00000065, "V_CMPS_LG_F64">;
587 defm V_CMPS_GE_F64 : VOPC_F64 <0x00000066, "V_CMPS_GE_F64">;
588 defm V_CMPS_O_F64 : VOPC_F64 <0x00000067, "V_CMPS_O_F64">;
589 defm V_CMPS_U_F64 : VOPC_F64 <0x00000068, "V_CMPS_U_F64">;
590 defm V_CMPS_NGE_F64 : VOPC_F64 <0x00000069, "V_CMPS_NGE_F64">;
591 defm V_CMPS_NLG_F64 : VOPC_F64 <0x0000006a, "V_CMPS_NLG_F64">;
592 defm V_CMPS_NGT_F64 : VOPC_F64 <0x0000006b, "V_CMPS_NGT_F64">;
593 defm V_CMPS_NLE_F64 : VOPC_F64 <0x0000006c, "V_CMPS_NLE_F64">;
594 defm V_CMPS_NEQ_F64 : VOPC_F64 <0x0000006d, "V_CMPS_NEQ_F64">;
595 defm V_CMPS_NLT_F64 : VOPC_F64 <0x0000006e, "V_CMPS_NLT_F64">;
596 defm V_CMPS_TRU_F64 : VOPC_F64 <0x0000006f, "V_CMPS_TRU_F64">;
598 let hasSideEffects = 1, Defs = [EXEC] in {
600 defm V_CMPSX_F_F64 : VOPC_F64 <0x00000070, "V_CMPSX_F_F64">;
601 defm V_CMPSX_LT_F64 : VOPC_F64 <0x00000071, "V_CMPSX_LT_F64">;
602 defm V_CMPSX_EQ_F64 : VOPC_F64 <0x00000072, "V_CMPSX_EQ_F64">;
603 defm V_CMPSX_LE_F64 : VOPC_F64 <0x00000073, "V_CMPSX_LE_F64">;
604 defm V_CMPSX_GT_F64 : VOPC_F64 <0x00000074, "V_CMPSX_GT_F64">;
605 defm V_CMPSX_LG_F64 : VOPC_F64 <0x00000075, "V_CMPSX_LG_F64">;
606 defm V_CMPSX_GE_F64 : VOPC_F64 <0x00000076, "V_CMPSX_GE_F64">;
607 defm V_CMPSX_O_F64 : VOPC_F64 <0x00000077, "V_CMPSX_O_F64">;
608 defm V_CMPSX_U_F64 : VOPC_F64 <0x00000078, "V_CMPSX_U_F64">;
609 defm V_CMPSX_NGE_F64 : VOPC_F64 <0x00000079, "V_CMPSX_NGE_F64">;
610 defm V_CMPSX_NLG_F64 : VOPC_F64 <0x0000007a, "V_CMPSX_NLG_F64">;
611 defm V_CMPSX_NGT_F64 : VOPC_F64 <0x0000007b, "V_CMPSX_NGT_F64">;
612 defm V_CMPSX_NLE_F64 : VOPC_F64 <0x0000007c, "V_CMPSX_NLE_F64">;
613 defm V_CMPSX_NEQ_F64 : VOPC_F64 <0x0000007d, "V_CMPSX_NEQ_F64">;
614 defm V_CMPSX_NLT_F64 : VOPC_F64 <0x0000007e, "V_CMPSX_NLT_F64">;
615 defm V_CMPSX_TRU_F64 : VOPC_F64 <0x0000007f, "V_CMPSX_TRU_F64">;
617 } // End hasSideEffects = 1, Defs = [EXEC]
619 defm V_CMP_F_I32 : VOPC_I32 <0x00000080, "V_CMP_F_I32">;
620 defm V_CMP_LT_I32 : VOPC_I32 <0x00000081, "V_CMP_LT_I32", COND_SLT>;
621 defm V_CMP_EQ_I32 : VOPC_I32 <0x00000082, "V_CMP_EQ_I32", COND_EQ>;
622 defm V_CMP_LE_I32 : VOPC_I32 <0x00000083, "V_CMP_LE_I32", COND_SLE>;
623 defm V_CMP_GT_I32 : VOPC_I32 <0x00000084, "V_CMP_GT_I32", COND_SGT>;
624 defm V_CMP_NE_I32 : VOPC_I32 <0x00000085, "V_CMP_NE_I32", COND_NE>;
625 defm V_CMP_GE_I32 : VOPC_I32 <0x00000086, "V_CMP_GE_I32", COND_SGE>;
626 defm V_CMP_T_I32 : VOPC_I32 <0x00000087, "V_CMP_T_I32">;
628 let hasSideEffects = 1 in {
630 defm V_CMPX_F_I32 : VOPCX_I32 <0x00000090, "V_CMPX_F_I32">;
631 defm V_CMPX_LT_I32 : VOPCX_I32 <0x00000091, "V_CMPX_LT_I32">;
632 defm V_CMPX_EQ_I32 : VOPCX_I32 <0x00000092, "V_CMPX_EQ_I32">;
633 defm V_CMPX_LE_I32 : VOPCX_I32 <0x00000093, "V_CMPX_LE_I32">;
634 defm V_CMPX_GT_I32 : VOPCX_I32 <0x00000094, "V_CMPX_GT_I32">;
635 defm V_CMPX_NE_I32 : VOPCX_I32 <0x00000095, "V_CMPX_NE_I32">;
636 defm V_CMPX_GE_I32 : VOPCX_I32 <0x00000096, "V_CMPX_GE_I32">;
637 defm V_CMPX_T_I32 : VOPCX_I32 <0x00000097, "V_CMPX_T_I32">;
639 } // End hasSideEffects = 1
641 defm V_CMP_F_I64 : VOPC_I64 <0x000000a0, "V_CMP_F_I64">;
642 defm V_CMP_LT_I64 : VOPC_I64 <0x000000a1, "V_CMP_LT_I64", COND_SLT>;
643 defm V_CMP_EQ_I64 : VOPC_I64 <0x000000a2, "V_CMP_EQ_I64", COND_EQ>;
644 defm V_CMP_LE_I64 : VOPC_I64 <0x000000a3, "V_CMP_LE_I64", COND_SLE>;
645 defm V_CMP_GT_I64 : VOPC_I64 <0x000000a4, "V_CMP_GT_I64", COND_SGT>;
646 defm V_CMP_NE_I64 : VOPC_I64 <0x000000a5, "V_CMP_NE_I64", COND_NE>;
647 defm V_CMP_GE_I64 : VOPC_I64 <0x000000a6, "V_CMP_GE_I64", COND_SGE>;
648 defm V_CMP_T_I64 : VOPC_I64 <0x000000a7, "V_CMP_T_I64">;
650 let hasSideEffects = 1 in {
652 defm V_CMPX_F_I64 : VOPCX_I64 <0x000000b0, "V_CMPX_F_I64">;
653 defm V_CMPX_LT_I64 : VOPCX_I64 <0x000000b1, "V_CMPX_LT_I64">;
654 defm V_CMPX_EQ_I64 : VOPCX_I64 <0x000000b2, "V_CMPX_EQ_I64">;
655 defm V_CMPX_LE_I64 : VOPCX_I64 <0x000000b3, "V_CMPX_LE_I64">;
656 defm V_CMPX_GT_I64 : VOPCX_I64 <0x000000b4, "V_CMPX_GT_I64">;
657 defm V_CMPX_NE_I64 : VOPCX_I64 <0x000000b5, "V_CMPX_NE_I64">;
658 defm V_CMPX_GE_I64 : VOPCX_I64 <0x000000b6, "V_CMPX_GE_I64">;
659 defm V_CMPX_T_I64 : VOPCX_I64 <0x000000b7, "V_CMPX_T_I64">;
661 } // End hasSideEffects = 1
663 defm V_CMP_F_U32 : VOPC_I32 <0x000000c0, "V_CMP_F_U32">;
664 defm V_CMP_LT_U32 : VOPC_I32 <0x000000c1, "V_CMP_LT_U32", COND_ULT>;
665 defm V_CMP_EQ_U32 : VOPC_I32 <0x000000c2, "V_CMP_EQ_U32", COND_EQ>;
666 defm V_CMP_LE_U32 : VOPC_I32 <0x000000c3, "V_CMP_LE_U32", COND_ULE>;
667 defm V_CMP_GT_U32 : VOPC_I32 <0x000000c4, "V_CMP_GT_U32", COND_UGT>;
668 defm V_CMP_NE_U32 : VOPC_I32 <0x000000c5, "V_CMP_NE_U32", COND_NE>;
669 defm V_CMP_GE_U32 : VOPC_I32 <0x000000c6, "V_CMP_GE_U32", COND_UGE>;
670 defm V_CMP_T_U32 : VOPC_I32 <0x000000c7, "V_CMP_T_U32">;
672 let hasSideEffects = 1 in {
674 defm V_CMPX_F_U32 : VOPCX_I32 <0x000000d0, "V_CMPX_F_U32">;
675 defm V_CMPX_LT_U32 : VOPCX_I32 <0x000000d1, "V_CMPX_LT_U32">;
676 defm V_CMPX_EQ_U32 : VOPCX_I32 <0x000000d2, "V_CMPX_EQ_U32">;
677 defm V_CMPX_LE_U32 : VOPCX_I32 <0x000000d3, "V_CMPX_LE_U32">;
678 defm V_CMPX_GT_U32 : VOPCX_I32 <0x000000d4, "V_CMPX_GT_U32">;
679 defm V_CMPX_NE_U32 : VOPCX_I32 <0x000000d5, "V_CMPX_NE_U32">;
680 defm V_CMPX_GE_U32 : VOPCX_I32 <0x000000d6, "V_CMPX_GE_U32">;
681 defm V_CMPX_T_U32 : VOPCX_I32 <0x000000d7, "V_CMPX_T_U32">;
683 } // End hasSideEffects = 1
685 defm V_CMP_F_U64 : VOPC_I64 <0x000000e0, "V_CMP_F_U64">;
686 defm V_CMP_LT_U64 : VOPC_I64 <0x000000e1, "V_CMP_LT_U64", COND_ULT>;
687 defm V_CMP_EQ_U64 : VOPC_I64 <0x000000e2, "V_CMP_EQ_U64", COND_EQ>;
688 defm V_CMP_LE_U64 : VOPC_I64 <0x000000e3, "V_CMP_LE_U64", COND_ULE>;
689 defm V_CMP_GT_U64 : VOPC_I64 <0x000000e4, "V_CMP_GT_U64", COND_UGT>;
690 defm V_CMP_NE_U64 : VOPC_I64 <0x000000e5, "V_CMP_NE_U64", COND_NE>;
691 defm V_CMP_GE_U64 : VOPC_I64 <0x000000e6, "V_CMP_GE_U64", COND_UGE>;
692 defm V_CMP_T_U64 : VOPC_I64 <0x000000e7, "V_CMP_T_U64">;
694 let hasSideEffects = 1 in {
696 defm V_CMPX_F_U64 : VOPCX_I64 <0x000000f0, "V_CMPX_F_U64">;
697 defm V_CMPX_LT_U64 : VOPCX_I64 <0x000000f1, "V_CMPX_LT_U64">;
698 defm V_CMPX_EQ_U64 : VOPCX_I64 <0x000000f2, "V_CMPX_EQ_U64">;
699 defm V_CMPX_LE_U64 : VOPCX_I64 <0x000000f3, "V_CMPX_LE_U64">;
700 defm V_CMPX_GT_U64 : VOPCX_I64 <0x000000f4, "V_CMPX_GT_U64">;
701 defm V_CMPX_NE_U64 : VOPCX_I64 <0x000000f5, "V_CMPX_NE_U64">;
702 defm V_CMPX_GE_U64 : VOPCX_I64 <0x000000f6, "V_CMPX_GE_U64">;
703 defm V_CMPX_T_U64 : VOPCX_I64 <0x000000f7, "V_CMPX_T_U64">;
705 } // End hasSideEffects = 1
707 defm V_CMP_CLASS_F32 : VOPC_F32 <0x00000088, "V_CMP_CLASS_F32">;
709 let hasSideEffects = 1 in {
710 defm V_CMPX_CLASS_F32 : VOPCX_F32 <0x00000098, "V_CMPX_CLASS_F32">;
711 } // End hasSideEffects = 1
713 defm V_CMP_CLASS_F64 : VOPC_F64 <0x000000a8, "V_CMP_CLASS_F64">;
715 let hasSideEffects = 1 in {
716 defm V_CMPX_CLASS_F64 : VOPCX_F64 <0x000000b8, "V_CMPX_CLASS_F64">;
717 } // End hasSideEffects = 1
719 } // End isCompare = 1
721 //===----------------------------------------------------------------------===//
723 //===----------------------------------------------------------------------===//
726 def DS_ADD_U32 : DS_1A1D_NORET <0x0, "DS_ADD_U32", VReg_32>;
727 def DS_SUB_U32 : DS_1A1D_NORET <0x1, "DS_SUB_U32", VReg_32>;
728 def DS_RSUB_U32 : DS_1A1D_NORET <0x2, "DS_RSUB_U32", VReg_32>;
729 def DS_INC_U32 : DS_1A1D_NORET <0x3, "DS_INC_U32", VReg_32>;
730 def DS_DEC_U32 : DS_1A1D_NORET <0x4, "DS_DEC_U32", VReg_32>;
731 def DS_MIN_I32 : DS_1A1D_NORET <0x5, "DS_MIN_I32", VReg_32>;
732 def DS_MAX_I32 : DS_1A1D_NORET <0x6, "DS_MAX_I32", VReg_32>;
733 def DS_MIN_U32 : DS_1A1D_NORET <0x7, "DS_MIN_U32", VReg_32>;
734 def DS_MAX_U32 : DS_1A1D_NORET <0x8, "DS_MAX_U32", VReg_32>;
735 def DS_AND_B32 : DS_1A1D_NORET <0x9, "DS_AND_B32", VReg_32>;
736 def DS_OR_B32 : DS_1A1D_NORET <0xa, "DS_OR_B32", VReg_32>;
737 def DS_XOR_B32 : DS_1A1D_NORET <0xb, "DS_XOR_B32", VReg_32>;
738 def DS_MSKOR_B32 : DS_1A1D_NORET <0xc, "DS_MSKOR_B32", VReg_32>;
739 def DS_CMPST_B32 : DS_1A2D_NORET <0x10, "DS_CMPST_B32", VReg_32>;
740 def DS_CMPST_F32 : DS_1A2D_NORET <0x11, "DS_CMPST_F32", VReg_32>;
741 def DS_MIN_F32 : DS_1A1D_NORET <0x12, "DS_MIN_F32", VReg_32>;
742 def DS_MAX_F32 : DS_1A1D_NORET <0x13, "DS_MAX_F32", VReg_32>;
744 def DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "DS_ADD_RTN_U32", VReg_32>;
745 def DS_SUB_RTN_U32 : DS_1A1D_RET <0x21, "DS_SUB_RTN_U32", VReg_32>;
746 def DS_RSUB_RTN_U32 : DS_1A1D_RET <0x22, "DS_RSUB_RTN_U32", VReg_32>;
747 def DS_INC_RTN_U32 : DS_1A1D_RET <0x23, "DS_INC_RTN_U32", VReg_32>;
748 def DS_DEC_RTN_U32 : DS_1A1D_RET <0x24, "DS_DEC_RTN_U32", VReg_32>;
749 def DS_MIN_RTN_I32 : DS_1A1D_RET <0x25, "DS_MIN_RTN_I32", VReg_32>;
750 def DS_MAX_RTN_I32 : DS_1A1D_RET <0x26, "DS_MAX_RTN_I32", VReg_32>;
751 def DS_MIN_RTN_U32 : DS_1A1D_RET <0x27, "DS_MIN_RTN_U32", VReg_32>;
752 def DS_MAX_RTN_U32 : DS_1A1D_RET <0x28, "DS_MAX_RTN_U32", VReg_32>;
753 def DS_AND_RTN_B32 : DS_1A1D_RET <0x29, "DS_AND_RTN_B32", VReg_32>;
754 def DS_OR_RTN_B32 : DS_1A1D_RET <0x2a, "DS_OR_RTN_B32", VReg_32>;
755 def DS_XOR_RTN_B32 : DS_1A1D_RET <0x2b, "DS_XOR_RTN_B32", VReg_32>;
756 def DS_MSKOR_RTN_B32 : DS_1A1D_RET <0x2c, "DS_MSKOR_RTN_B32", VReg_32>;
757 def DS_WRXCHG_RTN_B32 : DS_1A1D_RET <0x2d, "DS_WRXCHG_RTN_B32", VReg_32>;
758 //def DS_WRXCHG2_RTN_B32 : DS_2A0D_RET <0x2e, "DS_WRXCHG2_RTN_B32", VReg_32>;
759 //def DS_WRXCHG2ST64_RTN_B32 : DS_2A0D_RET <0x2f, "DS_WRXCHG2_RTN_B32", VReg_32>;
760 def DS_CMPST_RTN_B32 : DS_1A2D_RET <0x30, "DS_CMPST_RTN_B32", VReg_32>;
761 def DS_CMPST_RTN_F32 : DS_1A2D_RET <0x31, "DS_CMPST_RTN_F32", VReg_32>;
762 def DS_MIN_RTN_F32 : DS_1A1D_RET <0x32, "DS_MIN_RTN_F32", VReg_32>;
763 def DS_MAX_RTN_F32 : DS_1A1D_RET <0x33, "DS_MAX_RTN_F32", VReg_32>;
765 let SubtargetPredicate = isCI in {
766 def DS_WRAP_RTN_F32 : DS_1A1D_RET <0x34, "DS_WRAP_RTN_F32", VReg_32>;
770 def DS_ADD_U64 : DS_1A1D_NORET <0x40, "DS_ADD_U64", VReg_32>;
771 def DS_SUB_U64 : DS_1A1D_NORET <0x41, "DS_SUB_U64", VReg_32>;
772 def DS_RSUB_U64 : DS_1A1D_NORET <0x42, "DS_RSUB_U64", VReg_32>;
773 def DS_INC_U64 : DS_1A1D_NORET <0x43, "DS_INC_U64", VReg_32>;
774 def DS_DEC_U64 : DS_1A1D_NORET <0x44, "DS_DEC_U64", VReg_32>;
775 def DS_MIN_I64 : DS_1A1D_NORET <0x45, "DS_MIN_I64", VReg_64>;
776 def DS_MAX_I64 : DS_1A1D_NORET <0x46, "DS_MAX_I64", VReg_64>;
777 def DS_MIN_U64 : DS_1A1D_NORET <0x47, "DS_MIN_U64", VReg_64>;
778 def DS_MAX_U64 : DS_1A1D_NORET <0x48, "DS_MAX_U64", VReg_64>;
779 def DS_AND_B64 : DS_1A1D_NORET <0x49, "DS_AND_B64", VReg_64>;
780 def DS_OR_B64 : DS_1A1D_NORET <0x4a, "DS_OR_B64", VReg_64>;
781 def DS_XOR_B64 : DS_1A1D_NORET <0x4b, "DS_XOR_B64", VReg_64>;
782 def DS_MSKOR_B64 : DS_1A1D_NORET <0x4c, "DS_MSKOR_B64", VReg_64>;
783 def DS_CMPST_B64 : DS_1A2D_NORET <0x50, "DS_CMPST_B64", VReg_64>;
784 def DS_CMPST_F64 : DS_1A2D_NORET <0x51, "DS_CMPST_F64", VReg_64>;
785 def DS_MIN_F64 : DS_1A1D_NORET <0x52, "DS_MIN_F64", VReg_64>;
786 def DS_MAX_F64 : DS_1A1D_NORET <0x53, "DS_MAX_F64", VReg_64>;
788 def DS_ADD_RTN_U64 : DS_1A1D_RET <0x60, "DS_ADD_RTN_U64", VReg_64>;
789 def DS_SUB_RTN_U64 : DS_1A1D_RET <0x61, "DS_SUB_RTN_U64", VReg_64>;
790 def DS_RSUB_RTN_U64 : DS_1A1D_RET <0x62, "DS_RSUB_RTN_U64", VReg_64>;
791 def DS_INC_RTN_U64 : DS_1A1D_RET <0x63, "DS_INC_RTN_U64", VReg_64>;
792 def DS_DEC_RTN_U64 : DS_1A1D_RET <0x64, "DS_DEC_RTN_U64", VReg_64>;
793 def DS_MIN_RTN_I64 : DS_1A1D_RET <0x65, "DS_MIN_RTN_I64", VReg_64>;
794 def DS_MAX_RTN_I64 : DS_1A1D_RET <0x66, "DS_MAX_RTN_I64", VReg_64>;
795 def DS_MIN_RTN_U64 : DS_1A1D_RET <0x67, "DS_MIN_RTN_U64", VReg_64>;
796 def DS_MAX_RTN_U64 : DS_1A1D_RET <0x68, "DS_MAX_RTN_U64", VReg_64>;
797 def DS_AND_RTN_B64 : DS_1A1D_RET <0x69, "DS_AND_RTN_B64", VReg_64>;
798 def DS_OR_RTN_B64 : DS_1A1D_RET <0x6a, "DS_OR_RTN_B64", VReg_64>;
799 def DS_XOR_RTN_B64 : DS_1A1D_RET <0x6b, "DS_XOR_RTN_B64", VReg_64>;
800 def DS_MSKOR_RTN_B64 : DS_1A1D_RET <0x6c, "DS_MSKOR_RTN_B64", VReg_64>;
801 def DS_WRXCHG_RTN_B64 : DS_1A1D_RET <0x6d, "DS_WRXCHG_RTN_B64", VReg_64>;
802 //def DS_WRXCHG2_RTN_B64 : DS_2A0D_RET <0x6e, "DS_WRXCHG2_RTN_B64", VReg_64>;
803 //def DS_WRXCHG2ST64_RTN_B64 : DS_2A0D_RET <0x6f, "DS_WRXCHG2_RTN_B64", VReg_64>;
804 def DS_CMPST_RTN_B64 : DS_1A2D_RET <0x70, "DS_CMPST_RTN_B64", VReg_64>;
805 def DS_CMPST_RTN_F64 : DS_1A2D_RET <0x71, "DS_CMPST_RTN_F64", VReg_64>;
806 def DS_MIN_RTN_F64 : DS_1A1D_RET <0x72, "DS_MIN_F64", VReg_64>;
807 def DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "DS_MAX_F64", VReg_64>;
809 //let SubtargetPredicate = isCI in {
810 // DS_CONDXCHG32_RTN_B64
811 // DS_CONDXCHG32_RTN_B128
814 // TODO: _SRC2_* forms
816 def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>;
817 def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "DS_WRITE_B8", VReg_32>;
818 def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "DS_WRITE_B16", VReg_32>;
819 def DS_WRITE_B64 : DS_Store_Helper <0x00000004d, "DS_WRITE_B64", VReg_64>;
821 def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>;
822 def DS_READ_I8 : DS_Load_Helper <0x00000039, "DS_READ_I8", VReg_32>;
823 def DS_READ_U8 : DS_Load_Helper <0x0000003a, "DS_READ_U8", VReg_32>;
824 def DS_READ_I16 : DS_Load_Helper <0x0000003b, "DS_READ_I16", VReg_32>;
825 def DS_READ_U16 : DS_Load_Helper <0x0000003c, "DS_READ_U16", VReg_32>;
826 def DS_READ_B64 : DS_Load_Helper <0x00000076, "DS_READ_B64", VReg_64>;
829 def DS_WRITE2_B32 : DS_Store2_Helper <0x0000000E, "DS_WRITE2_B32", VReg_32>;
830 def DS_WRITE2ST64_B32 : DS_Store2_Helper <0x0000000F, "DS_WRITE2ST64_B32", VReg_32>;
831 def DS_WRITE2_B64 : DS_Store2_Helper <0x0000004E, "DS_WRITE2_B64", VReg_64>;
832 def DS_WRITE2ST64_B64 : DS_Store2_Helper <0x0000004F, "DS_WRITE2ST64_B64", VReg_64>;
834 def DS_READ2_B32 : DS_Load2_Helper <0x00000037, "DS_READ2_B32", VReg_64>;
835 def DS_READ2ST64_B32 : DS_Load2_Helper <0x00000038, "DS_READ2ST64_B32", VReg_64>;
836 def DS_READ2_B64 : DS_Load2_Helper <0x00000075, "DS_READ2_B64", VReg_128>;
837 def DS_READ2ST64_B64 : DS_Load2_Helper <0x00000076, "DS_READ2ST64_B64", VReg_128>;
839 //===----------------------------------------------------------------------===//
840 // MUBUF Instructions
841 //===----------------------------------------------------------------------===//
843 //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>;
844 //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>;
845 //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>;
846 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>;
847 //def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>;
848 //def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>;
849 //def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>;
850 //def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>;
851 defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <
852 0x00000008, "BUFFER_LOAD_UBYTE", VReg_32, i32, az_extloadi8_global
854 defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <
855 0x00000009, "BUFFER_LOAD_SBYTE", VReg_32, i32, sextloadi8_global
857 defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <
858 0x0000000a, "BUFFER_LOAD_USHORT", VReg_32, i32, az_extloadi16_global
860 defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <
861 0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32, i32, sextloadi16_global
863 defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <
864 0x0000000c, "BUFFER_LOAD_DWORD", VReg_32, i32, global_load
866 defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <
867 0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64, v2i32, global_load
869 defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <
870 0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128, v4i32, global_load
873 defm BUFFER_STORE_BYTE : MUBUF_Store_Helper <
874 0x00000018, "BUFFER_STORE_BYTE", VReg_32, i32, truncstorei8_global
877 defm BUFFER_STORE_SHORT : MUBUF_Store_Helper <
878 0x0000001a, "BUFFER_STORE_SHORT", VReg_32, i32, truncstorei16_global
881 defm BUFFER_STORE_DWORD : MUBUF_Store_Helper <
882 0x0000001c, "BUFFER_STORE_DWORD", VReg_32, i32, global_store
885 defm BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper <
886 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64, v2i32, global_store
889 defm BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper <
890 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128, v4i32, global_store
892 //def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>;
893 //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>;
894 //def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>;
895 //def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>;
896 //def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>;
897 //def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>;
898 //def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>;
899 //def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>;
900 //def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>;
901 //def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>;
902 //def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>;
903 //def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>;
904 //def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>;
905 //def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>;
906 //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>;
907 //def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>;
908 //def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>;
909 //def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>;
910 //def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>;
911 //def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>;
912 //def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>;
913 //def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>;
914 //def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>;
915 //def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>;
916 //def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>;
917 //def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>;
918 //def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>;
919 //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>;
920 //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>;
921 //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>;
922 //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>;
923 //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>;
924 //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>;
925 //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>;
926 //def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>;
927 //def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>;
929 //===----------------------------------------------------------------------===//
930 // MTBUF Instructions
931 //===----------------------------------------------------------------------===//
933 //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>;
934 //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>;
935 //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>;
936 def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>;
937 def TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "TBUFFER_STORE_FORMAT_X", VReg_32>;
938 def TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FORMAT_XY", VReg_64>;
939 def TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>;
940 def TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>;
942 //===----------------------------------------------------------------------===//
944 //===----------------------------------------------------------------------===//
946 defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "IMAGE_LOAD">;
947 defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "IMAGE_LOAD_MIP">;
948 //def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>;
949 //def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>;
950 //def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>;
951 //def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>;
952 //def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>;
953 //def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>;
954 //def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>;
955 //def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>;
956 defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "IMAGE_GET_RESINFO">;
957 //def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>;
958 //def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>;
959 //def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>;
960 //def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>;
961 //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>;
962 //def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>;
963 //def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>;
964 //def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>;
965 //def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>;
966 //def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>;
967 //def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>;
968 //def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>;
969 //def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>;
970 //def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>;
971 //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>;
972 //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>;
973 //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>;
974 defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">;
975 defm IMAGE_SAMPLE_CL : MIMG_Sampler <0x00000021, "IMAGE_SAMPLE_CL">;
976 defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">;
977 defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, "IMAGE_SAMPLE_D_CL">;
978 defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">;
979 defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">;
980 defm IMAGE_SAMPLE_B_CL : MIMG_Sampler <0x00000026, "IMAGE_SAMPLE_B_CL">;
981 defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, "IMAGE_SAMPLE_LZ">;
982 defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">;
983 defm IMAGE_SAMPLE_C_CL : MIMG_Sampler <0x00000029, "IMAGE_SAMPLE_C_CL">;
984 defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">;
985 defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, "IMAGE_SAMPLE_C_D_CL">;
986 defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">;
987 defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">;
988 defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler <0x0000002e, "IMAGE_SAMPLE_C_B_CL">;
989 defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, "IMAGE_SAMPLE_C_LZ">;
990 defm IMAGE_SAMPLE_O : MIMG_Sampler <0x00000030, "IMAGE_SAMPLE_O">;
991 defm IMAGE_SAMPLE_CL_O : MIMG_Sampler <0x00000031, "IMAGE_SAMPLE_CL_O">;
992 defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, "IMAGE_SAMPLE_D_O">;
993 defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, "IMAGE_SAMPLE_D_CL_O">;
994 defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, "IMAGE_SAMPLE_L_O">;
995 defm IMAGE_SAMPLE_B_O : MIMG_Sampler <0x00000035, "IMAGE_SAMPLE_B_O">;
996 defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler <0x00000036, "IMAGE_SAMPLE_B_CL_O">;
997 defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, "IMAGE_SAMPLE_LZ_O">;
998 defm IMAGE_SAMPLE_C_O : MIMG_Sampler <0x00000038, "IMAGE_SAMPLE_C_O">;
999 defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler <0x00000039, "IMAGE_SAMPLE_C_CL_O">;
1000 defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, "IMAGE_SAMPLE_C_D_O">;
1001 defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, "IMAGE_SAMPLE_C_D_CL_O">;
1002 defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, "IMAGE_SAMPLE_C_L_O">;
1003 defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler <0x0000003d, "IMAGE_SAMPLE_C_B_O">;
1004 defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler <0x0000003e, "IMAGE_SAMPLE_C_B_CL_O">;
1005 defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, "IMAGE_SAMPLE_C_LZ_O">;
1006 defm IMAGE_GATHER4 : MIMG_Gather <0x00000040, "IMAGE_GATHER4">;
1007 defm IMAGE_GATHER4_CL : MIMG_Gather <0x00000041, "IMAGE_GATHER4_CL">;
1008 defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, "IMAGE_GATHER4_L">;
1009 defm IMAGE_GATHER4_B : MIMG_Gather <0x00000045, "IMAGE_GATHER4_B">;
1010 defm IMAGE_GATHER4_B_CL : MIMG_Gather <0x00000046, "IMAGE_GATHER4_B_CL">;
1011 defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, "IMAGE_GATHER4_LZ">;
1012 defm IMAGE_GATHER4_C : MIMG_Gather <0x00000048, "IMAGE_GATHER4_C">;
1013 defm IMAGE_GATHER4_C_CL : MIMG_Gather <0x00000049, "IMAGE_GATHER4_C_CL">;
1014 defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, "IMAGE_GATHER4_C_L">;
1015 defm IMAGE_GATHER4_C_B : MIMG_Gather <0x0000004d, "IMAGE_GATHER4_C_B">;
1016 defm IMAGE_GATHER4_C_B_CL : MIMG_Gather <0x0000004e, "IMAGE_GATHER4_C_B_CL">;
1017 defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, "IMAGE_GATHER4_C_LZ">;
1018 defm IMAGE_GATHER4_O : MIMG_Gather <0x00000050, "IMAGE_GATHER4_O">;
1019 defm IMAGE_GATHER4_CL_O : MIMG_Gather <0x00000051, "IMAGE_GATHER4_CL_O">;
1020 defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, "IMAGE_GATHER4_L_O">;
1021 defm IMAGE_GATHER4_B_O : MIMG_Gather <0x00000055, "IMAGE_GATHER4_B_O">;
1022 defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, "IMAGE_GATHER4_B_CL_O">;
1023 defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, "IMAGE_GATHER4_LZ_O">;
1024 defm IMAGE_GATHER4_C_O : MIMG_Gather <0x00000058, "IMAGE_GATHER4_C_O">;
1025 defm IMAGE_GATHER4_C_CL_O : MIMG_Gather <0x00000059, "IMAGE_GATHER4_C_CL_O">;
1026 defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, "IMAGE_GATHER4_C_L_O">;
1027 defm IMAGE_GATHER4_C_B_O : MIMG_Gather <0x0000005d, "IMAGE_GATHER4_C_B_O">;
1028 defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather <0x0000005e, "IMAGE_GATHER4_C_B_CL_O">;
1029 defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, "IMAGE_GATHER4_C_LZ_O">;
1030 defm IMAGE_GET_LOD : MIMG_Sampler <0x00000060, "IMAGE_GET_LOD">;
1031 defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, "IMAGE_SAMPLE_CD">;
1032 defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, "IMAGE_SAMPLE_CD_CL">;
1033 defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, "IMAGE_SAMPLE_C_CD">;
1034 defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, "IMAGE_SAMPLE_C_CD_CL">;
1035 defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, "IMAGE_SAMPLE_CD_O">;
1036 defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, "IMAGE_SAMPLE_CD_CL_O">;
1037 defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, "IMAGE_SAMPLE_C_CD_O">;
1038 defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, "IMAGE_SAMPLE_C_CD_CL_O">;
1039 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>;
1040 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>;
1042 //===----------------------------------------------------------------------===//
1043 // VOP1 Instructions
1044 //===----------------------------------------------------------------------===//
1046 //def V_NOP : VOP1_ <0x00000000, "V_NOP", []>;
1048 let isMoveImm = 1 in {
1049 defm V_MOV_B32 : VOP1Inst <0x00000001, "V_MOV_B32", VOP_I32_I32>;
1050 } // End isMoveImm = 1
1052 let Uses = [EXEC] in {
1054 def V_READFIRSTLANE_B32 : VOP1 <
1056 (outs SReg_32:$vdst),
1057 (ins VReg_32:$src0),
1058 "V_READFIRSTLANE_B32 $vdst, $src0",
1064 defm V_CVT_I32_F64 : VOP1Inst <0x00000003, "V_CVT_I32_F64",
1065 VOP_I32_F64, fp_to_sint
1067 defm V_CVT_F64_I32 : VOP1Inst <0x00000004, "V_CVT_F64_I32",
1068 VOP_F64_I32, sint_to_fp
1070 defm V_CVT_F32_I32 : VOP1Inst <0x00000005, "V_CVT_F32_I32",
1071 VOP_F32_I32, sint_to_fp
1073 defm V_CVT_F32_U32 : VOP1Inst <0x00000006, "V_CVT_F32_U32",
1074 VOP_F32_I32, uint_to_fp
1076 defm V_CVT_U32_F32 : VOP1Inst <0x00000007, "V_CVT_U32_F32",
1077 VOP_I32_F32, fp_to_uint
1079 defm V_CVT_I32_F32 : VOP1Inst <0x00000008, "V_CVT_I32_F32",
1080 VOP_I32_F32, fp_to_sint
1082 defm V_MOV_FED_B32 : VOP1Inst <0x00000009, "V_MOV_FED_B32", VOP_I32_I32>;
1083 defm V_CVT_F16_F32 : VOP1Inst <0x0000000a, "V_CVT_F16_F32",
1084 VOP_I32_F32, fp_to_f16
1086 defm V_CVT_F32_F16 : VOP1Inst <0x0000000b, "V_CVT_F32_F16",
1087 VOP_F32_I32, f16_to_fp
1089 //defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>;
1090 //defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>;
1091 //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>;
1092 defm V_CVT_F32_F64 : VOP1Inst <0x0000000f, "V_CVT_F32_F64",
1095 defm V_CVT_F64_F32 : VOP1Inst <0x00000010, "V_CVT_F64_F32",
1096 VOP_F64_F32, fextend
1098 defm V_CVT_F32_UBYTE0 : VOP1Inst <0x00000011, "V_CVT_F32_UBYTE0",
1099 VOP_F32_I32, AMDGPUcvt_f32_ubyte0
1101 defm V_CVT_F32_UBYTE1 : VOP1Inst <0x00000012, "V_CVT_F32_UBYTE1",
1102 VOP_F32_I32, AMDGPUcvt_f32_ubyte1
1104 defm V_CVT_F32_UBYTE2 : VOP1Inst <0x00000013, "V_CVT_F32_UBYTE2",
1105 VOP_F32_I32, AMDGPUcvt_f32_ubyte2
1107 defm V_CVT_F32_UBYTE3 : VOP1Inst <0x00000014, "V_CVT_F32_UBYTE3",
1108 VOP_F32_I32, AMDGPUcvt_f32_ubyte3
1110 defm V_CVT_U32_F64 : VOP1Inst <0x00000015, "V_CVT_U32_F64",
1111 VOP_I32_F64, fp_to_uint
1113 defm V_CVT_F64_U32 : VOP1Inst <0x00000016, "V_CVT_F64_U32",
1114 VOP_F64_I32, uint_to_fp
1117 defm V_FRACT_F32 : VOP1Inst <0x00000020, "V_FRACT_F32",
1118 VOP_F32_F32, AMDGPUfract
1120 defm V_TRUNC_F32 : VOP1Inst <0x00000021, "V_TRUNC_F32",
1123 defm V_CEIL_F32 : VOP1Inst <0x00000022, "V_CEIL_F32",
1126 defm V_RNDNE_F32 : VOP1Inst <0x00000023, "V_RNDNE_F32",
1129 defm V_FLOOR_F32 : VOP1Inst <0x00000024, "V_FLOOR_F32",
1132 defm V_EXP_F32 : VOP1Inst <0x00000025, "V_EXP_F32",
1135 defm V_LOG_CLAMP_F32 : VOP1Inst <0x00000026, "V_LOG_CLAMP_F32", VOP_F32_F32>;
1136 defm V_LOG_F32 : VOP1Inst <0x00000027, "V_LOG_F32",
1140 defm V_RCP_CLAMP_F32 : VOP1Inst <0x00000028, "V_RCP_CLAMP_F32", VOP_F32_F32>;
1141 defm V_RCP_LEGACY_F32 : VOP1Inst <0x00000029, "V_RCP_LEGACY_F32", VOP_F32_F32>;
1142 defm V_RCP_F32 : VOP1Inst <0x0000002a, "V_RCP_F32",
1143 VOP_F32_F32, AMDGPUrcp
1145 defm V_RCP_IFLAG_F32 : VOP1Inst <0x0000002b, "V_RCP_IFLAG_F32", VOP_F32_F32>;
1146 defm V_RSQ_CLAMP_F32 : VOP1Inst <0x0000002c, "V_RSQ_CLAMP_F32",
1147 VOP_F32_F32, AMDGPUrsq_clamped
1149 defm V_RSQ_LEGACY_F32 : VOP1Inst <
1150 0x0000002d, "V_RSQ_LEGACY_F32",
1151 VOP_F32_F32, AMDGPUrsq_legacy
1153 defm V_RSQ_F32 : VOP1Inst <0x0000002e, "V_RSQ_F32",
1154 VOP_F32_F32, AMDGPUrsq
1156 defm V_RCP_F64 : VOP1Inst <0x0000002f, "V_RCP_F64",
1157 VOP_F64_F64, AMDGPUrcp
1159 defm V_RCP_CLAMP_F64 : VOP1Inst <0x00000030, "V_RCP_CLAMP_F64", VOP_F64_F64>;
1160 defm V_RSQ_F64 : VOP1Inst <0x00000031, "V_RSQ_F64",
1161 VOP_F64_F64, AMDGPUrsq
1163 defm V_RSQ_CLAMP_F64 : VOP1Inst <0x00000032, "V_RSQ_CLAMP_F64",
1164 VOP_F64_F64, AMDGPUrsq_clamped
1166 defm V_SQRT_F32 : VOP1Inst <0x00000033, "V_SQRT_F32",
1169 defm V_SQRT_F64 : VOP1Inst <0x00000034, "V_SQRT_F64",
1172 defm V_SIN_F32 : VOP1Inst <0x00000035, "V_SIN_F32",
1173 VOP_F32_F32, AMDGPUsin
1175 defm V_COS_F32 : VOP1Inst <0x00000036, "V_COS_F32",
1176 VOP_F32_F32, AMDGPUcos
1178 defm V_NOT_B32 : VOP1Inst <0x00000037, "V_NOT_B32", VOP_I32_I32>;
1179 defm V_BFREV_B32 : VOP1Inst <0x00000038, "V_BFREV_B32", VOP_I32_I32>;
1180 defm V_FFBH_U32 : VOP1Inst <0x00000039, "V_FFBH_U32", VOP_I32_I32>;
1181 defm V_FFBL_B32 : VOP1Inst <0x0000003a, "V_FFBL_B32", VOP_I32_I32>;
1182 defm V_FFBH_I32 : VOP1Inst <0x0000003b, "V_FFBH_I32", VOP_I32_I32>;
1183 //defm V_FREXP_EXP_I32_F64 : VOPInst <0x0000003c, "V_FREXP_EXP_I32_F64", VOP_I32_F32>;
1184 defm V_FREXP_MANT_F64 : VOP1Inst <0x0000003d, "V_FREXP_MANT_F64", VOP_F64_F64>;
1185 defm V_FRACT_F64 : VOP1Inst <0x0000003e, "V_FRACT_F64", VOP_F64_F64>;
1186 //defm V_FREXP_EXP_I32_F32 : VOPInst <0x0000003f, "V_FREXP_EXP_I32_F32", VOP_I32_F32>;
1187 defm V_FREXP_MANT_F32 : VOP1Inst <0x00000040, "V_FREXP_MANT_F32", VOP_F32_F32>;
1188 //def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>;
1189 defm V_MOVRELD_B32 : VOP1Inst <0x00000042, "V_MOVRELD_B32", VOP_I32_I32>;
1190 defm V_MOVRELS_B32 : VOP1Inst <0x00000043, "V_MOVRELS_B32", VOP_I32_I32>;
1191 defm V_MOVRELSD_B32 : VOP1Inst <0x00000044, "V_MOVRELSD_B32", VOP_I32_I32>;
1194 //===----------------------------------------------------------------------===//
1195 // VINTRP Instructions
1196 //===----------------------------------------------------------------------===//
1198 def V_INTERP_P1_F32 : VINTRP <
1200 (outs VReg_32:$dst),
1201 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1202 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]",
1204 let DisableEncoding = "$m0";
1207 def V_INTERP_P2_F32 : VINTRP <
1209 (outs VReg_32:$dst),
1210 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1211 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]",
1214 let Constraints = "$src0 = $dst";
1215 let DisableEncoding = "$src0,$m0";
1219 def V_INTERP_MOV_F32 : VINTRP <
1221 (outs VReg_32:$dst),
1222 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1223 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]",
1225 let DisableEncoding = "$m0";
1228 //===----------------------------------------------------------------------===//
1229 // VOP2 Instructions
1230 //===----------------------------------------------------------------------===//
1232 def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
1233 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc),
1234 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]",
1237 let DisableEncoding = "$vcc";
1240 def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst),
1241 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2,
1242 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
1243 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg",
1244 [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))]
1246 let src0_modifiers = 0;
1247 let src1_modifiers = 0;
1248 let src2_modifiers = 0;
1251 def V_READLANE_B32 : VOP2 <
1253 (outs SReg_32:$vdst),
1254 (ins VReg_32:$src0, SSrc_32:$vsrc1),
1255 "V_READLANE_B32 $vdst, $src0, $vsrc1",
1259 def V_WRITELANE_B32 : VOP2 <
1261 (outs VReg_32:$vdst),
1262 (ins SReg_32:$src0, SSrc_32:$vsrc1),
1263 "V_WRITELANE_B32 $vdst, $src0, $vsrc1",
1267 let isCommutable = 1 in {
1268 defm V_ADD_F32 : VOP2Inst <0x00000003, "V_ADD_F32",
1269 VOP_F32_F32_F32, fadd
1272 defm V_SUB_F32 : VOP2Inst <0x00000004, "V_SUB_F32", VOP_F32_F32_F32, fsub>;
1273 defm V_SUBREV_F32 : VOP2Inst <0x00000005, "V_SUBREV_F32",
1274 VOP_F32_F32_F32, null_frag, "V_SUB_F32"
1276 } // End isCommutable = 1
1278 defm V_MAC_LEGACY_F32 : VOP2Inst <0x00000006, "V_MAC_LEGACY_F32",
1282 let isCommutable = 1 in {
1284 defm V_MUL_LEGACY_F32 : VOP2Inst <
1285 0x00000007, "V_MUL_LEGACY_F32",
1286 VOP_F32_F32_F32, int_AMDGPU_mul
1289 defm V_MUL_F32 : VOP2Inst <0x00000008, "V_MUL_F32",
1290 VOP_F32_F32_F32, fmul
1294 defm V_MUL_I32_I24 : VOP2Inst <0x00000009, "V_MUL_I32_I24",
1295 VOP_I32_I32_I32, AMDGPUmul_i24
1297 //defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>;
1298 defm V_MUL_U32_U24 : VOP2Inst <0x0000000b, "V_MUL_U32_U24",
1299 VOP_I32_I32_I32, AMDGPUmul_u24
1301 //defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>;
1304 defm V_MIN_LEGACY_F32 : VOP2Inst <0x0000000d, "V_MIN_LEGACY_F32",
1305 VOP_F32_F32_F32, AMDGPUfmin
1308 defm V_MAX_LEGACY_F32 : VOP2Inst <0x0000000e, "V_MAX_LEGACY_F32",
1309 VOP_F32_F32_F32, AMDGPUfmax
1312 defm V_MIN_F32 : VOP2Inst <0x0000000f, "V_MIN_F32", VOP_F32_F32_F32>;
1313 defm V_MAX_F32 : VOP2Inst <0x00000010, "V_MAX_F32", VOP_F32_F32_F32>;
1314 defm V_MIN_I32 : VOP2Inst <0x00000011, "V_MIN_I32", VOP_I32_I32_I32, AMDGPUsmin>;
1315 defm V_MAX_I32 : VOP2Inst <0x00000012, "V_MAX_I32", VOP_I32_I32_I32, AMDGPUsmax>;
1316 defm V_MIN_U32 : VOP2Inst <0x00000013, "V_MIN_U32", VOP_I32_I32_I32, AMDGPUumin>;
1317 defm V_MAX_U32 : VOP2Inst <0x00000014, "V_MAX_U32", VOP_I32_I32_I32, AMDGPUumax>;
1319 defm V_LSHR_B32 : VOP2Inst <0x00000015, "V_LSHR_B32", VOP_I32_I32_I32, srl>;
1321 defm V_LSHRREV_B32 : VOP2Inst <
1322 0x00000016, "V_LSHRREV_B32", VOP_I32_I32_I32, null_frag, "V_LSHR_B32"
1325 defm V_ASHR_I32 : VOP2Inst <0x00000017, "V_ASHR_I32",
1326 VOP_I32_I32_I32, sra
1328 defm V_ASHRREV_I32 : VOP2Inst <
1329 0x00000018, "V_ASHRREV_I32", VOP_I32_I32_I32, null_frag, "V_ASHR_I32"
1332 let hasPostISelHook = 1 in {
1334 defm V_LSHL_B32 : VOP2Inst <0x00000019, "V_LSHL_B32", VOP_I32_I32_I32, shl>;
1337 defm V_LSHLREV_B32 : VOP2Inst <
1338 0x0000001a, "V_LSHLREV_B32", VOP_I32_I32_I32, null_frag, "V_LSHL_B32"
1341 defm V_AND_B32 : VOP2Inst <0x0000001b, "V_AND_B32",
1342 VOP_I32_I32_I32, and>;
1343 defm V_OR_B32 : VOP2Inst <0x0000001c, "V_OR_B32",
1346 defm V_XOR_B32 : VOP2Inst <0x0000001d, "V_XOR_B32",
1347 VOP_I32_I32_I32, xor
1350 } // End isCommutable = 1
1352 defm V_BFM_B32 : VOP2Inst <0x0000001e, "V_BFM_B32",
1353 VOP_I32_I32_I32, AMDGPUbfm>;
1354 defm V_MAC_F32 : VOP2Inst <0x0000001f, "V_MAC_F32", VOP_F32_F32_F32>;
1355 defm V_MADMK_F32 : VOP2Inst <0x00000020, "V_MADMK_F32", VOP_F32_F32_F32>;
1356 defm V_MADAK_F32 : VOP2Inst <0x00000021, "V_MADAK_F32", VOP_F32_F32_F32>;
1357 defm V_BCNT_U32_B32 : VOP2Inst <0x00000022, "V_BCNT_U32_B32", VOP_I32_I32_I32>;
1358 defm V_MBCNT_LO_U32_B32 : VOP2Inst <0x00000023, "V_MBCNT_LO_U32_B32",
1361 defm V_MBCNT_HI_U32_B32 : VOP2Inst <0x00000024, "V_MBCNT_HI_U32_B32",
1365 let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC
1366 // No patterns so that the scalar instructions are always selected.
1367 // The scalar versions will be replaced with vector when needed later.
1368 defm V_ADD_I32 : VOP2bInst <0x00000025, "V_ADD_I32",
1369 VOP_I32_I32_I32, add
1371 defm V_SUB_I32 : VOP2bInst <0x00000026, "V_SUB_I32",
1372 VOP_I32_I32_I32, sub
1374 defm V_SUBREV_I32 : VOP2bInst <0x00000027, "V_SUBREV_I32",
1375 VOP_I32_I32_I32, null_frag, "V_SUB_I32"
1378 let Uses = [VCC] in { // Carry-in comes from VCC
1379 defm V_ADDC_U32 : VOP2bInst <0x00000028, "V_ADDC_U32",
1380 VOP_I32_I32_I32_VCC, adde
1382 defm V_SUBB_U32 : VOP2bInst <0x00000029, "V_SUBB_U32",
1383 VOP_I32_I32_I32_VCC, sube
1385 defm V_SUBBREV_U32 : VOP2bInst <0x0000002a, "V_SUBBREV_U32",
1386 VOP_I32_I32_I32_VCC, null_frag, "V_SUBB_U32"
1389 } // End Uses = [VCC]
1390 } // End isCommutable = 1, Defs = [VCC]
1392 defm V_LDEXP_F32 : VOP2Inst <0x0000002b, "V_LDEXP_F32",
1395 ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>;
1396 ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>;
1397 ////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>;
1398 defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <0x0000002f, "V_CVT_PKRTZ_F16_F32",
1399 VOP_I32_F32_F32, int_SI_packf16
1401 ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>;
1402 ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>;
1404 //===----------------------------------------------------------------------===//
1405 // VOP3 Instructions
1406 //===----------------------------------------------------------------------===//
1408 defm V_MAD_LEGACY_F32 : VOP3Inst <0x00000140, "V_MAD_LEGACY_F32",
1411 defm V_MAD_F32 : VOP3Inst <0x00000141, "V_MAD_F32",
1412 VOP_F32_F32_F32_F32, fmad
1414 defm V_MAD_I32_I24 : VOP3Inst <0x00000142, "V_MAD_I32_I24",
1415 VOP_I32_I32_I32_I32, AMDGPUmad_i24
1417 defm V_MAD_U32_U24 : VOP3Inst <0x00000143, "V_MAD_U32_U24",
1418 VOP_I32_I32_I32_I32, AMDGPUmad_u24
1421 defm V_CUBEID_F32 : VOP3Inst <0x00000144, "V_CUBEID_F32",
1424 defm V_CUBESC_F32 : VOP3Inst <0x00000145, "V_CUBESC_F32",
1427 defm V_CUBETC_F32 : VOP3Inst <0x00000146, "V_CUBETC_F32",
1430 defm V_CUBEMA_F32 : VOP3Inst <0x00000147, "V_CUBEMA_F32",
1434 let neverHasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
1435 defm V_BFE_U32 : VOP3Inst <0x00000148, "V_BFE_U32",
1436 VOP_I32_I32_I32_I32, AMDGPUbfe_u32
1438 defm V_BFE_I32 : VOP3Inst <0x00000149, "V_BFE_I32",
1439 VOP_I32_I32_I32_I32, AMDGPUbfe_i32
1443 defm V_BFI_B32 : VOP3Inst <0x0000014a, "V_BFI_B32",
1444 VOP_I32_I32_I32_I32, AMDGPUbfi
1446 defm V_FMA_F32 : VOP3Inst <0x0000014b, "V_FMA_F32",
1447 VOP_F32_F32_F32_F32, fma
1449 defm V_FMA_F64 : VOP3Inst <0x0000014c, "V_FMA_F64",
1450 VOP_F64_F64_F64_F64, fma
1452 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>;
1453 defm V_ALIGNBIT_B32 : VOP3Inst <0x0000014e, "V_ALIGNBIT_B32",
1456 defm V_ALIGNBYTE_B32 : VOP3Inst <0x0000014f, "V_ALIGNBYTE_B32",
1459 defm V_MULLIT_F32 : VOP3Inst <0x00000150, "V_MULLIT_F32",
1460 VOP_F32_F32_F32_F32>;
1461 ////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>;
1462 ////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>;
1463 ////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>;
1464 ////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>;
1465 ////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>;
1466 ////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>;
1467 ////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>;
1468 ////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>;
1469 ////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>;
1470 //def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>;
1471 //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>;
1472 //def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>;
1473 defm V_SAD_U32 : VOP3Inst <0x0000015d, "V_SAD_U32",
1476 ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>;
1477 defm V_DIV_FIXUP_F32 : VOP3Inst <
1478 0x0000015f, "V_DIV_FIXUP_F32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup
1480 defm V_DIV_FIXUP_F64 : VOP3Inst <
1481 0x00000160, "V_DIV_FIXUP_F64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup
1484 defm V_LSHL_B64 : VOP3Inst <0x00000161, "V_LSHL_B64",
1485 VOP_I64_I64_I32, shl
1487 defm V_LSHR_B64 : VOP3Inst <0x00000162, "V_LSHR_B64",
1488 VOP_I64_I64_I32, srl
1490 defm V_ASHR_I64 : VOP3Inst <0x00000163, "V_ASHR_I64",
1491 VOP_I64_I64_I32, sra
1494 let isCommutable = 1 in {
1496 defm V_ADD_F64 : VOP3Inst <0x00000164, "V_ADD_F64",
1497 VOP_F64_F64_F64, fadd
1499 defm V_MUL_F64 : VOP3Inst <0x00000165, "V_MUL_F64",
1500 VOP_F64_F64_F64, fmul
1502 defm V_MIN_F64 : VOP3Inst <0x00000166, "V_MIN_F64",
1505 defm V_MAX_F64 : VOP3Inst <0x00000167, "V_MAX_F64",
1509 } // isCommutable = 1
1511 defm V_LDEXP_F64 : VOP3Inst <0x00000168, "V_LDEXP_F64",
1515 let isCommutable = 1 in {
1517 defm V_MUL_LO_U32 : VOP3Inst <0x00000169, "V_MUL_LO_U32",
1520 defm V_MUL_HI_U32 : VOP3Inst <0x0000016a, "V_MUL_HI_U32",
1523 defm V_MUL_LO_I32 : VOP3Inst <0x0000016b, "V_MUL_LO_I32",
1526 defm V_MUL_HI_I32 : VOP3Inst <0x0000016c, "V_MUL_HI_I32",
1530 } // isCommutable = 1
1532 defm V_DIV_SCALE_F32 : VOP3b_32 <0x0000016d, "V_DIV_SCALE_F32", []>;
1534 // Double precision division pre-scale.
1535 defm V_DIV_SCALE_F64 : VOP3b_64 <0x0000016e, "V_DIV_SCALE_F64", []>;
1537 defm V_DIV_FMAS_F32 : VOP3Inst <0x0000016f, "V_DIV_FMAS_F32",
1538 VOP_F32_F32_F32_F32, AMDGPUdiv_fmas
1540 defm V_DIV_FMAS_F64 : VOP3Inst <0x00000170, "V_DIV_FMAS_F64",
1541 VOP_F64_F64_F64_F64, AMDGPUdiv_fmas
1543 //def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>;
1544 //def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>;
1545 //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>;
1546 defm V_TRIG_PREOP_F64 : VOP3Inst <
1547 0x00000174, "V_TRIG_PREOP_F64", VOP_F64_F64_I32, AMDGPUtrig_preop
1550 //===----------------------------------------------------------------------===//
1551 // Pseudo Instructions
1552 //===----------------------------------------------------------------------===//
1554 let isCodeGenOnly = 1, isPseudo = 1 in {
1556 def V_MOV_I1 : InstSI <
1559 "", [(set i1:$dst, (imm:$src))]
1562 def V_AND_I1 : InstSI <
1563 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1564 [(set i1:$dst, (and i1:$src0, i1:$src1))]
1567 def V_OR_I1 : InstSI <
1568 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1569 [(set i1:$dst, (or i1:$src0, i1:$src1))]
1572 def V_XOR_I1 : InstSI <
1573 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1574 [(set i1:$dst, (xor i1:$src0, i1:$src1))]
1577 // SI pseudo instructions. These are used by the CFG structurizer pass
1578 // and should be lowered to ISA instructions prior to codegen.
1580 let mayLoad = 1, mayStore = 1, hasSideEffects = 1,
1581 Uses = [EXEC], Defs = [EXEC] in {
1583 let isBranch = 1, isTerminator = 1 in {
1586 (outs SReg_64:$dst),
1587 (ins SReg_64:$vcc, brtarget:$target),
1589 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))]
1592 def SI_ELSE : InstSI <
1593 (outs SReg_64:$dst),
1594 (ins SReg_64:$src, brtarget:$target),
1596 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]
1598 let Constraints = "$src = $dst";
1601 def SI_LOOP : InstSI <
1603 (ins SReg_64:$saved, brtarget:$target),
1604 "SI_LOOP $saved, $target",
1605 [(int_SI_loop i64:$saved, bb:$target)]
1608 } // end isBranch = 1, isTerminator = 1
1610 def SI_BREAK : InstSI <
1611 (outs SReg_64:$dst),
1613 "SI_ELSE $dst, $src",
1614 [(set i64:$dst, (int_SI_break i64:$src))]
1617 def SI_IF_BREAK : InstSI <
1618 (outs SReg_64:$dst),
1619 (ins SReg_64:$vcc, SReg_64:$src),
1620 "SI_IF_BREAK $dst, $vcc, $src",
1621 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))]
1624 def SI_ELSE_BREAK : InstSI <
1625 (outs SReg_64:$dst),
1626 (ins SReg_64:$src0, SReg_64:$src1),
1627 "SI_ELSE_BREAK $dst, $src0, $src1",
1628 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))]
1631 def SI_END_CF : InstSI <
1633 (ins SReg_64:$saved),
1635 [(int_SI_end_cf i64:$saved)]
1638 def SI_KILL : InstSI <
1642 [(int_AMDGPU_kill f32:$src)]
1645 } // end mayLoad = 1, mayStore = 1, hasSideEffects = 1
1646 // Uses = [EXEC], Defs = [EXEC]
1648 let Uses = [EXEC], Defs = [EXEC,VCC,M0] in {
1650 //defm SI_ : RegisterLoadStore <VReg_32, FRAMEri, ADDRIndirect>;
1652 let UseNamedOperandTable = 1 in {
1654 def SI_RegisterLoad : InstSI <
1655 (outs VReg_32:$dst, SReg_64:$temp),
1656 (ins FRAMEri32:$addr, i32imm:$chan),
1659 let isRegisterLoad = 1;
1663 class SIRegStore<dag outs> : InstSI <
1665 (ins VReg_32:$val, FRAMEri32:$addr, i32imm:$chan),
1668 let isRegisterStore = 1;
1672 let usesCustomInserter = 1 in {
1673 def SI_RegisterStorePseudo : SIRegStore<(outs)>;
1674 } // End usesCustomInserter = 1
1675 def SI_RegisterStore : SIRegStore<(outs SReg_64:$temp)>;
1678 } // End UseNamedOperandTable = 1
1680 def SI_INDIRECT_SRC : InstSI <
1681 (outs VReg_32:$dst, SReg_64:$temp),
1682 (ins unknown:$src, VSrc_32:$idx, i32imm:$off),
1683 "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off",
1687 class SI_INDIRECT_DST<RegisterClass rc> : InstSI <
1688 (outs rc:$dst, SReg_64:$temp),
1689 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val),
1690 "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val",
1693 let Constraints = "$src = $dst";
1696 def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VReg_32>;
1697 def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
1698 def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
1699 def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
1700 def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
1702 } // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0]
1704 let usesCustomInserter = 1 in {
1706 // This pseudo instruction takes a pointer as input and outputs a resource
1707 // constant that can be used with the ADDR64 MUBUF instructions.
1708 def SI_ADDR64_RSRC : InstSI <
1709 (outs SReg_128:$srsrc),
1714 def SI_BUFFER_RSRC : InstSI <
1715 (outs SReg_128:$srsrc),
1716 (ins SReg_32:$ptr_lo, SReg_32:$ptr_hi, SSrc_32:$data_lo, SSrc_32:$data_hi),
1720 def V_SUB_F64 : InstSI <
1721 (outs VReg_64:$dst),
1722 (ins VReg_64:$src0, VReg_64:$src1),
1723 "V_SUB_F64 $dst, $src0, $src1",
1724 [(set f64:$dst, (fsub f64:$src0, f64:$src1))]
1727 } // end usesCustomInserter
1729 multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
1731 def _SAVE : InstSI <
1732 (outs VReg_32:$dst),
1733 (ins sgpr_class:$src, i32imm:$frame_idx),
1737 def _RESTORE : InstSI <
1738 (outs sgpr_class:$dst),
1739 (ins VReg_32:$src, i32imm:$frame_idx),
1745 defm SI_SPILL_S32 : SI_SPILL_SGPR <SReg_32>;
1746 defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>;
1747 defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>;
1748 defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>;
1749 defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;
1751 let Defs = [SCC] in {
1753 def SI_CONSTDATA_PTR : InstSI <
1754 (outs SReg_64:$dst),
1756 "", [(set SReg_64:$dst, (i64 SIconstdata_ptr))]
1759 } // End Defs = [SCC]
1761 } // end IsCodeGenOnly, isPseudo
1763 } // end SubtargetPredicate = SI
1765 let Predicates = [isSI] in {
1768 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2),
1769 (V_CNDMASK_B32_e64 $src2, $src1,
1770 (V_CMP_GT_F32_e64 SRCMODS.NONE, 0, SRCMODS.NONE, $src0,
1771 DSTCLAMP.NONE, DSTOMOD.NONE))
1776 (SI_KILL 0xbf800000)
1779 /* int_SI_vs_load_input */
1781 (SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr),
1782 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0)
1787 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
1788 f32:$src0, f32:$src1, f32:$src2, f32:$src3),
1789 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
1790 $src0, $src1, $src2, $src3)
1793 //===----------------------------------------------------------------------===//
1795 //===----------------------------------------------------------------------===//
1797 multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
1799 // 1. Offset as 8bit DWORD immediate
1801 (constant_load (add i64:$sbase, (i64 IMM8bitDWORD:$offset))),
1802 (vt (Instr_IMM $sbase, (as_dword_i32imm $offset)))
1805 // 2. Offset loaded in an 32bit SGPR
1807 (constant_load (add i64:$sbase, (i64 IMM32bit:$offset))),
1808 (vt (Instr_SGPR $sbase, (S_MOV_B32 (i32 (as_i32imm $offset)))))
1811 // 3. No offset at all
1813 (constant_load i64:$sbase),
1814 (vt (Instr_IMM $sbase, 0))
1818 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>;
1819 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
1820 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>;
1821 defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>;
1822 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
1823 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>;
1824 defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
1826 // 1. Offset as 8bit DWORD immediate
1828 (SIload_constant v4i32:$sbase, IMM8bitDWORD:$offset),
1829 (S_BUFFER_LOAD_DWORD_IMM $sbase, (as_dword_i32imm $offset))
1832 // 2. Offset loaded in an 32bit SGPR
1834 (SIload_constant v4i32:$sbase, imm:$offset),
1835 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset))
1838 } // Predicates = [isSI] in {
1840 //===----------------------------------------------------------------------===//
1842 //===----------------------------------------------------------------------===//
1844 let Predicates = [isSI, isCFDepth0] in {
1847 (i64 (ctpop i64:$src)),
1848 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1849 (S_BCNT1_I32_B64 $src), sub0),
1850 (S_MOV_B32 0), sub1)
1853 //===----------------------------------------------------------------------===//
1855 //===----------------------------------------------------------------------===//
1857 // V_ADD_I32_e32/S_ADD_I32 produces carry in VCC/SCC. For the vector
1858 // case, the sgpr-copies pass will fix this to use the vector version.
1860 (i32 (addc i32:$src0, i32:$src1)),
1861 (S_ADD_I32 $src0, $src1)
1864 } // Predicates = [isSI, isCFDepth0]
1866 let Predicates = [isSI] in {
1868 //===----------------------------------------------------------------------===//
1870 //===----------------------------------------------------------------------===//
1873 (int_AMDGPU_barrier_global),
1877 //===----------------------------------------------------------------------===//
1879 //===----------------------------------------------------------------------===//
1881 let Predicates = [UnsafeFPMath] in {
1882 def : RcpPat<V_RCP_F64_e32, f64>;
1883 defm : RsqPat<V_RSQ_F64_e32, f64>;
1884 defm : RsqPat<V_RSQ_F32_e32, f32>;
1887 //===----------------------------------------------------------------------===//
1889 //===----------------------------------------------------------------------===//
1891 class BinOp64Pat <SDNode node, Instruction inst> : Pat <
1892 (node i64:$src0, i64:$src1),
1893 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1894 (inst (EXTRACT_SUBREG i64:$src0, sub0),
1895 (EXTRACT_SUBREG i64:$src1, sub0)), sub0),
1896 (inst (EXTRACT_SUBREG i64:$src0, sub1),
1897 (EXTRACT_SUBREG i64:$src1, sub1)), sub1)
1900 def : BinOp64Pat <or, V_OR_B32_e32>;
1901 def : BinOp64Pat <xor, V_XOR_B32_e32>;
1903 class SextInReg <ValueType vt, int ShiftAmt> : Pat <
1904 (sext_inreg i32:$src0, vt),
1905 (V_ASHRREV_I32_e32 ShiftAmt, (V_LSHLREV_B32_e32 ShiftAmt, $src0))
1908 def : SextInReg <i8, 24>;
1909 def : SextInReg <i16, 16>;
1912 (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)),
1913 (V_BCNT_U32_B32_e32 $popcnt, $val)
1917 (i32 (ctpop i32:$popcnt)),
1918 (V_BCNT_U32_B32_e64 $popcnt, 0)
1922 (i64 (ctpop i64:$src)),
1924 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1925 (V_BCNT_U32_B32_e32 (EXTRACT_SUBREG $src, sub1),
1926 (V_BCNT_U32_B32_e64 (EXTRACT_SUBREG $src, sub0), 0)),
1928 (V_MOV_B32_e32 0), sub1)
1932 (addc i32:$src0, i32:$src1),
1933 (V_ADD_I32_e32 $src0, $src1)
1936 /********** ======================= **********/
1937 /********** Image sampling patterns **********/
1938 /********** ======================= **********/
1941 class SampleRawPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
1942 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i32:$unorm,
1943 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
1944 (opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da),
1945 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc),
1946 $addr, $rsrc, $sampler)
1949 multiclass SampleRawPatterns<SDPatternOperator name, string opcode> {
1950 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
1951 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
1952 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
1953 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V8), v8i32>;
1954 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V16), v16i32>;
1958 class ImagePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
1959 (name vt:$addr, v8i32:$rsrc, i32:$dmask, i32:$unorm,
1960 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
1961 (opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da),
1962 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc),
1966 multiclass ImagePatterns<SDPatternOperator name, string opcode> {
1967 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
1968 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
1969 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
1973 defm : SampleRawPatterns<int_SI_image_sample, "IMAGE_SAMPLE">;
1974 defm : SampleRawPatterns<int_SI_image_sample_cl, "IMAGE_SAMPLE_CL">;
1975 defm : SampleRawPatterns<int_SI_image_sample_d, "IMAGE_SAMPLE_D">;
1976 defm : SampleRawPatterns<int_SI_image_sample_d_cl, "IMAGE_SAMPLE_D_CL">;
1977 defm : SampleRawPatterns<int_SI_image_sample_l, "IMAGE_SAMPLE_L">;
1978 defm : SampleRawPatterns<int_SI_image_sample_b, "IMAGE_SAMPLE_B">;
1979 defm : SampleRawPatterns<int_SI_image_sample_b_cl, "IMAGE_SAMPLE_B_CL">;
1980 defm : SampleRawPatterns<int_SI_image_sample_lz, "IMAGE_SAMPLE_LZ">;
1981 defm : SampleRawPatterns<int_SI_image_sample_cd, "IMAGE_SAMPLE_CD">;
1982 defm : SampleRawPatterns<int_SI_image_sample_cd_cl, "IMAGE_SAMPLE_CD_CL">;
1984 // Sample with comparison
1985 defm : SampleRawPatterns<int_SI_image_sample_c, "IMAGE_SAMPLE_C">;
1986 defm : SampleRawPatterns<int_SI_image_sample_c_cl, "IMAGE_SAMPLE_C_CL">;
1987 defm : SampleRawPatterns<int_SI_image_sample_c_d, "IMAGE_SAMPLE_C_D">;
1988 defm : SampleRawPatterns<int_SI_image_sample_c_d_cl, "IMAGE_SAMPLE_C_D_CL">;
1989 defm : SampleRawPatterns<int_SI_image_sample_c_l, "IMAGE_SAMPLE_C_L">;
1990 defm : SampleRawPatterns<int_SI_image_sample_c_b, "IMAGE_SAMPLE_C_B">;
1991 defm : SampleRawPatterns<int_SI_image_sample_c_b_cl, "IMAGE_SAMPLE_C_B_CL">;
1992 defm : SampleRawPatterns<int_SI_image_sample_c_lz, "IMAGE_SAMPLE_C_LZ">;
1993 defm : SampleRawPatterns<int_SI_image_sample_c_cd, "IMAGE_SAMPLE_C_CD">;
1994 defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl, "IMAGE_SAMPLE_C_CD_CL">;
1996 // Sample with offsets
1997 defm : SampleRawPatterns<int_SI_image_sample_o, "IMAGE_SAMPLE_O">;
1998 defm : SampleRawPatterns<int_SI_image_sample_cl_o, "IMAGE_SAMPLE_CL_O">;
1999 defm : SampleRawPatterns<int_SI_image_sample_d_o, "IMAGE_SAMPLE_D_O">;
2000 defm : SampleRawPatterns<int_SI_image_sample_d_cl_o, "IMAGE_SAMPLE_D_CL_O">;
2001 defm : SampleRawPatterns<int_SI_image_sample_l_o, "IMAGE_SAMPLE_L_O">;
2002 defm : SampleRawPatterns<int_SI_image_sample_b_o, "IMAGE_SAMPLE_B_O">;
2003 defm : SampleRawPatterns<int_SI_image_sample_b_cl_o, "IMAGE_SAMPLE_B_CL_O">;
2004 defm : SampleRawPatterns<int_SI_image_sample_lz_o, "IMAGE_SAMPLE_LZ_O">;
2005 defm : SampleRawPatterns<int_SI_image_sample_cd_o, "IMAGE_SAMPLE_CD_O">;
2006 defm : SampleRawPatterns<int_SI_image_sample_cd_cl_o, "IMAGE_SAMPLE_CD_CL_O">;
2008 // Sample with comparison and offsets
2009 defm : SampleRawPatterns<int_SI_image_sample_c_o, "IMAGE_SAMPLE_C_O">;
2010 defm : SampleRawPatterns<int_SI_image_sample_c_cl_o, "IMAGE_SAMPLE_C_CL_O">;
2011 defm : SampleRawPatterns<int_SI_image_sample_c_d_o, "IMAGE_SAMPLE_C_D_O">;
2012 defm : SampleRawPatterns<int_SI_image_sample_c_d_cl_o, "IMAGE_SAMPLE_C_D_CL_O">;
2013 defm : SampleRawPatterns<int_SI_image_sample_c_l_o, "IMAGE_SAMPLE_C_L_O">;
2014 defm : SampleRawPatterns<int_SI_image_sample_c_b_o, "IMAGE_SAMPLE_C_B_O">;
2015 defm : SampleRawPatterns<int_SI_image_sample_c_b_cl_o, "IMAGE_SAMPLE_C_B_CL_O">;
2016 defm : SampleRawPatterns<int_SI_image_sample_c_lz_o, "IMAGE_SAMPLE_C_LZ_O">;
2017 defm : SampleRawPatterns<int_SI_image_sample_c_cd_o, "IMAGE_SAMPLE_C_CD_O">;
2018 defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl_o, "IMAGE_SAMPLE_C_CD_CL_O">;
2021 // Only the variants which make sense are defined.
2022 def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V2, v2i32>;
2023 def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V4, v4i32>;
2024 def : SampleRawPattern<int_SI_gather4_cl, IMAGE_GATHER4_CL_V4_V4, v4i32>;
2025 def : SampleRawPattern<int_SI_gather4_l, IMAGE_GATHER4_L_V4_V4, v4i32>;
2026 def : SampleRawPattern<int_SI_gather4_b, IMAGE_GATHER4_B_V4_V4, v4i32>;
2027 def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V4, v4i32>;
2028 def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V8, v8i32>;
2029 def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V2, v2i32>;
2030 def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V4, v4i32>;
2032 def : SampleRawPattern<int_SI_gather4_c, IMAGE_GATHER4_C_V4_V4, v4i32>;
2033 def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V4, v4i32>;
2034 def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V8, v8i32>;
2035 def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V4, v4i32>;
2036 def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V8, v8i32>;
2037 def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V4, v4i32>;
2038 def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V8, v8i32>;
2039 def : SampleRawPattern<int_SI_gather4_c_b_cl, IMAGE_GATHER4_C_B_CL_V4_V8, v8i32>;
2040 def : SampleRawPattern<int_SI_gather4_c_lz, IMAGE_GATHER4_C_LZ_V4_V4, v4i32>;
2042 def : SampleRawPattern<int_SI_gather4_o, IMAGE_GATHER4_O_V4_V4, v4i32>;
2043 def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V4, v4i32>;
2044 def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V8, v8i32>;
2045 def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V4, v4i32>;
2046 def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V8, v8i32>;
2047 def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V4, v4i32>;
2048 def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V8, v8i32>;
2049 def : SampleRawPattern<int_SI_gather4_b_cl_o, IMAGE_GATHER4_B_CL_O_V4_V8, v8i32>;
2050 def : SampleRawPattern<int_SI_gather4_lz_o, IMAGE_GATHER4_LZ_O_V4_V4, v4i32>;
2052 def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V4, v4i32>;
2053 def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V8, v8i32>;
2054 def : SampleRawPattern<int_SI_gather4_c_cl_o, IMAGE_GATHER4_C_CL_O_V4_V8, v8i32>;
2055 def : SampleRawPattern<int_SI_gather4_c_l_o, IMAGE_GATHER4_C_L_O_V4_V8, v8i32>;
2056 def : SampleRawPattern<int_SI_gather4_c_b_o, IMAGE_GATHER4_C_B_O_V4_V8, v8i32>;
2057 def : SampleRawPattern<int_SI_gather4_c_b_cl_o, IMAGE_GATHER4_C_B_CL_O_V4_V8, v8i32>;
2058 def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V4, v4i32>;
2059 def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V8, v8i32>;
2061 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V1, i32>;
2062 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V2, v2i32>;
2063 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V4, v4i32>;
2065 def : ImagePattern<int_SI_getresinfo, IMAGE_GET_RESINFO_V4_V1, i32>;
2066 defm : ImagePatterns<int_SI_image_load, "IMAGE_LOAD">;
2067 defm : ImagePatterns<int_SI_image_load_mip, "IMAGE_LOAD_MIP">;
2069 /* SIsample for simple 1D texture lookup */
2071 (SIsample i32:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
2072 (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2075 class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
2076 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
2077 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2080 class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
2081 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_RECT),
2082 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2085 class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
2086 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_ARRAY),
2087 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2090 class SampleShadowPattern<SDNode name, MIMG opcode,
2091 ValueType vt> : Pat <
2092 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW),
2093 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2096 class SampleShadowArrayPattern<SDNode name, MIMG opcode,
2097 ValueType vt> : Pat <
2098 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
2099 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2102 /* SIsample* for texture lookups consuming more address parameters */
2103 multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l,
2104 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b,
2105 MIMG sample_d, MIMG sample_c_d, ValueType addr_type> {
2106 def : SamplePattern <SIsample, sample, addr_type>;
2107 def : SampleRectPattern <SIsample, sample, addr_type>;
2108 def : SampleArrayPattern <SIsample, sample, addr_type>;
2109 def : SampleShadowPattern <SIsample, sample_c, addr_type>;
2110 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>;
2112 def : SamplePattern <SIsamplel, sample_l, addr_type>;
2113 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>;
2114 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>;
2115 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>;
2117 def : SamplePattern <SIsampleb, sample_b, addr_type>;
2118 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>;
2119 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>;
2120 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>;
2122 def : SamplePattern <SIsampled, sample_d, addr_type>;
2123 def : SampleArrayPattern <SIsampled, sample_d, addr_type>;
2124 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>;
2125 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>;
2128 defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2,
2129 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2,
2130 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2,
2131 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2,
2133 defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4,
2134 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4,
2135 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4,
2136 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4,
2138 defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8,
2139 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8,
2140 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8,
2141 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8,
2143 defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16,
2144 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16,
2145 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16,
2146 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16,
2149 /* int_SI_imageload for texture fetches consuming varying address parameters */
2150 class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2151 (name addr_type:$addr, v32i8:$rsrc, imm),
2152 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
2155 class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2156 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY),
2157 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
2160 class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2161 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA),
2162 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
2165 class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2166 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA),
2167 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
2170 multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> {
2171 def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>;
2172 def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>;
2175 multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> {
2176 def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>;
2177 def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>;
2180 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V2, v2i32>;
2181 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V4, v4i32>;
2183 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V2, v2i32>;
2184 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V4, v4i32>;
2186 /* Image resource information */
2188 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm),
2189 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
2193 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY),
2194 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
2198 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA),
2199 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
2202 /********** ============================================ **********/
2203 /********** Extraction, Insertion, Building and Casting **********/
2204 /********** ============================================ **********/
2206 foreach Index = 0-2 in {
2207 def Extract_Element_v2i32_#Index : Extract_Element <
2208 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
2210 def Insert_Element_v2i32_#Index : Insert_Element <
2211 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
2214 def Extract_Element_v2f32_#Index : Extract_Element <
2215 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
2217 def Insert_Element_v2f32_#Index : Insert_Element <
2218 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
2222 foreach Index = 0-3 in {
2223 def Extract_Element_v4i32_#Index : Extract_Element <
2224 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
2226 def Insert_Element_v4i32_#Index : Insert_Element <
2227 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
2230 def Extract_Element_v4f32_#Index : Extract_Element <
2231 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
2233 def Insert_Element_v4f32_#Index : Insert_Element <
2234 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
2238 foreach Index = 0-7 in {
2239 def Extract_Element_v8i32_#Index : Extract_Element <
2240 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
2242 def Insert_Element_v8i32_#Index : Insert_Element <
2243 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
2246 def Extract_Element_v8f32_#Index : Extract_Element <
2247 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
2249 def Insert_Element_v8f32_#Index : Insert_Element <
2250 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
2254 foreach Index = 0-15 in {
2255 def Extract_Element_v16i32_#Index : Extract_Element <
2256 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
2258 def Insert_Element_v16i32_#Index : Insert_Element <
2259 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
2262 def Extract_Element_v16f32_#Index : Extract_Element <
2263 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
2265 def Insert_Element_v16f32_#Index : Insert_Element <
2266 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
2270 def : BitConvert <i32, f32, SReg_32>;
2271 def : BitConvert <i32, f32, VReg_32>;
2273 def : BitConvert <f32, i32, SReg_32>;
2274 def : BitConvert <f32, i32, VReg_32>;
2276 def : BitConvert <i64, f64, VReg_64>;
2278 def : BitConvert <f64, i64, VReg_64>;
2280 def : BitConvert <v2f32, v2i32, VReg_64>;
2281 def : BitConvert <v2i32, v2f32, VReg_64>;
2282 def : BitConvert <v2i32, i64, VReg_64>;
2283 def : BitConvert <i64, v2i32, VReg_64>;
2284 def : BitConvert <v2f32, i64, VReg_64>;
2285 def : BitConvert <i64, v2f32, VReg_64>;
2286 def : BitConvert <v2i32, f64, VReg_64>;
2287 def : BitConvert <f64, v2i32, VReg_64>;
2288 def : BitConvert <v4f32, v4i32, VReg_128>;
2289 def : BitConvert <v4i32, v4f32, VReg_128>;
2291 def : BitConvert <v8f32, v8i32, SReg_256>;
2292 def : BitConvert <v8i32, v8f32, SReg_256>;
2293 def : BitConvert <v8i32, v32i8, SReg_256>;
2294 def : BitConvert <v32i8, v8i32, SReg_256>;
2295 def : BitConvert <v8i32, v32i8, VReg_256>;
2296 def : BitConvert <v8i32, v8f32, VReg_256>;
2297 def : BitConvert <v8f32, v8i32, VReg_256>;
2298 def : BitConvert <v32i8, v8i32, VReg_256>;
2300 def : BitConvert <v16i32, v16f32, VReg_512>;
2301 def : BitConvert <v16f32, v16i32, VReg_512>;
2303 /********** =================== **********/
2304 /********** Src & Dst modifiers **********/
2305 /********** =================== **********/
2307 def FCLAMP_SI : AMDGPUShaderInst <
2308 (outs VReg_32:$dst),
2309 (ins VSrc_32:$src0),
2310 "FCLAMP_SI $dst, $src0",
2313 let usesCustomInserter = 1;
2317 (AMDGPUclamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)),
2318 (FCLAMP_SI f32:$src)
2321 /********** ================================ **********/
2322 /********** Floating point absolute/negative **********/
2323 /********** ================================ **********/
2325 // Manipulate the sign bit directly, as e.g. using the source negation modifier
2326 // in V_ADD_F32_e64 $src, 0, [...] does not result in -0.0 for $src == +0.0,
2327 // breaking the piglit *s-floatBitsToInt-neg* tests
2329 // TODO: Look into not implementing isFNegFree/isFAbsFree for SI, and possibly
2330 // removing these patterns
2333 (fneg (fabs f32:$src)),
2334 (V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
2337 def FABS_SI : AMDGPUShaderInst <
2338 (outs VReg_32:$dst),
2339 (ins VSrc_32:$src0),
2340 "FABS_SI $dst, $src0",
2343 let usesCustomInserter = 1;
2351 def FNEG_SI : AMDGPUShaderInst <
2352 (outs VReg_32:$dst),
2353 (ins VSrc_32:$src0),
2354 "FNEG_SI $dst, $src0",
2357 let usesCustomInserter = 1;
2365 /********** ================== **********/
2366 /********** Immediate Patterns **********/
2367 /********** ================== **********/
2370 (SGPRImm<(i32 imm)>:$imm),
2371 (S_MOV_B32 imm:$imm)
2375 (SGPRImm<(f32 fpimm)>:$imm),
2376 (S_MOV_B32 fpimm:$imm)
2381 (V_MOV_B32_e32 imm:$imm)
2386 (V_MOV_B32_e32 fpimm:$imm)
2390 (i64 InlineImm<i64>:$imm),
2391 (S_MOV_B64 InlineImm<i64>:$imm)
2394 /********** ===================== **********/
2395 /********** Interpolation Paterns **********/
2396 /********** ===================== **********/
2399 (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params),
2400 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, $params)
2404 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, v2i32:$ij),
2405 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0),
2406 imm:$attr_chan, imm:$attr, i32:$params),
2407 (EXTRACT_SUBREG $ij, sub1),
2408 imm:$attr_chan, imm:$attr, $params)
2411 /********** ================== **********/
2412 /********** Intrinsic Patterns **********/
2413 /********** ================== **********/
2415 /* llvm.AMDGPU.pow */
2416 def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>;
2419 (int_AMDGPU_div f32:$src0, f32:$src1),
2420 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1))
2424 (fdiv f64:$src0, f64:$src1),
2425 (V_MUL_F64 0 /* src0_modifiers */, $src0,
2426 0 /* src1_modifiers */, (V_RCP_F64_e32 $src1),
2427 0 /* clamp */, 0 /* omod */)
2431 (int_AMDGPU_cube v4f32:$src),
2432 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2433 (V_CUBETC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
2434 0 /* src1_modifiers */, (EXTRACT_SUBREG $src, sub1),
2435 0 /* src2_modifiers */, (EXTRACT_SUBREG $src, sub2),
2436 0 /* clamp */, 0 /* omod */),
2438 (V_CUBESC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
2439 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2440 0 /* src2_modifiers */,(EXTRACT_SUBREG $src, sub2),
2441 0 /* clamp */, 0 /* omod */),
2443 (V_CUBEMA_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0),
2444 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2445 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2),
2446 0 /* clamp */, 0 /* omod */),
2448 (V_CUBEID_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0),
2449 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2450 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2),
2451 0 /* clamp */, 0 /* omod */),
2456 (i32 (sext i1:$src0)),
2457 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
2460 class Ext32Pat <SDNode ext> : Pat <
2461 (i32 (ext i1:$src0)),
2462 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0)
2465 def : Ext32Pat <zext>;
2466 def : Ext32Pat <anyext>;
2468 // Offset in an 32Bit VGPR
2470 (SIload_constant v4i32:$sbase, i32:$voff),
2471 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0, 0)
2474 // The multiplication scales from [0,1] to the unsigned integer range
2476 (AMDGPUurecip i32:$src0),
2478 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1,
2479 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
2484 (V_MBCNT_HI_U32_B32_e32 0xffffffff,
2485 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0))
2488 //===----------------------------------------------------------------------===//
2490 //===----------------------------------------------------------------------===//
2492 def : IMad24Pat<V_MAD_I32_I24>;
2493 def : UMad24Pat<V_MAD_U32_U24>;
2496 (mul i32:$src0, i32:$src1),
2497 (V_MUL_LO_I32 $src0, $src1)
2501 (mulhu i32:$src0, i32:$src1),
2502 (V_MUL_HI_U32 $src0, $src1)
2506 (mulhs i32:$src0, i32:$src1),
2507 (V_MUL_HI_I32 $src0, $src1)
2510 defm : BFIPatterns <V_BFI_B32, S_MOV_B32>;
2511 def : ROTRPattern <V_ALIGNBIT_B32>;
2513 /********** ======================= **********/
2514 /********** Load/Store Patterns **********/
2515 /********** ======================= **********/
2517 multiclass DSReadPat <DS inst, ValueType vt, PatFrag frag> {
2519 (vt (frag (add i32:$ptr, (i32 IMM16bit:$offset)))),
2520 (inst (i1 0), $ptr, (as_i16imm $offset))
2525 (vt (inst 0, $src0, 0))
2529 defm : DSReadPat <DS_READ_I8, i32, sextloadi8_local>;
2530 defm : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>;
2531 defm : DSReadPat <DS_READ_I16, i32, sextloadi16_local>;
2532 defm : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>;
2533 defm : DSReadPat <DS_READ_B32, i32, local_load>;
2534 defm : DSReadPat <DS_READ_B64, v2i32, local_load>;
2536 multiclass DSWritePat <DS inst, ValueType vt, PatFrag frag> {
2538 (frag vt:$value, (add i32:$ptr, (i32 IMM16bit:$offset))),
2539 (inst (i1 0), $ptr, $value, (as_i16imm $offset))
2543 (frag vt:$val, i32:$ptr),
2544 (inst 0, $ptr, $val, 0)
2548 defm : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>;
2549 defm : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>;
2550 defm : DSWritePat <DS_WRITE_B32, i32, local_store>;
2551 defm : DSWritePat <DS_WRITE_B64, v2i32, local_store>;
2553 multiclass DSAtomicRetPat<DS inst, ValueType vt, PatFrag frag> {
2555 (frag (add i32:$ptr, (i32 IMM16bit:$offset)), vt:$value),
2556 (inst (i1 0), $ptr, $value, (as_i16imm $offset))
2560 (frag i32:$ptr, vt:$val),
2561 (inst 0, $ptr, $val, 0)
2565 // Special case of DSAtomicRetPat for add / sub 1 -> inc / dec
2567 // We need to use something for the data0, so we set a register to
2568 // -1. For the non-rtn variants, the manual says it does
2569 // DS[A] = (DS[A] >= D0) ? 0 : DS[A] + 1, and setting D0 to uint_max
2570 // will always do the increment so I'm assuming it's the same.
2572 // We also load this -1 with s_mov_b32 / s_mov_b64 even though this
2573 // needs to be a VGPR. The SGPR copy pass will fix this, and it's
2574 // easier since there is no v_mov_b64.
2575 multiclass DSAtomicIncRetPat<DS inst, ValueType vt,
2576 Instruction LoadImm, PatFrag frag> {
2578 (frag (add i32:$ptr, (i32 IMM16bit:$offset)), (vt 1)),
2579 (inst (i1 0), $ptr, (LoadImm (vt -1)), (as_i16imm $offset))
2583 (frag i32:$ptr, (vt 1)),
2584 (inst 0, $ptr, (LoadImm (vt -1)), 0)
2588 multiclass DSAtomicCmpXChg <DS inst, ValueType vt, PatFrag frag> {
2590 (frag (add i32:$ptr, (i32 IMM16bit:$offset)), vt:$cmp, vt:$swap),
2591 (inst (i1 0), $ptr, $cmp, $swap, (as_i16imm $offset))
2595 (frag i32:$ptr, vt:$cmp, vt:$swap),
2596 (inst 0, $ptr, $cmp, $swap, 0)
2602 defm : DSAtomicIncRetPat<DS_INC_RTN_U32, i32,
2603 S_MOV_B32, atomic_load_add_local>;
2604 defm : DSAtomicIncRetPat<DS_DEC_RTN_U32, i32,
2605 S_MOV_B32, atomic_load_sub_local>;
2607 defm : DSAtomicRetPat<DS_WRXCHG_RTN_B32, i32, atomic_swap_local>;
2608 defm : DSAtomicRetPat<DS_ADD_RTN_U32, i32, atomic_load_add_local>;
2609 defm : DSAtomicRetPat<DS_SUB_RTN_U32, i32, atomic_load_sub_local>;
2610 defm : DSAtomicRetPat<DS_AND_RTN_B32, i32, atomic_load_and_local>;
2611 defm : DSAtomicRetPat<DS_OR_RTN_B32, i32, atomic_load_or_local>;
2612 defm : DSAtomicRetPat<DS_XOR_RTN_B32, i32, atomic_load_xor_local>;
2613 defm : DSAtomicRetPat<DS_MIN_RTN_I32, i32, atomic_load_min_local>;
2614 defm : DSAtomicRetPat<DS_MAX_RTN_I32, i32, atomic_load_max_local>;
2615 defm : DSAtomicRetPat<DS_MIN_RTN_U32, i32, atomic_load_umin_local>;
2616 defm : DSAtomicRetPat<DS_MAX_RTN_U32, i32, atomic_load_umax_local>;
2618 defm : DSAtomicCmpXChg<DS_CMPST_RTN_B32, i32, atomic_cmp_swap_32_local>;
2621 defm : DSAtomicIncRetPat<DS_INC_RTN_U64, i64,
2622 S_MOV_B64, atomic_load_add_local>;
2623 defm : DSAtomicIncRetPat<DS_DEC_RTN_U64, i64,
2624 S_MOV_B64, atomic_load_sub_local>;
2626 defm : DSAtomicRetPat<DS_WRXCHG_RTN_B64, i64, atomic_swap_local>;
2627 defm : DSAtomicRetPat<DS_ADD_RTN_U64, i64, atomic_load_add_local>;
2628 defm : DSAtomicRetPat<DS_SUB_RTN_U64, i64, atomic_load_sub_local>;
2629 defm : DSAtomicRetPat<DS_AND_RTN_B64, i64, atomic_load_and_local>;
2630 defm : DSAtomicRetPat<DS_OR_RTN_B64, i64, atomic_load_or_local>;
2631 defm : DSAtomicRetPat<DS_XOR_RTN_B64, i64, atomic_load_xor_local>;
2632 defm : DSAtomicRetPat<DS_MIN_RTN_I64, i64, atomic_load_min_local>;
2633 defm : DSAtomicRetPat<DS_MAX_RTN_I64, i64, atomic_load_max_local>;
2634 defm : DSAtomicRetPat<DS_MIN_RTN_U64, i64, atomic_load_umin_local>;
2635 defm : DSAtomicRetPat<DS_MAX_RTN_U64, i64, atomic_load_umax_local>;
2637 defm : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, atomic_cmp_swap_64_local>;
2640 //===----------------------------------------------------------------------===//
2642 //===----------------------------------------------------------------------===//
2644 multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
2645 PatFrag constant_ld> {
2647 (vt (constant_ld (add i64:$ptr, i64:$offset))),
2648 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0)
2653 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, sextloadi8_constant>;
2654 defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, az_extloadi8_constant>;
2655 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_constant>;
2656 defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, az_extloadi16_constant>;
2657 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32, constant_load>;
2658 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32, constant_load>;
2659 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32, constant_load>;
2661 class MUBUFScratchLoadPat <MUBUF Instr, ValueType vt, PatFrag ld> : Pat <
2662 (vt (ld (MUBUFScratch v4i32:$srsrc, i32:$vaddr,
2663 i32:$soffset, u16imm:$offset))),
2664 (Instr $srsrc, $vaddr, $soffset, $offset, 0, 0, 0)
2667 def : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, i32, sextloadi8_private>;
2668 def : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, i32, extloadi8_private>;
2669 def : MUBUFScratchLoadPat <BUFFER_LOAD_SSHORT_OFFEN, i32, sextloadi16_private>;
2670 def : MUBUFScratchLoadPat <BUFFER_LOAD_USHORT_OFFEN, i32, extloadi16_private>;
2671 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORD_OFFEN, i32, load_private>;
2672 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX2_OFFEN, v2i32, load_private>;
2673 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX4_OFFEN, v4i32, load_private>;
2675 // BUFFER_LOAD_DWORD*, addr64=0
2676 multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen,
2680 (vt (int_SI_buffer_load_dword v4i32:$rsrc, (i32 imm), i32:$soffset,
2681 imm:$offset, 0, 0, imm:$glc, imm:$slc,
2683 (offset $rsrc, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2684 (as_i1imm $slc), (as_i1imm $tfe))
2688 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2689 imm:$offset, 1, 0, imm:$glc, imm:$slc,
2691 (offen $rsrc, $vaddr, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc),
2696 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2697 imm:$offset, 0, 1, imm:$glc, imm:$slc,
2699 (idxen $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2700 (as_i1imm $slc), (as_i1imm $tfe))
2704 (vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset,
2705 imm, 1, 1, imm:$glc, imm:$slc,
2707 (bothen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
2712 defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN,
2713 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
2714 defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN,
2715 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>;
2716 defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN,
2717 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
2719 class MUBUFScratchStorePat <MUBUF Instr, ValueType vt, PatFrag st> : Pat <
2720 (st vt:$value, (MUBUFScratch v4i32:$srsrc, i32:$vaddr, i32:$soffset,
2722 (Instr $value, $srsrc, $vaddr, $soffset, $offset, 0, 0, 0)
2725 def : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, i32, truncstorei8_private>;
2726 def : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, i32, truncstorei16_private>;
2727 def : MUBUFScratchStorePat <BUFFER_STORE_DWORD_OFFEN, i32, store_private>;
2728 def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX2_OFFEN, v2i32, store_private>;
2729 def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, v4i32, store_private>;
2732 class MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> : Pat <
2733 (st vt:$value, (MUBUFScratch v4i32:$srsrc, i64:$vaddr, u16imm:$offset)),
2734 (Instr $value, $srsrc, $vaddr, $offset)
2737 def : MUBUFStore_Pattern <BUFFER_STORE_BYTE_ADDR64, i32, truncstorei8_private>;
2738 def : MUBUFStore_Pattern <BUFFER_STORE_SHORT_ADDR64, i32, truncstorei16_private>;
2739 def : MUBUFStore_Pattern <BUFFER_STORE_DWORD_ADDR64, i32, store_private>;
2740 def : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2_ADDR64, v2i32, store_private>;
2741 def : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4_ADDR64, v4i32, store_private>;
2745 //===----------------------------------------------------------------------===//
2747 //===----------------------------------------------------------------------===//
2749 // TBUFFER_STORE_FORMAT_*, addr64=0
2750 class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat<
2751 (SItbuffer_store v4i32:$rsrc, vt:$vdata, num_channels, i32:$vaddr,
2752 i32:$soffset, imm:$inst_offset, imm:$dfmt,
2753 imm:$nfmt, imm:$offen, imm:$idxen,
2754 imm:$glc, imm:$slc, imm:$tfe),
2756 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen),
2757 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc,
2758 (as_i1imm $slc), (as_i1imm $tfe), $soffset)
2761 def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>;
2762 def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>;
2763 def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>;
2764 def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>;
2766 let SubtargetPredicate = isCI in {
2768 // Sea island new arithmetic instructinos
2769 defm V_TRUNC_F64 : VOP1Inst <0x00000017, "V_TRUNC_F64",
2772 defm V_CEIL_F64 : VOP1Inst <0x00000018, "V_CEIL_F64",
2775 defm V_FLOOR_F64 : VOP1Inst <0x0000001A, "V_FLOOR_F64",
2778 defm V_RNDNE_F64 : VOP1Inst <0x00000019, "V_RNDNE_F64",
2782 defm V_QSAD_PK_U16_U8 : VOP3Inst <0x00000173, "V_QSAD_PK_U16_U8",
2785 defm V_MQSAD_U16_U8 : VOP3Inst <0x000000172, "V_MQSAD_U16_U8",
2788 defm V_MQSAD_U32_U8 : VOP3Inst <0x00000175, "V_MQSAD_U32_U8",
2791 defm V_MAD_U64_U32 : VOP3Inst <0x00000176, "V_MAD_U64_U32",
2795 // XXX - Does this set VCC?
2796 defm V_MAD_I64_I32 : VOP3Inst <0x00000177, "V_MAD_I64_I32",
2800 // Remaining instructions:
2802 // S_CBRANCH_CDBGUSER
2803 // S_CBRANCH_CDBGSYS
2804 // S_CBRANCH_CDBGSYS_OR_USER
2805 // S_CBRANCH_CDBGSYS_AND_USER
2810 // DS_GWS_SEMA_RELEASE_ALL
2812 // DS_CNDXCHG32_RTN_B64
2815 // DS_CONDXCHG32_RTN_B128
2818 // BUFFER_LOAD_DWORDX3
2819 // BUFFER_STORE_DWORDX3
2824 /********** ====================== **********/
2825 /********** Indirect adressing **********/
2826 /********** ====================== **********/
2828 multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, SI_INDIRECT_DST IndDst> {
2830 // 1. Extract with offset
2832 (vector_extract vt:$vec, (add i32:$idx, imm:$off)),
2833 (eltvt (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off))
2836 // 2. Extract without offset
2838 (vector_extract vt:$vec, i32:$idx),
2839 (eltvt (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0))
2842 // 3. Insert with offset
2844 (vector_insert vt:$vec, eltvt:$val, (add i32:$idx, imm:$off)),
2845 (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val)
2848 // 4. Insert without offset
2850 (vector_insert vt:$vec, eltvt:$val, i32:$idx),
2851 (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val)
2855 defm : SI_INDIRECT_Pattern <v2f32, f32, SI_INDIRECT_DST_V2>;
2856 defm : SI_INDIRECT_Pattern <v4f32, f32, SI_INDIRECT_DST_V4>;
2857 defm : SI_INDIRECT_Pattern <v8f32, f32, SI_INDIRECT_DST_V8>;
2858 defm : SI_INDIRECT_Pattern <v16f32, f32, SI_INDIRECT_DST_V16>;
2860 defm : SI_INDIRECT_Pattern <v2i32, i32, SI_INDIRECT_DST_V2>;
2861 defm : SI_INDIRECT_Pattern <v4i32, i32, SI_INDIRECT_DST_V4>;
2862 defm : SI_INDIRECT_Pattern <v8i32, i32, SI_INDIRECT_DST_V8>;
2863 defm : SI_INDIRECT_Pattern <v16i32, i32, SI_INDIRECT_DST_V16>;
2865 //===----------------------------------------------------------------------===//
2866 // Conversion Patterns
2867 //===----------------------------------------------------------------------===//
2869 def : Pat<(i32 (sext_inreg i32:$src, i1)),
2870 (S_BFE_I32 i32:$src, 65536)>; // 0 | 1 << 16
2872 // TODO: Match 64-bit BFE. SI has a 64-bit BFE, but it's scalar only so it
2873 // might not be worth the effort, and will need to expand to shifts when
2874 // fixing SGPR copies.
2876 // Handle sext_inreg in i64
2878 (i64 (sext_inreg i64:$src, i1)),
2879 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2880 (S_BFE_I32 (EXTRACT_SUBREG i64:$src, sub0), 65536), sub0), // 0 | 1 << 16
2881 (S_MOV_B32 -1), sub1)
2885 (i64 (sext_inreg i64:$src, i8)),
2886 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2887 (S_SEXT_I32_I8 (EXTRACT_SUBREG i64:$src, sub0)), sub0),
2888 (S_MOV_B32 -1), sub1)
2892 (i64 (sext_inreg i64:$src, i16)),
2893 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2894 (S_SEXT_I32_I16 (EXTRACT_SUBREG i64:$src, sub0)), sub0),
2895 (S_MOV_B32 -1), sub1)
2898 class ZExt_i64_i32_Pat <SDNode ext> : Pat <
2899 (i64 (ext i32:$src)),
2900 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $src, sub0),
2901 (S_MOV_B32 0), sub1)
2904 class ZExt_i64_i1_Pat <SDNode ext> : Pat <
2905 (i64 (ext i1:$src)),
2907 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2908 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src), sub0),
2909 (S_MOV_B32 0), sub1)
2913 def : ZExt_i64_i32_Pat<zext>;
2914 def : ZExt_i64_i32_Pat<anyext>;
2915 def : ZExt_i64_i1_Pat<zext>;
2916 def : ZExt_i64_i1_Pat<anyext>;
2919 (i64 (sext i32:$src)),
2921 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $src, sub0),
2922 (S_ASHR_I32 $src, 31), sub1)
2926 (i64 (sext i1:$src)),
2929 (i64 (IMPLICIT_DEF)),
2930 (V_CNDMASK_B32_e64 0, -1, $src), sub0),
2931 (V_CNDMASK_B32_e64 0, -1, $src), sub1)
2935 (f32 (sint_to_fp i1:$src)),
2936 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_NEG_ONE, $src)
2940 (f32 (uint_to_fp i1:$src)),
2941 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_ONE, $src)
2945 (f64 (sint_to_fp i1:$src)),
2946 (V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src))
2950 (f64 (uint_to_fp i1:$src)),
2951 (V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src))
2954 //===----------------------------------------------------------------------===//
2955 // Miscellaneous Patterns
2956 //===----------------------------------------------------------------------===//
2959 (i32 (trunc i64:$a)),
2960 (EXTRACT_SUBREG $a, sub0)
2964 (i1 (trunc i32:$a)),
2965 (V_CMP_EQ_I32_e64 (V_AND_B32_e32 (i32 1), $a), 1)
2968 //============================================================================//
2969 // Miscellaneous Optimization Patterns
2970 //============================================================================//
2972 def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e32>;
2974 } // End isSI predicate