1 //===-- SIInstructions.td - SI Instruction Defintions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This file was originally auto-generated from a GPU register header file and
10 // all the instruction definitions were originally commented out. Instructions
11 // that are not yet supported remain commented out.
12 //===----------------------------------------------------------------------===//
19 def INTERP : InterpSlots;
21 def InterpSlot : Operand<i32> {
22 let PrintMethod = "printInterpSlot";
25 def SendMsgImm : Operand<i32> {
26 let PrintMethod = "printSendMsg";
29 def isSI : Predicate<"Subtarget.getGeneration() "
30 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">;
32 def isCI : Predicate<"Subtarget.getGeneration() "
33 ">= AMDGPUSubtarget::SEA_ISLANDS">;
34 def HasFlatAddressSpace : Predicate<"Subtarget.hasFlatAddressSpace()">;
36 def isCFDepth0 : Predicate<"isCFDepth0()">;
38 def WAIT_FLAG : InstFlag<"printWaitFlag">;
40 let SubtargetPredicate = isSI in {
41 let OtherPredicates = [isCFDepth0] in {
43 //===----------------------------------------------------------------------===//
45 //===----------------------------------------------------------------------===//
49 // We are using the SGPR_32 and not the SReg_32 register class for 32-bit
50 // SMRD instructions, because the SGPR_32 register class does not include M0
51 // and writing to M0 from an SMRD instruction will hang the GPU.
52 defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SGPR_32>;
53 defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>;
54 defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>;
55 defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>;
56 defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>;
58 defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
59 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SGPR_32
62 defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
63 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64
66 defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper <
67 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128
70 defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <
71 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256
74 defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
75 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512
80 //def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>;
81 //def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>;
83 //===----------------------------------------------------------------------===//
85 //===----------------------------------------------------------------------===//
87 let isMoveImm = 1 in {
88 def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>;
89 def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>;
90 def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>;
91 def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>;
92 } // End isMoveImm = 1
94 def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32",
95 [(set i32:$dst, (not i32:$src0))]
98 def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64",
99 [(set i64:$dst, (not i64:$src0))]
101 def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>;
102 def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>;
103 def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32",
104 [(set i32:$dst, (AMDGPUbrev i32:$src0))]
106 def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>;
108 ////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>;
109 ////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>;
110 def S_BCNT1_I32_B32 : SOP1_32 <0x0000000f, "S_BCNT1_I32_B32",
111 [(set i32:$dst, (ctpop i32:$src0))]
113 def S_BCNT1_I32_B64 : SOP1_32_64 <0x00000010, "S_BCNT1_I32_B64", []>;
115 ////def S_FF0_I32_B32 : SOP1_32 <0x00000011, "S_FF0_I32_B32", []>;
116 ////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>;
117 def S_FF1_I32_B32 : SOP1_32 <0x00000013, "S_FF1_I32_B32",
118 [(set i32:$dst, (cttz_zero_undef i32:$src0))]
120 ////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>;
122 def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32",
123 [(set i32:$dst, (ctlz_zero_undef i32:$src0))]
126 //def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>;
127 def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>;
128 //def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>;
129 def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8",
130 [(set i32:$dst, (sext_inreg i32:$src0, i8))]
132 def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16",
133 [(set i32:$dst, (sext_inreg i32:$src0, i16))]
136 ////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>;
137 ////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>;
138 ////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>;
139 ////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>;
140 def S_GETPC_B64 : SOP1 <
141 0x0000001f, (outs SReg_64:$dst), (ins), "S_GETPC_B64 $dst", []
145 def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>;
146 def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>;
147 def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>;
149 let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in {
151 def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>;
152 def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>;
153 def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>;
154 def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>;
155 def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>;
156 def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>;
157 def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>;
158 def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>;
160 } // End hasSideEffects = 1
162 def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>;
163 def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>;
164 def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>;
165 def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>;
166 def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>;
167 def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>;
168 //def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>;
169 def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>;
170 def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>;
171 def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>;
173 //===----------------------------------------------------------------------===//
175 //===----------------------------------------------------------------------===//
177 let Defs = [SCC] in { // Carry out goes to SCC
178 let isCommutable = 1 in {
179 def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>;
180 def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32",
181 [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))]
183 } // End isCommutable = 1
185 def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>;
186 def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32",
187 [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))]
190 let Uses = [SCC] in { // Carry in comes from SCC
191 let isCommutable = 1 in {
192 def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32",
193 [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
194 } // End isCommutable = 1
196 def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32",
197 [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
198 } // End Uses = [SCC]
199 } // End Defs = [SCC]
201 def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32",
202 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]
204 def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32",
205 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]
207 def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32",
208 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]
210 def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32",
211 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]
214 def S_CSELECT_B32 : SOP2 <
215 0x0000000a, (outs SReg_32:$dst),
216 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32",
220 def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>;
222 def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32",
223 [(set i32:$dst, (and i32:$src0, i32:$src1))]
226 def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64",
227 [(set i64:$dst, (and i64:$src0, i64:$src1))]
230 def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32",
231 [(set i32:$dst, (or i32:$src0, i32:$src1))]
234 def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64",
235 [(set i64:$dst, (or i64:$src0, i64:$src1))]
238 def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32",
239 [(set i32:$dst, (xor i32:$src0, i32:$src1))]
242 def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64",
243 [(set i64:$dst, (xor i64:$src0, i64:$src1))]
245 def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>;
246 def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>;
247 def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>;
248 def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>;
249 def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>;
250 def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>;
251 def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>;
252 def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>;
253 def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>;
254 def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>;
256 // Use added complexity so these patterns are preferred to the VALU patterns.
257 let AddedComplexity = 1 in {
259 def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32",
260 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
262 def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "S_LSHL_B64",
263 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
265 def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32",
266 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
268 def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "S_LSHR_B64",
269 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
271 def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32",
272 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
274 def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64",
275 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
279 def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>;
280 def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>;
281 def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32",
282 [(set i32:$dst, (mul i32:$src0, i32:$src1))]
285 } // End AddedComplexity = 1
287 def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>;
288 def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>;
289 def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>;
290 def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>;
291 //def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>;
292 def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>;
294 //===----------------------------------------------------------------------===//
296 //===----------------------------------------------------------------------===//
298 def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32">;
299 def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32">;
300 def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32">;
301 def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32">;
302 def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32">;
303 def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32">;
304 def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32">;
305 def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32">;
306 def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32">;
307 def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32">;
308 def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32">;
309 def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32">;
310 ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>;
311 ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>;
312 ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>;
313 ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>;
314 //def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>;
316 //===----------------------------------------------------------------------===//
318 //===----------------------------------------------------------------------===//
320 def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>;
321 def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>;
324 This instruction is disabled for now until we can figure out how to teach
325 the instruction selector to correctly use the S_CMP* vs V_CMP*
328 When this instruction is enabled the code generator sometimes produces this
331 SCC = S_CMPK_EQ_I32 SGPR0, imm
333 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
335 def S_CMPK_EQ_I32 : SOPK <
336 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1),
338 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))]
342 let isCompare = 1, Defs = [SCC] in {
343 def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>;
344 def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>;
345 def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>;
346 def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>;
347 def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>;
348 def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>;
349 def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>;
350 def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>;
351 def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>;
352 def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>;
353 def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>;
354 } // End isCompare = 1, Defs = [SCC]
356 let Defs = [SCC], isCommutable = 1 in {
357 def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>;
358 def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>;
361 //def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>;
362 def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>;
363 def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>;
364 def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>;
365 //def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>;
366 //def EXP : EXP_ <0x00000000, "EXP", []>;
368 } // End let OtherPredicates = [isCFDepth0]
370 //===----------------------------------------------------------------------===//
372 //===----------------------------------------------------------------------===//
374 def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "S_NOP $simm16", []>;
376 let isTerminator = 1 in {
378 def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM",
385 let isBranch = 1 in {
386 def S_BRANCH : SOPP <
387 0x00000002, (ins sopp_brtarget:$simm16), "S_BRANCH $simm16",
392 let DisableEncoding = "$scc" in {
393 def S_CBRANCH_SCC0 : SOPP <
394 0x00000004, (ins sopp_brtarget:$simm16, SCCReg:$scc),
395 "S_CBRANCH_SCC0 $simm16", []
397 def S_CBRANCH_SCC1 : SOPP <
398 0x00000005, (ins sopp_brtarget:$simm16, SCCReg:$scc),
399 "S_CBRANCH_SCC1 $simm16",
402 } // End DisableEncoding = "$scc"
404 def S_CBRANCH_VCCZ : SOPP <
405 0x00000006, (ins sopp_brtarget:$simm16, VCCReg:$vcc),
406 "S_CBRANCH_VCCZ $simm16",
409 def S_CBRANCH_VCCNZ : SOPP <
410 0x00000007, (ins sopp_brtarget:$simm16, VCCReg:$vcc),
411 "S_CBRANCH_VCCNZ $simm16",
415 let DisableEncoding = "$exec" in {
416 def S_CBRANCH_EXECZ : SOPP <
417 0x00000008, (ins sopp_brtarget:$simm16, EXECReg:$exec),
418 "S_CBRANCH_EXECZ $simm16",
421 def S_CBRANCH_EXECNZ : SOPP <
422 0x00000009, (ins sopp_brtarget:$simm16, EXECReg:$exec),
423 "S_CBRANCH_EXECNZ $simm16",
426 } // End DisableEncoding = "$exec"
429 } // End isBranch = 1
430 } // End isTerminator = 1
432 let hasSideEffects = 1 in {
433 def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER",
434 [(int_AMDGPU_barrier_local)]
443 def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16",
446 //def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>;
447 //def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>;
448 //def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>;
450 let Uses = [EXEC] in {
451 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "S_SENDMSG $simm16",
452 [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)]
454 let DisableEncoding = "$m0";
456 } // End Uses = [EXEC]
458 //def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>;
459 //def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>;
460 //def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>;
461 //def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>;
462 //def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>;
463 //def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
464 } // End hasSideEffects
466 //===----------------------------------------------------------------------===//
468 //===----------------------------------------------------------------------===//
470 let isCompare = 1 in {
472 defm V_CMP_F_F32 : VOPC_F32 <0x00000000, "V_CMP_F_F32">;
473 defm V_CMP_LT_F32 : VOPC_F32 <0x00000001, "V_CMP_LT_F32", COND_OLT>;
474 defm V_CMP_EQ_F32 : VOPC_F32 <0x00000002, "V_CMP_EQ_F32", COND_OEQ>;
475 defm V_CMP_LE_F32 : VOPC_F32 <0x00000003, "V_CMP_LE_F32", COND_OLE>;
476 defm V_CMP_GT_F32 : VOPC_F32 <0x00000004, "V_CMP_GT_F32", COND_OGT>;
477 defm V_CMP_LG_F32 : VOPC_F32 <0x00000005, "V_CMP_LG_F32">;
478 defm V_CMP_GE_F32 : VOPC_F32 <0x00000006, "V_CMP_GE_F32", COND_OGE>;
479 defm V_CMP_O_F32 : VOPC_F32 <0x00000007, "V_CMP_O_F32", COND_O>;
480 defm V_CMP_U_F32 : VOPC_F32 <0x00000008, "V_CMP_U_F32", COND_UO>;
481 defm V_CMP_NGE_F32 : VOPC_F32 <0x00000009, "V_CMP_NGE_F32">;
482 defm V_CMP_NLG_F32 : VOPC_F32 <0x0000000a, "V_CMP_NLG_F32">;
483 defm V_CMP_NGT_F32 : VOPC_F32 <0x0000000b, "V_CMP_NGT_F32">;
484 defm V_CMP_NLE_F32 : VOPC_F32 <0x0000000c, "V_CMP_NLE_F32">;
485 defm V_CMP_NEQ_F32 : VOPC_F32 <0x0000000d, "V_CMP_NEQ_F32", COND_UNE>;
486 defm V_CMP_NLT_F32 : VOPC_F32 <0x0000000e, "V_CMP_NLT_F32">;
487 defm V_CMP_TRU_F32 : VOPC_F32 <0x0000000f, "V_CMP_TRU_F32">;
489 let hasSideEffects = 1 in {
491 defm V_CMPX_F_F32 : VOPCX_F32 <0x00000010, "V_CMPX_F_F32">;
492 defm V_CMPX_LT_F32 : VOPCX_F32 <0x00000011, "V_CMPX_LT_F32">;
493 defm V_CMPX_EQ_F32 : VOPCX_F32 <0x00000012, "V_CMPX_EQ_F32">;
494 defm V_CMPX_LE_F32 : VOPCX_F32 <0x00000013, "V_CMPX_LE_F32">;
495 defm V_CMPX_GT_F32 : VOPCX_F32 <0x00000014, "V_CMPX_GT_F32">;
496 defm V_CMPX_LG_F32 : VOPCX_F32 <0x00000015, "V_CMPX_LG_F32">;
497 defm V_CMPX_GE_F32 : VOPCX_F32 <0x00000016, "V_CMPX_GE_F32">;
498 defm V_CMPX_O_F32 : VOPCX_F32 <0x00000017, "V_CMPX_O_F32">;
499 defm V_CMPX_U_F32 : VOPCX_F32 <0x00000018, "V_CMPX_U_F32">;
500 defm V_CMPX_NGE_F32 : VOPCX_F32 <0x00000019, "V_CMPX_NGE_F32">;
501 defm V_CMPX_NLG_F32 : VOPCX_F32 <0x0000001a, "V_CMPX_NLG_F32">;
502 defm V_CMPX_NGT_F32 : VOPCX_F32 <0x0000001b, "V_CMPX_NGT_F32">;
503 defm V_CMPX_NLE_F32 : VOPCX_F32 <0x0000001c, "V_CMPX_NLE_F32">;
504 defm V_CMPX_NEQ_F32 : VOPCX_F32 <0x0000001d, "V_CMPX_NEQ_F32">;
505 defm V_CMPX_NLT_F32 : VOPCX_F32 <0x0000001e, "V_CMPX_NLT_F32">;
506 defm V_CMPX_TRU_F32 : VOPCX_F32 <0x0000001f, "V_CMPX_TRU_F32">;
508 } // End hasSideEffects = 1
510 defm V_CMP_F_F64 : VOPC_F64 <0x00000020, "V_CMP_F_F64">;
511 defm V_CMP_LT_F64 : VOPC_F64 <0x00000021, "V_CMP_LT_F64", COND_OLT>;
512 defm V_CMP_EQ_F64 : VOPC_F64 <0x00000022, "V_CMP_EQ_F64", COND_OEQ>;
513 defm V_CMP_LE_F64 : VOPC_F64 <0x00000023, "V_CMP_LE_F64", COND_OLE>;
514 defm V_CMP_GT_F64 : VOPC_F64 <0x00000024, "V_CMP_GT_F64", COND_OGT>;
515 defm V_CMP_LG_F64 : VOPC_F64 <0x00000025, "V_CMP_LG_F64">;
516 defm V_CMP_GE_F64 : VOPC_F64 <0x00000026, "V_CMP_GE_F64", COND_OGE>;
517 defm V_CMP_O_F64 : VOPC_F64 <0x00000027, "V_CMP_O_F64", COND_O>;
518 defm V_CMP_U_F64 : VOPC_F64 <0x00000028, "V_CMP_U_F64", COND_UO>;
519 defm V_CMP_NGE_F64 : VOPC_F64 <0x00000029, "V_CMP_NGE_F64">;
520 defm V_CMP_NLG_F64 : VOPC_F64 <0x0000002a, "V_CMP_NLG_F64">;
521 defm V_CMP_NGT_F64 : VOPC_F64 <0x0000002b, "V_CMP_NGT_F64">;
522 defm V_CMP_NLE_F64 : VOPC_F64 <0x0000002c, "V_CMP_NLE_F64">;
523 defm V_CMP_NEQ_F64 : VOPC_F64 <0x0000002d, "V_CMP_NEQ_F64", COND_UNE>;
524 defm V_CMP_NLT_F64 : VOPC_F64 <0x0000002e, "V_CMP_NLT_F64">;
525 defm V_CMP_TRU_F64 : VOPC_F64 <0x0000002f, "V_CMP_TRU_F64">;
527 let hasSideEffects = 1 in {
529 defm V_CMPX_F_F64 : VOPCX_F64 <0x00000030, "V_CMPX_F_F64">;
530 defm V_CMPX_LT_F64 : VOPCX_F64 <0x00000031, "V_CMPX_LT_F64">;
531 defm V_CMPX_EQ_F64 : VOPCX_F64 <0x00000032, "V_CMPX_EQ_F64">;
532 defm V_CMPX_LE_F64 : VOPCX_F64 <0x00000033, "V_CMPX_LE_F64">;
533 defm V_CMPX_GT_F64 : VOPCX_F64 <0x00000034, "V_CMPX_GT_F64">;
534 defm V_CMPX_LG_F64 : VOPCX_F64 <0x00000035, "V_CMPX_LG_F64">;
535 defm V_CMPX_GE_F64 : VOPCX_F64 <0x00000036, "V_CMPX_GE_F64">;
536 defm V_CMPX_O_F64 : VOPCX_F64 <0x00000037, "V_CMPX_O_F64">;
537 defm V_CMPX_U_F64 : VOPCX_F64 <0x00000038, "V_CMPX_U_F64">;
538 defm V_CMPX_NGE_F64 : VOPCX_F64 <0x00000039, "V_CMPX_NGE_F64">;
539 defm V_CMPX_NLG_F64 : VOPCX_F64 <0x0000003a, "V_CMPX_NLG_F64">;
540 defm V_CMPX_NGT_F64 : VOPCX_F64 <0x0000003b, "V_CMPX_NGT_F64">;
541 defm V_CMPX_NLE_F64 : VOPCX_F64 <0x0000003c, "V_CMPX_NLE_F64">;
542 defm V_CMPX_NEQ_F64 : VOPCX_F64 <0x0000003d, "V_CMPX_NEQ_F64">;
543 defm V_CMPX_NLT_F64 : VOPCX_F64 <0x0000003e, "V_CMPX_NLT_F64">;
544 defm V_CMPX_TRU_F64 : VOPCX_F64 <0x0000003f, "V_CMPX_TRU_F64">;
546 } // End hasSideEffects = 1
548 defm V_CMPS_F_F32 : VOPC_F32 <0x00000040, "V_CMPS_F_F32">;
549 defm V_CMPS_LT_F32 : VOPC_F32 <0x00000041, "V_CMPS_LT_F32">;
550 defm V_CMPS_EQ_F32 : VOPC_F32 <0x00000042, "V_CMPS_EQ_F32">;
551 defm V_CMPS_LE_F32 : VOPC_F32 <0x00000043, "V_CMPS_LE_F32">;
552 defm V_CMPS_GT_F32 : VOPC_F32 <0x00000044, "V_CMPS_GT_F32">;
553 defm V_CMPS_LG_F32 : VOPC_F32 <0x00000045, "V_CMPS_LG_F32">;
554 defm V_CMPS_GE_F32 : VOPC_F32 <0x00000046, "V_CMPS_GE_F32">;
555 defm V_CMPS_O_F32 : VOPC_F32 <0x00000047, "V_CMPS_O_F32">;
556 defm V_CMPS_U_F32 : VOPC_F32 <0x00000048, "V_CMPS_U_F32">;
557 defm V_CMPS_NGE_F32 : VOPC_F32 <0x00000049, "V_CMPS_NGE_F32">;
558 defm V_CMPS_NLG_F32 : VOPC_F32 <0x0000004a, "V_CMPS_NLG_F32">;
559 defm V_CMPS_NGT_F32 : VOPC_F32 <0x0000004b, "V_CMPS_NGT_F32">;
560 defm V_CMPS_NLE_F32 : VOPC_F32 <0x0000004c, "V_CMPS_NLE_F32">;
561 defm V_CMPS_NEQ_F32 : VOPC_F32 <0x0000004d, "V_CMPS_NEQ_F32">;
562 defm V_CMPS_NLT_F32 : VOPC_F32 <0x0000004e, "V_CMPS_NLT_F32">;
563 defm V_CMPS_TRU_F32 : VOPC_F32 <0x0000004f, "V_CMPS_TRU_F32">;
565 let hasSideEffects = 1 in {
567 defm V_CMPSX_F_F32 : VOPCX_F32 <0x00000050, "V_CMPSX_F_F32">;
568 defm V_CMPSX_LT_F32 : VOPCX_F32 <0x00000051, "V_CMPSX_LT_F32">;
569 defm V_CMPSX_EQ_F32 : VOPCX_F32 <0x00000052, "V_CMPSX_EQ_F32">;
570 defm V_CMPSX_LE_F32 : VOPCX_F32 <0x00000053, "V_CMPSX_LE_F32">;
571 defm V_CMPSX_GT_F32 : VOPCX_F32 <0x00000054, "V_CMPSX_GT_F32">;
572 defm V_CMPSX_LG_F32 : VOPCX_F32 <0x00000055, "V_CMPSX_LG_F32">;
573 defm V_CMPSX_GE_F32 : VOPCX_F32 <0x00000056, "V_CMPSX_GE_F32">;
574 defm V_CMPSX_O_F32 : VOPCX_F32 <0x00000057, "V_CMPSX_O_F32">;
575 defm V_CMPSX_U_F32 : VOPCX_F32 <0x00000058, "V_CMPSX_U_F32">;
576 defm V_CMPSX_NGE_F32 : VOPCX_F32 <0x00000059, "V_CMPSX_NGE_F32">;
577 defm V_CMPSX_NLG_F32 : VOPCX_F32 <0x0000005a, "V_CMPSX_NLG_F32">;
578 defm V_CMPSX_NGT_F32 : VOPCX_F32 <0x0000005b, "V_CMPSX_NGT_F32">;
579 defm V_CMPSX_NLE_F32 : VOPCX_F32 <0x0000005c, "V_CMPSX_NLE_F32">;
580 defm V_CMPSX_NEQ_F32 : VOPCX_F32 <0x0000005d, "V_CMPSX_NEQ_F32">;
581 defm V_CMPSX_NLT_F32 : VOPCX_F32 <0x0000005e, "V_CMPSX_NLT_F32">;
582 defm V_CMPSX_TRU_F32 : VOPCX_F32 <0x0000005f, "V_CMPSX_TRU_F32">;
584 } // End hasSideEffects = 1
586 defm V_CMPS_F_F64 : VOPC_F64 <0x00000060, "V_CMPS_F_F64">;
587 defm V_CMPS_LT_F64 : VOPC_F64 <0x00000061, "V_CMPS_LT_F64">;
588 defm V_CMPS_EQ_F64 : VOPC_F64 <0x00000062, "V_CMPS_EQ_F64">;
589 defm V_CMPS_LE_F64 : VOPC_F64 <0x00000063, "V_CMPS_LE_F64">;
590 defm V_CMPS_GT_F64 : VOPC_F64 <0x00000064, "V_CMPS_GT_F64">;
591 defm V_CMPS_LG_F64 : VOPC_F64 <0x00000065, "V_CMPS_LG_F64">;
592 defm V_CMPS_GE_F64 : VOPC_F64 <0x00000066, "V_CMPS_GE_F64">;
593 defm V_CMPS_O_F64 : VOPC_F64 <0x00000067, "V_CMPS_O_F64">;
594 defm V_CMPS_U_F64 : VOPC_F64 <0x00000068, "V_CMPS_U_F64">;
595 defm V_CMPS_NGE_F64 : VOPC_F64 <0x00000069, "V_CMPS_NGE_F64">;
596 defm V_CMPS_NLG_F64 : VOPC_F64 <0x0000006a, "V_CMPS_NLG_F64">;
597 defm V_CMPS_NGT_F64 : VOPC_F64 <0x0000006b, "V_CMPS_NGT_F64">;
598 defm V_CMPS_NLE_F64 : VOPC_F64 <0x0000006c, "V_CMPS_NLE_F64">;
599 defm V_CMPS_NEQ_F64 : VOPC_F64 <0x0000006d, "V_CMPS_NEQ_F64">;
600 defm V_CMPS_NLT_F64 : VOPC_F64 <0x0000006e, "V_CMPS_NLT_F64">;
601 defm V_CMPS_TRU_F64 : VOPC_F64 <0x0000006f, "V_CMPS_TRU_F64">;
603 let hasSideEffects = 1, Defs = [EXEC] in {
605 defm V_CMPSX_F_F64 : VOPC_F64 <0x00000070, "V_CMPSX_F_F64">;
606 defm V_CMPSX_LT_F64 : VOPC_F64 <0x00000071, "V_CMPSX_LT_F64">;
607 defm V_CMPSX_EQ_F64 : VOPC_F64 <0x00000072, "V_CMPSX_EQ_F64">;
608 defm V_CMPSX_LE_F64 : VOPC_F64 <0x00000073, "V_CMPSX_LE_F64">;
609 defm V_CMPSX_GT_F64 : VOPC_F64 <0x00000074, "V_CMPSX_GT_F64">;
610 defm V_CMPSX_LG_F64 : VOPC_F64 <0x00000075, "V_CMPSX_LG_F64">;
611 defm V_CMPSX_GE_F64 : VOPC_F64 <0x00000076, "V_CMPSX_GE_F64">;
612 defm V_CMPSX_O_F64 : VOPC_F64 <0x00000077, "V_CMPSX_O_F64">;
613 defm V_CMPSX_U_F64 : VOPC_F64 <0x00000078, "V_CMPSX_U_F64">;
614 defm V_CMPSX_NGE_F64 : VOPC_F64 <0x00000079, "V_CMPSX_NGE_F64">;
615 defm V_CMPSX_NLG_F64 : VOPC_F64 <0x0000007a, "V_CMPSX_NLG_F64">;
616 defm V_CMPSX_NGT_F64 : VOPC_F64 <0x0000007b, "V_CMPSX_NGT_F64">;
617 defm V_CMPSX_NLE_F64 : VOPC_F64 <0x0000007c, "V_CMPSX_NLE_F64">;
618 defm V_CMPSX_NEQ_F64 : VOPC_F64 <0x0000007d, "V_CMPSX_NEQ_F64">;
619 defm V_CMPSX_NLT_F64 : VOPC_F64 <0x0000007e, "V_CMPSX_NLT_F64">;
620 defm V_CMPSX_TRU_F64 : VOPC_F64 <0x0000007f, "V_CMPSX_TRU_F64">;
622 } // End hasSideEffects = 1, Defs = [EXEC]
624 defm V_CMP_F_I32 : VOPC_I32 <0x00000080, "V_CMP_F_I32">;
625 defm V_CMP_LT_I32 : VOPC_I32 <0x00000081, "V_CMP_LT_I32", COND_SLT>;
626 defm V_CMP_EQ_I32 : VOPC_I32 <0x00000082, "V_CMP_EQ_I32", COND_EQ>;
627 defm V_CMP_LE_I32 : VOPC_I32 <0x00000083, "V_CMP_LE_I32", COND_SLE>;
628 defm V_CMP_GT_I32 : VOPC_I32 <0x00000084, "V_CMP_GT_I32", COND_SGT>;
629 defm V_CMP_NE_I32 : VOPC_I32 <0x00000085, "V_CMP_NE_I32", COND_NE>;
630 defm V_CMP_GE_I32 : VOPC_I32 <0x00000086, "V_CMP_GE_I32", COND_SGE>;
631 defm V_CMP_T_I32 : VOPC_I32 <0x00000087, "V_CMP_T_I32">;
633 let hasSideEffects = 1 in {
635 defm V_CMPX_F_I32 : VOPCX_I32 <0x00000090, "V_CMPX_F_I32">;
636 defm V_CMPX_LT_I32 : VOPCX_I32 <0x00000091, "V_CMPX_LT_I32">;
637 defm V_CMPX_EQ_I32 : VOPCX_I32 <0x00000092, "V_CMPX_EQ_I32">;
638 defm V_CMPX_LE_I32 : VOPCX_I32 <0x00000093, "V_CMPX_LE_I32">;
639 defm V_CMPX_GT_I32 : VOPCX_I32 <0x00000094, "V_CMPX_GT_I32">;
640 defm V_CMPX_NE_I32 : VOPCX_I32 <0x00000095, "V_CMPX_NE_I32">;
641 defm V_CMPX_GE_I32 : VOPCX_I32 <0x00000096, "V_CMPX_GE_I32">;
642 defm V_CMPX_T_I32 : VOPCX_I32 <0x00000097, "V_CMPX_T_I32">;
644 } // End hasSideEffects = 1
646 defm V_CMP_F_I64 : VOPC_I64 <0x000000a0, "V_CMP_F_I64">;
647 defm V_CMP_LT_I64 : VOPC_I64 <0x000000a1, "V_CMP_LT_I64", COND_SLT>;
648 defm V_CMP_EQ_I64 : VOPC_I64 <0x000000a2, "V_CMP_EQ_I64", COND_EQ>;
649 defm V_CMP_LE_I64 : VOPC_I64 <0x000000a3, "V_CMP_LE_I64", COND_SLE>;
650 defm V_CMP_GT_I64 : VOPC_I64 <0x000000a4, "V_CMP_GT_I64", COND_SGT>;
651 defm V_CMP_NE_I64 : VOPC_I64 <0x000000a5, "V_CMP_NE_I64", COND_NE>;
652 defm V_CMP_GE_I64 : VOPC_I64 <0x000000a6, "V_CMP_GE_I64", COND_SGE>;
653 defm V_CMP_T_I64 : VOPC_I64 <0x000000a7, "V_CMP_T_I64">;
655 let hasSideEffects = 1 in {
657 defm V_CMPX_F_I64 : VOPCX_I64 <0x000000b0, "V_CMPX_F_I64">;
658 defm V_CMPX_LT_I64 : VOPCX_I64 <0x000000b1, "V_CMPX_LT_I64">;
659 defm V_CMPX_EQ_I64 : VOPCX_I64 <0x000000b2, "V_CMPX_EQ_I64">;
660 defm V_CMPX_LE_I64 : VOPCX_I64 <0x000000b3, "V_CMPX_LE_I64">;
661 defm V_CMPX_GT_I64 : VOPCX_I64 <0x000000b4, "V_CMPX_GT_I64">;
662 defm V_CMPX_NE_I64 : VOPCX_I64 <0x000000b5, "V_CMPX_NE_I64">;
663 defm V_CMPX_GE_I64 : VOPCX_I64 <0x000000b6, "V_CMPX_GE_I64">;
664 defm V_CMPX_T_I64 : VOPCX_I64 <0x000000b7, "V_CMPX_T_I64">;
666 } // End hasSideEffects = 1
668 defm V_CMP_F_U32 : VOPC_I32 <0x000000c0, "V_CMP_F_U32">;
669 defm V_CMP_LT_U32 : VOPC_I32 <0x000000c1, "V_CMP_LT_U32", COND_ULT>;
670 defm V_CMP_EQ_U32 : VOPC_I32 <0x000000c2, "V_CMP_EQ_U32", COND_EQ>;
671 defm V_CMP_LE_U32 : VOPC_I32 <0x000000c3, "V_CMP_LE_U32", COND_ULE>;
672 defm V_CMP_GT_U32 : VOPC_I32 <0x000000c4, "V_CMP_GT_U32", COND_UGT>;
673 defm V_CMP_NE_U32 : VOPC_I32 <0x000000c5, "V_CMP_NE_U32", COND_NE>;
674 defm V_CMP_GE_U32 : VOPC_I32 <0x000000c6, "V_CMP_GE_U32", COND_UGE>;
675 defm V_CMP_T_U32 : VOPC_I32 <0x000000c7, "V_CMP_T_U32">;
677 let hasSideEffects = 1 in {
679 defm V_CMPX_F_U32 : VOPCX_I32 <0x000000d0, "V_CMPX_F_U32">;
680 defm V_CMPX_LT_U32 : VOPCX_I32 <0x000000d1, "V_CMPX_LT_U32">;
681 defm V_CMPX_EQ_U32 : VOPCX_I32 <0x000000d2, "V_CMPX_EQ_U32">;
682 defm V_CMPX_LE_U32 : VOPCX_I32 <0x000000d3, "V_CMPX_LE_U32">;
683 defm V_CMPX_GT_U32 : VOPCX_I32 <0x000000d4, "V_CMPX_GT_U32">;
684 defm V_CMPX_NE_U32 : VOPCX_I32 <0x000000d5, "V_CMPX_NE_U32">;
685 defm V_CMPX_GE_U32 : VOPCX_I32 <0x000000d6, "V_CMPX_GE_U32">;
686 defm V_CMPX_T_U32 : VOPCX_I32 <0x000000d7, "V_CMPX_T_U32">;
688 } // End hasSideEffects = 1
690 defm V_CMP_F_U64 : VOPC_I64 <0x000000e0, "V_CMP_F_U64">;
691 defm V_CMP_LT_U64 : VOPC_I64 <0x000000e1, "V_CMP_LT_U64", COND_ULT>;
692 defm V_CMP_EQ_U64 : VOPC_I64 <0x000000e2, "V_CMP_EQ_U64", COND_EQ>;
693 defm V_CMP_LE_U64 : VOPC_I64 <0x000000e3, "V_CMP_LE_U64", COND_ULE>;
694 defm V_CMP_GT_U64 : VOPC_I64 <0x000000e4, "V_CMP_GT_U64", COND_UGT>;
695 defm V_CMP_NE_U64 : VOPC_I64 <0x000000e5, "V_CMP_NE_U64", COND_NE>;
696 defm V_CMP_GE_U64 : VOPC_I64 <0x000000e6, "V_CMP_GE_U64", COND_UGE>;
697 defm V_CMP_T_U64 : VOPC_I64 <0x000000e7, "V_CMP_T_U64">;
699 let hasSideEffects = 1 in {
701 defm V_CMPX_F_U64 : VOPCX_I64 <0x000000f0, "V_CMPX_F_U64">;
702 defm V_CMPX_LT_U64 : VOPCX_I64 <0x000000f1, "V_CMPX_LT_U64">;
703 defm V_CMPX_EQ_U64 : VOPCX_I64 <0x000000f2, "V_CMPX_EQ_U64">;
704 defm V_CMPX_LE_U64 : VOPCX_I64 <0x000000f3, "V_CMPX_LE_U64">;
705 defm V_CMPX_GT_U64 : VOPCX_I64 <0x000000f4, "V_CMPX_GT_U64">;
706 defm V_CMPX_NE_U64 : VOPCX_I64 <0x000000f5, "V_CMPX_NE_U64">;
707 defm V_CMPX_GE_U64 : VOPCX_I64 <0x000000f6, "V_CMPX_GE_U64">;
708 defm V_CMPX_T_U64 : VOPCX_I64 <0x000000f7, "V_CMPX_T_U64">;
710 } // End hasSideEffects = 1
712 defm V_CMP_CLASS_F32 : VOPC_F32 <0x00000088, "V_CMP_CLASS_F32">;
714 let hasSideEffects = 1 in {
715 defm V_CMPX_CLASS_F32 : VOPCX_F32 <0x00000098, "V_CMPX_CLASS_F32">;
716 } // End hasSideEffects = 1
718 defm V_CMP_CLASS_F64 : VOPC_F64 <0x000000a8, "V_CMP_CLASS_F64">;
720 let hasSideEffects = 1 in {
721 defm V_CMPX_CLASS_F64 : VOPCX_F64 <0x000000b8, "V_CMPX_CLASS_F64">;
722 } // End hasSideEffects = 1
724 } // End isCompare = 1
726 //===----------------------------------------------------------------------===//
728 //===----------------------------------------------------------------------===//
731 def DS_ADD_U32 : DS_1A1D_NORET <0x0, "DS_ADD_U32", VReg_32>;
732 def DS_SUB_U32 : DS_1A1D_NORET <0x1, "DS_SUB_U32", VReg_32>;
733 def DS_RSUB_U32 : DS_1A1D_NORET <0x2, "DS_RSUB_U32", VReg_32>;
734 def DS_INC_U32 : DS_1A1D_NORET <0x3, "DS_INC_U32", VReg_32>;
735 def DS_DEC_U32 : DS_1A1D_NORET <0x4, "DS_DEC_U32", VReg_32>;
736 def DS_MIN_I32 : DS_1A1D_NORET <0x5, "DS_MIN_I32", VReg_32>;
737 def DS_MAX_I32 : DS_1A1D_NORET <0x6, "DS_MAX_I32", VReg_32>;
738 def DS_MIN_U32 : DS_1A1D_NORET <0x7, "DS_MIN_U32", VReg_32>;
739 def DS_MAX_U32 : DS_1A1D_NORET <0x8, "DS_MAX_U32", VReg_32>;
740 def DS_AND_B32 : DS_1A1D_NORET <0x9, "DS_AND_B32", VReg_32>;
741 def DS_OR_B32 : DS_1A1D_NORET <0xa, "DS_OR_B32", VReg_32>;
742 def DS_XOR_B32 : DS_1A1D_NORET <0xb, "DS_XOR_B32", VReg_32>;
743 def DS_MSKOR_B32 : DS_1A1D_NORET <0xc, "DS_MSKOR_B32", VReg_32>;
744 def DS_CMPST_B32 : DS_1A2D_NORET <0x10, "DS_CMPST_B32", VReg_32>;
745 def DS_CMPST_F32 : DS_1A2D_NORET <0x11, "DS_CMPST_F32", VReg_32>;
746 def DS_MIN_F32 : DS_1A1D_NORET <0x12, "DS_MIN_F32", VReg_32>;
747 def DS_MAX_F32 : DS_1A1D_NORET <0x13, "DS_MAX_F32", VReg_32>;
749 def DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "DS_ADD_RTN_U32", VReg_32, "DS_ADD_U32">;
750 def DS_SUB_RTN_U32 : DS_1A1D_RET <0x21, "DS_SUB_RTN_U32", VReg_32, "DS_SUB_U32">;
751 def DS_RSUB_RTN_U32 : DS_1A1D_RET <0x22, "DS_RSUB_RTN_U32", VReg_32, "DS_RSUB_U32">;
752 def DS_INC_RTN_U32 : DS_1A1D_RET <0x23, "DS_INC_RTN_U32", VReg_32, "DS_INC_U32">;
753 def DS_DEC_RTN_U32 : DS_1A1D_RET <0x24, "DS_DEC_RTN_U32", VReg_32, "DS_DEC_U32">;
754 def DS_MIN_RTN_I32 : DS_1A1D_RET <0x25, "DS_MIN_RTN_I32", VReg_32, "DS_MIN_I32">;
755 def DS_MAX_RTN_I32 : DS_1A1D_RET <0x26, "DS_MAX_RTN_I32", VReg_32, "DS_MAX_I32">;
756 def DS_MIN_RTN_U32 : DS_1A1D_RET <0x27, "DS_MIN_RTN_U32", VReg_32, "DS_MIN_U32">;
757 def DS_MAX_RTN_U32 : DS_1A1D_RET <0x28, "DS_MAX_RTN_U32", VReg_32, "DS_MAX_U32">;
758 def DS_AND_RTN_B32 : DS_1A1D_RET <0x29, "DS_AND_RTN_B32", VReg_32, "DS_AND_B32">;
759 def DS_OR_RTN_B32 : DS_1A1D_RET <0x2a, "DS_OR_RTN_B32", VReg_32, "DS_OR_B32">;
760 def DS_XOR_RTN_B32 : DS_1A1D_RET <0x2b, "DS_XOR_RTN_B32", VReg_32, "DS_XOR_B32">;
761 def DS_MSKOR_RTN_B32 : DS_1A1D_RET <0x2c, "DS_MSKOR_RTN_B32", VReg_32, "DS_MSKOR_B32">;
762 def DS_WRXCHG_RTN_B32 : DS_1A1D_RET <0x2d, "DS_WRXCHG_RTN_B32", VReg_32>;
763 //def DS_WRXCHG2_RTN_B32 : DS_2A0D_RET <0x2e, "DS_WRXCHG2_RTN_B32", VReg_32, "DS_WRXCHG2_B32">;
764 //def DS_WRXCHG2ST64_RTN_B32 : DS_2A0D_RET <0x2f, "DS_WRXCHG2_RTN_B32", VReg_32, "DS_WRXCHG2ST64_B32">;
765 def DS_CMPST_RTN_B32 : DS_1A2D_RET <0x30, "DS_CMPST_RTN_B32", VReg_32, "DS_CMPST_B32">;
766 def DS_CMPST_RTN_F32 : DS_1A2D_RET <0x31, "DS_CMPST_RTN_F32", VReg_32, "DS_CMPST_F32">;
767 def DS_MIN_RTN_F32 : DS_1A1D_RET <0x32, "DS_MIN_RTN_F32", VReg_32, "DS_MIN_F32">;
768 def DS_MAX_RTN_F32 : DS_1A1D_RET <0x33, "DS_MAX_RTN_F32", VReg_32, "DS_MAX_F32">;
770 let SubtargetPredicate = isCI in {
771 def DS_WRAP_RTN_F32 : DS_1A1D_RET <0x34, "DS_WRAP_RTN_F32", VReg_32, "DS_WRAP_F32">;
775 def DS_ADD_U64 : DS_1A1D_NORET <0x40, "DS_ADD_U64", VReg_64>;
776 def DS_SUB_U64 : DS_1A1D_NORET <0x41, "DS_SUB_U64", VReg_64>;
777 def DS_RSUB_U64 : DS_1A1D_NORET <0x42, "DS_RSUB_U64", VReg_64>;
778 def DS_INC_U64 : DS_1A1D_NORET <0x43, "DS_INC_U64", VReg_64>;
779 def DS_DEC_U64 : DS_1A1D_NORET <0x44, "DS_DEC_U64", VReg_64>;
780 def DS_MIN_I64 : DS_1A1D_NORET <0x45, "DS_MIN_I64", VReg_64>;
781 def DS_MAX_I64 : DS_1A1D_NORET <0x46, "DS_MAX_I64", VReg_64>;
782 def DS_MIN_U64 : DS_1A1D_NORET <0x47, "DS_MIN_U64", VReg_64>;
783 def DS_MAX_U64 : DS_1A1D_NORET <0x48, "DS_MAX_U64", VReg_64>;
784 def DS_AND_B64 : DS_1A1D_NORET <0x49, "DS_AND_B64", VReg_64>;
785 def DS_OR_B64 : DS_1A1D_NORET <0x4a, "DS_OR_B64", VReg_64>;
786 def DS_XOR_B64 : DS_1A1D_NORET <0x4b, "DS_XOR_B64", VReg_64>;
787 def DS_MSKOR_B64 : DS_1A1D_NORET <0x4c, "DS_MSKOR_B64", VReg_64>;
788 def DS_CMPST_B64 : DS_1A2D_NORET <0x50, "DS_CMPST_B64", VReg_64>;
789 def DS_CMPST_F64 : DS_1A2D_NORET <0x51, "DS_CMPST_F64", VReg_64>;
790 def DS_MIN_F64 : DS_1A1D_NORET <0x52, "DS_MIN_F64", VReg_64>;
791 def DS_MAX_F64 : DS_1A1D_NORET <0x53, "DS_MAX_F64", VReg_64>;
793 def DS_ADD_RTN_U64 : DS_1A1D_RET <0x60, "DS_ADD_RTN_U64", VReg_64, "DS_ADD_U64">;
794 def DS_SUB_RTN_U64 : DS_1A1D_RET <0x61, "DS_SUB_RTN_U64", VReg_64, "DS_SUB_U64">;
795 def DS_RSUB_RTN_U64 : DS_1A1D_RET <0x62, "DS_RSUB_RTN_U64", VReg_64, "DS_RSUB_U64">;
796 def DS_INC_RTN_U64 : DS_1A1D_RET <0x63, "DS_INC_RTN_U64", VReg_64, "DS_INC_U64">;
797 def DS_DEC_RTN_U64 : DS_1A1D_RET <0x64, "DS_DEC_RTN_U64", VReg_64, "DS_DEC_U64">;
798 def DS_MIN_RTN_I64 : DS_1A1D_RET <0x65, "DS_MIN_RTN_I64", VReg_64, "DS_MIN_I64">;
799 def DS_MAX_RTN_I64 : DS_1A1D_RET <0x66, "DS_MAX_RTN_I64", VReg_64, "DS_MAX_I64">;
800 def DS_MIN_RTN_U64 : DS_1A1D_RET <0x67, "DS_MIN_RTN_U64", VReg_64, "DS_MIN_U64">;
801 def DS_MAX_RTN_U64 : DS_1A1D_RET <0x68, "DS_MAX_RTN_U64", VReg_64, "DS_MAX_U64">;
802 def DS_AND_RTN_B64 : DS_1A1D_RET <0x69, "DS_AND_RTN_B64", VReg_64, "DS_AND_B64">;
803 def DS_OR_RTN_B64 : DS_1A1D_RET <0x6a, "DS_OR_RTN_B64", VReg_64, "DS_OR_B64">;
804 def DS_XOR_RTN_B64 : DS_1A1D_RET <0x6b, "DS_XOR_RTN_B64", VReg_64, "DS_XOR_B64">;
805 def DS_MSKOR_RTN_B64 : DS_1A1D_RET <0x6c, "DS_MSKOR_RTN_B64", VReg_64, "DS_MSKOR_B64">;
806 def DS_WRXCHG_RTN_B64 : DS_1A1D_RET <0x6d, "DS_WRXCHG_RTN_B64", VReg_64, "DS_WRXCHG_B64">;
807 //def DS_WRXCHG2_RTN_B64 : DS_2A0D_RET <0x6e, "DS_WRXCHG2_RTN_B64", VReg_64, "DS_WRXCHG2_B64">;
808 //def DS_WRXCHG2ST64_RTN_B64 : DS_2A0D_RET <0x6f, "DS_WRXCHG2_RTN_B64", VReg_64, "DS_WRXCHG2ST64_B64">;
809 def DS_CMPST_RTN_B64 : DS_1A2D_RET <0x70, "DS_CMPST_RTN_B64", VReg_64, "DS_CMPST_B64">;
810 def DS_CMPST_RTN_F64 : DS_1A2D_RET <0x71, "DS_CMPST_RTN_F64", VReg_64, "DS_CMPST_F64">;
811 def DS_MIN_RTN_F64 : DS_1A1D_RET <0x72, "DS_MIN_F64", VReg_64, "DS_MIN_F64">;
812 def DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "DS_MAX_F64", VReg_64, "DS_MAX_F64">;
814 //let SubtargetPredicate = isCI in {
815 // DS_CONDXCHG32_RTN_B64
816 // DS_CONDXCHG32_RTN_B128
819 // TODO: _SRC2_* forms
821 def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>;
822 def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "DS_WRITE_B8", VReg_32>;
823 def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "DS_WRITE_B16", VReg_32>;
824 def DS_WRITE_B64 : DS_Store_Helper <0x00000004d, "DS_WRITE_B64", VReg_64>;
826 def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>;
827 def DS_READ_I8 : DS_Load_Helper <0x00000039, "DS_READ_I8", VReg_32>;
828 def DS_READ_U8 : DS_Load_Helper <0x0000003a, "DS_READ_U8", VReg_32>;
829 def DS_READ_I16 : DS_Load_Helper <0x0000003b, "DS_READ_I16", VReg_32>;
830 def DS_READ_U16 : DS_Load_Helper <0x0000003c, "DS_READ_U16", VReg_32>;
831 def DS_READ_B64 : DS_Load_Helper <0x00000076, "DS_READ_B64", VReg_64>;
834 def DS_WRITE2_B32 : DS_Store2_Helper <0x0000000E, "DS_WRITE2_B32", VReg_32>;
835 def DS_WRITE2ST64_B32 : DS_Store2_Helper <0x0000000F, "DS_WRITE2ST64_B32", VReg_32>;
836 def DS_WRITE2_B64 : DS_Store2_Helper <0x0000004E, "DS_WRITE2_B64", VReg_64>;
837 def DS_WRITE2ST64_B64 : DS_Store2_Helper <0x0000004F, "DS_WRITE2ST64_B64", VReg_64>;
839 def DS_READ2_B32 : DS_Load2_Helper <0x00000037, "DS_READ2_B32", VReg_64>;
840 def DS_READ2ST64_B32 : DS_Load2_Helper <0x00000038, "DS_READ2ST64_B32", VReg_64>;
841 def DS_READ2_B64 : DS_Load2_Helper <0x00000075, "DS_READ2_B64", VReg_128>;
842 def DS_READ2ST64_B64 : DS_Load2_Helper <0x00000076, "DS_READ2ST64_B64", VReg_128>;
844 //===----------------------------------------------------------------------===//
845 // MUBUF Instructions
846 //===----------------------------------------------------------------------===//
848 //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>;
849 //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>;
850 //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>;
851 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>;
852 //def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>;
853 //def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>;
854 //def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>;
855 //def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>;
856 defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <
857 0x00000008, "BUFFER_LOAD_UBYTE", VReg_32, i32, az_extloadi8_global
859 defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <
860 0x00000009, "BUFFER_LOAD_SBYTE", VReg_32, i32, sextloadi8_global
862 defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <
863 0x0000000a, "BUFFER_LOAD_USHORT", VReg_32, i32, az_extloadi16_global
865 defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <
866 0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32, i32, sextloadi16_global
868 defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <
869 0x0000000c, "BUFFER_LOAD_DWORD", VReg_32, i32, global_load
871 defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <
872 0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64, v2i32, global_load
874 defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <
875 0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128, v4i32, global_load
878 defm BUFFER_STORE_BYTE : MUBUF_Store_Helper <
879 0x00000018, "BUFFER_STORE_BYTE", VReg_32, i32, truncstorei8_global
882 defm BUFFER_STORE_SHORT : MUBUF_Store_Helper <
883 0x0000001a, "BUFFER_STORE_SHORT", VReg_32, i32, truncstorei16_global
886 defm BUFFER_STORE_DWORD : MUBUF_Store_Helper <
887 0x0000001c, "BUFFER_STORE_DWORD", VReg_32, i32, global_store
890 defm BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper <
891 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64, v2i32, global_store
894 defm BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper <
895 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128, v4i32, global_store
897 //def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>;
898 //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>;
899 //def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>;
900 //def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>;
901 //def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>;
902 //def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>;
903 //def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>;
904 //def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>;
905 //def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>;
906 //def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>;
907 //def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>;
908 //def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>;
909 //def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>;
910 //def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>;
911 //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>;
912 //def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>;
913 //def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>;
914 //def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>;
915 //def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>;
916 //def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>;
917 //def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>;
918 //def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>;
919 //def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>;
920 //def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>;
921 //def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>;
922 //def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>;
923 //def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>;
924 //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>;
925 //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>;
926 //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>;
927 //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>;
928 //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>;
929 //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>;
930 //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>;
931 //def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>;
932 //def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>;
934 //===----------------------------------------------------------------------===//
935 // MTBUF Instructions
936 //===----------------------------------------------------------------------===//
938 //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>;
939 //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>;
940 //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>;
941 def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>;
942 def TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "TBUFFER_STORE_FORMAT_X", VReg_32>;
943 def TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FORMAT_XY", VReg_64>;
944 def TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>;
945 def TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>;
947 //===----------------------------------------------------------------------===//
949 //===----------------------------------------------------------------------===//
951 defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "IMAGE_LOAD">;
952 defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "IMAGE_LOAD_MIP">;
953 //def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>;
954 //def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>;
955 //def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>;
956 //def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>;
957 //def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>;
958 //def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>;
959 //def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>;
960 //def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>;
961 defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "IMAGE_GET_RESINFO">;
962 //def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>;
963 //def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>;
964 //def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>;
965 //def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>;
966 //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>;
967 //def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>;
968 //def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>;
969 //def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>;
970 //def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>;
971 //def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>;
972 //def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>;
973 //def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>;
974 //def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>;
975 //def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>;
976 //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>;
977 //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>;
978 //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>;
979 defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">;
980 defm IMAGE_SAMPLE_CL : MIMG_Sampler <0x00000021, "IMAGE_SAMPLE_CL">;
981 defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">;
982 defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, "IMAGE_SAMPLE_D_CL">;
983 defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">;
984 defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">;
985 defm IMAGE_SAMPLE_B_CL : MIMG_Sampler <0x00000026, "IMAGE_SAMPLE_B_CL">;
986 defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, "IMAGE_SAMPLE_LZ">;
987 defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">;
988 defm IMAGE_SAMPLE_C_CL : MIMG_Sampler <0x00000029, "IMAGE_SAMPLE_C_CL">;
989 defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">;
990 defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, "IMAGE_SAMPLE_C_D_CL">;
991 defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">;
992 defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">;
993 defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler <0x0000002e, "IMAGE_SAMPLE_C_B_CL">;
994 defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, "IMAGE_SAMPLE_C_LZ">;
995 defm IMAGE_SAMPLE_O : MIMG_Sampler <0x00000030, "IMAGE_SAMPLE_O">;
996 defm IMAGE_SAMPLE_CL_O : MIMG_Sampler <0x00000031, "IMAGE_SAMPLE_CL_O">;
997 defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, "IMAGE_SAMPLE_D_O">;
998 defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, "IMAGE_SAMPLE_D_CL_O">;
999 defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, "IMAGE_SAMPLE_L_O">;
1000 defm IMAGE_SAMPLE_B_O : MIMG_Sampler <0x00000035, "IMAGE_SAMPLE_B_O">;
1001 defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler <0x00000036, "IMAGE_SAMPLE_B_CL_O">;
1002 defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, "IMAGE_SAMPLE_LZ_O">;
1003 defm IMAGE_SAMPLE_C_O : MIMG_Sampler <0x00000038, "IMAGE_SAMPLE_C_O">;
1004 defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler <0x00000039, "IMAGE_SAMPLE_C_CL_O">;
1005 defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, "IMAGE_SAMPLE_C_D_O">;
1006 defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, "IMAGE_SAMPLE_C_D_CL_O">;
1007 defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, "IMAGE_SAMPLE_C_L_O">;
1008 defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler <0x0000003d, "IMAGE_SAMPLE_C_B_O">;
1009 defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler <0x0000003e, "IMAGE_SAMPLE_C_B_CL_O">;
1010 defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, "IMAGE_SAMPLE_C_LZ_O">;
1011 defm IMAGE_GATHER4 : MIMG_Gather <0x00000040, "IMAGE_GATHER4">;
1012 defm IMAGE_GATHER4_CL : MIMG_Gather <0x00000041, "IMAGE_GATHER4_CL">;
1013 defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, "IMAGE_GATHER4_L">;
1014 defm IMAGE_GATHER4_B : MIMG_Gather <0x00000045, "IMAGE_GATHER4_B">;
1015 defm IMAGE_GATHER4_B_CL : MIMG_Gather <0x00000046, "IMAGE_GATHER4_B_CL">;
1016 defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, "IMAGE_GATHER4_LZ">;
1017 defm IMAGE_GATHER4_C : MIMG_Gather <0x00000048, "IMAGE_GATHER4_C">;
1018 defm IMAGE_GATHER4_C_CL : MIMG_Gather <0x00000049, "IMAGE_GATHER4_C_CL">;
1019 defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, "IMAGE_GATHER4_C_L">;
1020 defm IMAGE_GATHER4_C_B : MIMG_Gather <0x0000004d, "IMAGE_GATHER4_C_B">;
1021 defm IMAGE_GATHER4_C_B_CL : MIMG_Gather <0x0000004e, "IMAGE_GATHER4_C_B_CL">;
1022 defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, "IMAGE_GATHER4_C_LZ">;
1023 defm IMAGE_GATHER4_O : MIMG_Gather <0x00000050, "IMAGE_GATHER4_O">;
1024 defm IMAGE_GATHER4_CL_O : MIMG_Gather <0x00000051, "IMAGE_GATHER4_CL_O">;
1025 defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, "IMAGE_GATHER4_L_O">;
1026 defm IMAGE_GATHER4_B_O : MIMG_Gather <0x00000055, "IMAGE_GATHER4_B_O">;
1027 defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, "IMAGE_GATHER4_B_CL_O">;
1028 defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, "IMAGE_GATHER4_LZ_O">;
1029 defm IMAGE_GATHER4_C_O : MIMG_Gather <0x00000058, "IMAGE_GATHER4_C_O">;
1030 defm IMAGE_GATHER4_C_CL_O : MIMG_Gather <0x00000059, "IMAGE_GATHER4_C_CL_O">;
1031 defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, "IMAGE_GATHER4_C_L_O">;
1032 defm IMAGE_GATHER4_C_B_O : MIMG_Gather <0x0000005d, "IMAGE_GATHER4_C_B_O">;
1033 defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather <0x0000005e, "IMAGE_GATHER4_C_B_CL_O">;
1034 defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, "IMAGE_GATHER4_C_LZ_O">;
1035 defm IMAGE_GET_LOD : MIMG_Sampler <0x00000060, "IMAGE_GET_LOD">;
1036 defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, "IMAGE_SAMPLE_CD">;
1037 defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, "IMAGE_SAMPLE_CD_CL">;
1038 defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, "IMAGE_SAMPLE_C_CD">;
1039 defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, "IMAGE_SAMPLE_C_CD_CL">;
1040 defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, "IMAGE_SAMPLE_CD_O">;
1041 defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, "IMAGE_SAMPLE_CD_CL_O">;
1042 defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, "IMAGE_SAMPLE_C_CD_O">;
1043 defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, "IMAGE_SAMPLE_C_CD_CL_O">;
1044 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>;
1045 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>;
1047 //===----------------------------------------------------------------------===//
1048 // Flat Instructions
1049 //===----------------------------------------------------------------------===//
1051 let Predicates = [HasFlatAddressSpace] in {
1052 def FLAT_LOAD_UBYTE : FLAT_Load_Helper <0x00000008, "FLAT_LOAD_UBYTE", VReg_32>;
1053 def FLAT_LOAD_SBYTE : FLAT_Load_Helper <0x00000009, "FLAT_LOAD_SBYTE", VReg_32>;
1054 def FLAT_LOAD_USHORT : FLAT_Load_Helper <0x0000000a, "FLAT_LOAD_USHORT", VReg_32>;
1055 def FLAT_LOAD_SSHORT : FLAT_Load_Helper <0x0000000b, "FLAT_LOAD_SSHORT", VReg_32>;
1056 def FLAT_LOAD_DWORD : FLAT_Load_Helper <0x0000000c, "FLAT_LOAD_DWORD", VReg_32>;
1057 def FLAT_LOAD_DWORDX2 : FLAT_Load_Helper <0x0000000d, "FLAT_LOAD_DWORDX2", VReg_64>;
1058 def FLAT_LOAD_DWORDX4 : FLAT_Load_Helper <0x0000000e, "FLAT_LOAD_DWORDX4", VReg_128>;
1059 def FLAT_LOAD_DWORDX3 : FLAT_Load_Helper <0x00000010, "FLAT_LOAD_DWORDX3", VReg_96>;
1061 def FLAT_STORE_BYTE : FLAT_Store_Helper <
1062 0x00000018, "FLAT_STORE_BYTE", VReg_32
1065 def FLAT_STORE_SHORT : FLAT_Store_Helper <
1066 0x0000001a, "FLAT_STORE_SHORT", VReg_32
1069 def FLAT_STORE_DWORD : FLAT_Store_Helper <
1070 0x0000001c, "FLAT_STORE_DWORD", VReg_32
1073 def FLAT_STORE_DWORDX2 : FLAT_Store_Helper <
1074 0x0000001d, "FLAT_STORE_DWORDX2", VReg_64
1077 def FLAT_STORE_DWORDX4 : FLAT_Store_Helper <
1078 0x0000001e, "FLAT_STORE_DWORDX4", VReg_128
1081 def FLAT_STORE_DWORDX3 : FLAT_Store_Helper <
1082 0x0000001e, "FLAT_STORE_DWORDX3", VReg_96
1085 //def FLAT_ATOMIC_SWAP : FLAT_ <0x00000030, "FLAT_ATOMIC_SWAP", []>;
1086 //def FLAT_ATOMIC_CMPSWAP : FLAT_ <0x00000031, "FLAT_ATOMIC_CMPSWAP", []>;
1087 //def FLAT_ATOMIC_ADD : FLAT_ <0x00000032, "FLAT_ATOMIC_ADD", []>;
1088 //def FLAT_ATOMIC_SUB : FLAT_ <0x00000033, "FLAT_ATOMIC_SUB", []>;
1089 //def FLAT_ATOMIC_RSUB : FLAT_ <0x00000034, "FLAT_ATOMIC_RSUB", []>;
1090 //def FLAT_ATOMIC_SMIN : FLAT_ <0x00000035, "FLAT_ATOMIC_SMIN", []>;
1091 //def FLAT_ATOMIC_UMIN : FLAT_ <0x00000036, "FLAT_ATOMIC_UMIN", []>;
1092 //def FLAT_ATOMIC_SMAX : FLAT_ <0x00000037, "FLAT_ATOMIC_SMAX", []>;
1093 //def FLAT_ATOMIC_UMAX : FLAT_ <0x00000038, "FLAT_ATOMIC_UMAX", []>;
1094 //def FLAT_ATOMIC_AND : FLAT_ <0x00000039, "FLAT_ATOMIC_AND", []>;
1095 //def FLAT_ATOMIC_OR : FLAT_ <0x0000003a, "FLAT_ATOMIC_OR", []>;
1096 //def FLAT_ATOMIC_XOR : FLAT_ <0x0000003b, "FLAT_ATOMIC_XOR", []>;
1097 //def FLAT_ATOMIC_INC : FLAT_ <0x0000003c, "FLAT_ATOMIC_INC", []>;
1098 //def FLAT_ATOMIC_DEC : FLAT_ <0x0000003d, "FLAT_ATOMIC_DEC", []>;
1099 //def FLAT_ATOMIC_FCMPSWAP : FLAT_ <0x0000003e, "FLAT_ATOMIC_FCMPSWAP", []>;
1100 //def FLAT_ATOMIC_FMIN : FLAT_ <0x0000003f, "FLAT_ATOMIC_FMIN", []>;
1101 //def FLAT_ATOMIC_FMAX : FLAT_ <0x00000040, "FLAT_ATOMIC_FMAX", []>;
1102 //def FLAT_ATOMIC_SWAP_X2 : FLAT_X2 <0x00000050, "FLAT_ATOMIC_SWAP_X2", []>;
1103 //def FLAT_ATOMIC_CMPSWAP_X2 : FLAT_X2 <0x00000051, "FLAT_ATOMIC_CMPSWAP_X2", []>;
1104 //def FLAT_ATOMIC_ADD_X2 : FLAT_X2 <0x00000052, "FLAT_ATOMIC_ADD_X2", []>;
1105 //def FLAT_ATOMIC_SUB_X2 : FLAT_X2 <0x00000053, "FLAT_ATOMIC_SUB_X2", []>;
1106 //def FLAT_ATOMIC_RSUB_X2 : FLAT_X2 <0x00000054, "FLAT_ATOMIC_RSUB_X2", []>;
1107 //def FLAT_ATOMIC_SMIN_X2 : FLAT_X2 <0x00000055, "FLAT_ATOMIC_SMIN_X2", []>;
1108 //def FLAT_ATOMIC_UMIN_X2 : FLAT_X2 <0x00000056, "FLAT_ATOMIC_UMIN_X2", []>;
1109 //def FLAT_ATOMIC_SMAX_X2 : FLAT_X2 <0x00000057, "FLAT_ATOMIC_SMAX_X2", []>;
1110 //def FLAT_ATOMIC_UMAX_X2 : FLAT_X2 <0x00000058, "FLAT_ATOMIC_UMAX_X2", []>;
1111 //def FLAT_ATOMIC_AND_X2 : FLAT_X2 <0x00000059, "FLAT_ATOMIC_AND_X2", []>;
1112 //def FLAT_ATOMIC_OR_X2 : FLAT_X2 <0x0000005a, "FLAT_ATOMIC_OR_X2", []>;
1113 //def FLAT_ATOMIC_XOR_X2 : FLAT_X2 <0x0000005b, "FLAT_ATOMIC_XOR_X2", []>;
1114 //def FLAT_ATOMIC_INC_X2 : FLAT_X2 <0x0000005c, "FLAT_ATOMIC_INC_X2", []>;
1115 //def FLAT_ATOMIC_DEC_X2 : FLAT_X2 <0x0000005d, "FLAT_ATOMIC_DEC_X2", []>;
1116 //def FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_X2 <0x0000005e, "FLAT_ATOMIC_FCMPSWAP_X2", []>;
1117 //def FLAT_ATOMIC_FMIN_X2 : FLAT_X2 <0x0000005f, "FLAT_ATOMIC_FMIN_X2", []>;
1118 //def FLAT_ATOMIC_FMAX_X2 : FLAT_X2 <0x00000060, "FLAT_ATOMIC_FMAX_X2", []>;
1120 } // End HasFlatAddressSpace predicate
1121 //===----------------------------------------------------------------------===//
1122 // VOP1 Instructions
1123 //===----------------------------------------------------------------------===//
1125 //def V_NOP : VOP1_ <0x00000000, "V_NOP", []>;
1127 let isMoveImm = 1 in {
1128 defm V_MOV_B32 : VOP1Inst <0x00000001, "V_MOV_B32", VOP_I32_I32>;
1129 } // End isMoveImm = 1
1131 let Uses = [EXEC] in {
1133 def V_READFIRSTLANE_B32 : VOP1 <
1135 (outs SReg_32:$vdst),
1136 (ins VReg_32:$src0),
1137 "V_READFIRSTLANE_B32 $vdst, $src0",
1143 defm V_CVT_I32_F64 : VOP1Inst <0x00000003, "V_CVT_I32_F64",
1144 VOP_I32_F64, fp_to_sint
1146 defm V_CVT_F64_I32 : VOP1Inst <0x00000004, "V_CVT_F64_I32",
1147 VOP_F64_I32, sint_to_fp
1149 defm V_CVT_F32_I32 : VOP1Inst <0x00000005, "V_CVT_F32_I32",
1150 VOP_F32_I32, sint_to_fp
1152 defm V_CVT_F32_U32 : VOP1Inst <0x00000006, "V_CVT_F32_U32",
1153 VOP_F32_I32, uint_to_fp
1155 defm V_CVT_U32_F32 : VOP1Inst <0x00000007, "V_CVT_U32_F32",
1156 VOP_I32_F32, fp_to_uint
1158 defm V_CVT_I32_F32 : VOP1Inst <0x00000008, "V_CVT_I32_F32",
1159 VOP_I32_F32, fp_to_sint
1161 defm V_MOV_FED_B32 : VOP1Inst <0x00000009, "V_MOV_FED_B32", VOP_I32_I32>;
1162 defm V_CVT_F16_F32 : VOP1Inst <0x0000000a, "V_CVT_F16_F32",
1163 VOP_I32_F32, fp_to_f16
1165 defm V_CVT_F32_F16 : VOP1Inst <0x0000000b, "V_CVT_F32_F16",
1166 VOP_F32_I32, f16_to_fp
1168 //defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>;
1169 //defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>;
1170 //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>;
1171 defm V_CVT_F32_F64 : VOP1Inst <0x0000000f, "V_CVT_F32_F64",
1174 defm V_CVT_F64_F32 : VOP1Inst <0x00000010, "V_CVT_F64_F32",
1175 VOP_F64_F32, fextend
1177 defm V_CVT_F32_UBYTE0 : VOP1Inst <0x00000011, "V_CVT_F32_UBYTE0",
1178 VOP_F32_I32, AMDGPUcvt_f32_ubyte0
1180 defm V_CVT_F32_UBYTE1 : VOP1Inst <0x00000012, "V_CVT_F32_UBYTE1",
1181 VOP_F32_I32, AMDGPUcvt_f32_ubyte1
1183 defm V_CVT_F32_UBYTE2 : VOP1Inst <0x00000013, "V_CVT_F32_UBYTE2",
1184 VOP_F32_I32, AMDGPUcvt_f32_ubyte2
1186 defm V_CVT_F32_UBYTE3 : VOP1Inst <0x00000014, "V_CVT_F32_UBYTE3",
1187 VOP_F32_I32, AMDGPUcvt_f32_ubyte3
1189 defm V_CVT_U32_F64 : VOP1Inst <0x00000015, "V_CVT_U32_F64",
1190 VOP_I32_F64, fp_to_uint
1192 defm V_CVT_F64_U32 : VOP1Inst <0x00000016, "V_CVT_F64_U32",
1193 VOP_F64_I32, uint_to_fp
1196 defm V_FRACT_F32 : VOP1Inst <0x00000020, "V_FRACT_F32",
1197 VOP_F32_F32, AMDGPUfract
1199 defm V_TRUNC_F32 : VOP1Inst <0x00000021, "V_TRUNC_F32",
1202 defm V_CEIL_F32 : VOP1Inst <0x00000022, "V_CEIL_F32",
1205 defm V_RNDNE_F32 : VOP1Inst <0x00000023, "V_RNDNE_F32",
1208 defm V_FLOOR_F32 : VOP1Inst <0x00000024, "V_FLOOR_F32",
1211 defm V_EXP_F32 : VOP1Inst <0x00000025, "V_EXP_F32",
1214 defm V_LOG_CLAMP_F32 : VOP1Inst <0x00000026, "V_LOG_CLAMP_F32", VOP_F32_F32>;
1215 defm V_LOG_F32 : VOP1Inst <0x00000027, "V_LOG_F32",
1219 defm V_RCP_CLAMP_F32 : VOP1Inst <0x00000028, "V_RCP_CLAMP_F32", VOP_F32_F32>;
1220 defm V_RCP_LEGACY_F32 : VOP1Inst <0x00000029, "V_RCP_LEGACY_F32", VOP_F32_F32>;
1221 defm V_RCP_F32 : VOP1Inst <0x0000002a, "V_RCP_F32",
1222 VOP_F32_F32, AMDGPUrcp
1224 defm V_RCP_IFLAG_F32 : VOP1Inst <0x0000002b, "V_RCP_IFLAG_F32", VOP_F32_F32>;
1225 defm V_RSQ_CLAMP_F32 : VOP1Inst <0x0000002c, "V_RSQ_CLAMP_F32",
1226 VOP_F32_F32, AMDGPUrsq_clamped
1228 defm V_RSQ_LEGACY_F32 : VOP1Inst <
1229 0x0000002d, "V_RSQ_LEGACY_F32",
1230 VOP_F32_F32, AMDGPUrsq_legacy
1232 defm V_RSQ_F32 : VOP1Inst <0x0000002e, "V_RSQ_F32",
1233 VOP_F32_F32, AMDGPUrsq
1235 defm V_RCP_F64 : VOP1Inst <0x0000002f, "V_RCP_F64",
1236 VOP_F64_F64, AMDGPUrcp
1238 defm V_RCP_CLAMP_F64 : VOP1Inst <0x00000030, "V_RCP_CLAMP_F64", VOP_F64_F64>;
1239 defm V_RSQ_F64 : VOP1Inst <0x00000031, "V_RSQ_F64",
1240 VOP_F64_F64, AMDGPUrsq
1242 defm V_RSQ_CLAMP_F64 : VOP1Inst <0x00000032, "V_RSQ_CLAMP_F64",
1243 VOP_F64_F64, AMDGPUrsq_clamped
1245 defm V_SQRT_F32 : VOP1Inst <0x00000033, "V_SQRT_F32",
1248 defm V_SQRT_F64 : VOP1Inst <0x00000034, "V_SQRT_F64",
1251 defm V_SIN_F32 : VOP1Inst <0x00000035, "V_SIN_F32",
1252 VOP_F32_F32, AMDGPUsin
1254 defm V_COS_F32 : VOP1Inst <0x00000036, "V_COS_F32",
1255 VOP_F32_F32, AMDGPUcos
1257 defm V_NOT_B32 : VOP1Inst <0x00000037, "V_NOT_B32", VOP_I32_I32>;
1258 defm V_BFREV_B32 : VOP1Inst <0x00000038, "V_BFREV_B32", VOP_I32_I32>;
1259 defm V_FFBH_U32 : VOP1Inst <0x00000039, "V_FFBH_U32", VOP_I32_I32>;
1260 defm V_FFBL_B32 : VOP1Inst <0x0000003a, "V_FFBL_B32", VOP_I32_I32>;
1261 defm V_FFBH_I32 : VOP1Inst <0x0000003b, "V_FFBH_I32", VOP_I32_I32>;
1262 //defm V_FREXP_EXP_I32_F64 : VOPInst <0x0000003c, "V_FREXP_EXP_I32_F64", VOP_I32_F32>;
1263 defm V_FREXP_MANT_F64 : VOP1Inst <0x0000003d, "V_FREXP_MANT_F64", VOP_F64_F64>;
1264 defm V_FRACT_F64 : VOP1Inst <0x0000003e, "V_FRACT_F64", VOP_F64_F64>;
1265 //defm V_FREXP_EXP_I32_F32 : VOPInst <0x0000003f, "V_FREXP_EXP_I32_F32", VOP_I32_F32>;
1266 defm V_FREXP_MANT_F32 : VOP1Inst <0x00000040, "V_FREXP_MANT_F32", VOP_F32_F32>;
1267 //def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>;
1268 defm V_MOVRELD_B32 : VOP1Inst <0x00000042, "V_MOVRELD_B32", VOP_I32_I32>;
1269 defm V_MOVRELS_B32 : VOP1Inst <0x00000043, "V_MOVRELS_B32", VOP_I32_I32>;
1270 defm V_MOVRELSD_B32 : VOP1Inst <0x00000044, "V_MOVRELSD_B32", VOP_I32_I32>;
1273 //===----------------------------------------------------------------------===//
1274 // VINTRP Instructions
1275 //===----------------------------------------------------------------------===//
1277 def V_INTERP_P1_F32 : VINTRP <
1279 (outs VReg_32:$dst),
1280 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1281 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]",
1283 let DisableEncoding = "$m0";
1286 def V_INTERP_P2_F32 : VINTRP <
1288 (outs VReg_32:$dst),
1289 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1290 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]",
1293 let Constraints = "$src0 = $dst";
1294 let DisableEncoding = "$src0,$m0";
1298 def V_INTERP_MOV_F32 : VINTRP <
1300 (outs VReg_32:$dst),
1301 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1302 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]",
1304 let DisableEncoding = "$m0";
1307 //===----------------------------------------------------------------------===//
1308 // VOP2 Instructions
1309 //===----------------------------------------------------------------------===//
1311 def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
1312 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc),
1313 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]",
1316 let DisableEncoding = "$vcc";
1319 def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst),
1320 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2),
1321 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2",
1322 [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))]
1324 let src0_modifiers = 0;
1325 let src1_modifiers = 0;
1326 let src2_modifiers = 0;
1329 def V_READLANE_B32 : VOP2 <
1331 (outs SReg_32:$vdst),
1332 (ins VReg_32:$src0, SSrc_32:$vsrc1),
1333 "V_READLANE_B32 $vdst, $src0, $vsrc1",
1337 def V_WRITELANE_B32 : VOP2 <
1339 (outs VReg_32:$vdst),
1340 (ins SReg_32:$src0, SSrc_32:$vsrc1),
1341 "V_WRITELANE_B32 $vdst, $src0, $vsrc1",
1345 let isCommutable = 1 in {
1346 defm V_ADD_F32 : VOP2Inst <0x00000003, "V_ADD_F32",
1347 VOP_F32_F32_F32, fadd
1350 defm V_SUB_F32 : VOP2Inst <0x00000004, "V_SUB_F32", VOP_F32_F32_F32, fsub>;
1351 defm V_SUBREV_F32 : VOP2Inst <0x00000005, "V_SUBREV_F32",
1352 VOP_F32_F32_F32, null_frag, "V_SUB_F32"
1354 } // End isCommutable = 1
1356 defm V_MAC_LEGACY_F32 : VOP2Inst <0x00000006, "V_MAC_LEGACY_F32",
1360 let isCommutable = 1 in {
1362 defm V_MUL_LEGACY_F32 : VOP2Inst <
1363 0x00000007, "V_MUL_LEGACY_F32",
1364 VOP_F32_F32_F32, int_AMDGPU_mul
1367 defm V_MUL_F32 : VOP2Inst <0x00000008, "V_MUL_F32",
1368 VOP_F32_F32_F32, fmul
1372 defm V_MUL_I32_I24 : VOP2Inst <0x00000009, "V_MUL_I32_I24",
1373 VOP_I32_I32_I32, AMDGPUmul_i24
1375 //defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>;
1376 defm V_MUL_U32_U24 : VOP2Inst <0x0000000b, "V_MUL_U32_U24",
1377 VOP_I32_I32_I32, AMDGPUmul_u24
1379 //defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>;
1382 defm V_MIN_LEGACY_F32 : VOP2Inst <0x0000000d, "V_MIN_LEGACY_F32",
1383 VOP_F32_F32_F32, AMDGPUfmin
1386 defm V_MAX_LEGACY_F32 : VOP2Inst <0x0000000e, "V_MAX_LEGACY_F32",
1387 VOP_F32_F32_F32, AMDGPUfmax
1390 defm V_MIN_F32 : VOP2Inst <0x0000000f, "V_MIN_F32", VOP_F32_F32_F32>;
1391 defm V_MAX_F32 : VOP2Inst <0x00000010, "V_MAX_F32", VOP_F32_F32_F32>;
1392 defm V_MIN_I32 : VOP2Inst <0x00000011, "V_MIN_I32", VOP_I32_I32_I32, AMDGPUsmin>;
1393 defm V_MAX_I32 : VOP2Inst <0x00000012, "V_MAX_I32", VOP_I32_I32_I32, AMDGPUsmax>;
1394 defm V_MIN_U32 : VOP2Inst <0x00000013, "V_MIN_U32", VOP_I32_I32_I32, AMDGPUumin>;
1395 defm V_MAX_U32 : VOP2Inst <0x00000014, "V_MAX_U32", VOP_I32_I32_I32, AMDGPUumax>;
1397 defm V_LSHR_B32 : VOP2Inst <0x00000015, "V_LSHR_B32", VOP_I32_I32_I32, srl>;
1399 defm V_LSHRREV_B32 : VOP2Inst <
1400 0x00000016, "V_LSHRREV_B32", VOP_I32_I32_I32, null_frag, "V_LSHR_B32"
1403 defm V_ASHR_I32 : VOP2Inst <0x00000017, "V_ASHR_I32",
1404 VOP_I32_I32_I32, sra
1406 defm V_ASHRREV_I32 : VOP2Inst <
1407 0x00000018, "V_ASHRREV_I32", VOP_I32_I32_I32, null_frag, "V_ASHR_I32"
1410 let hasPostISelHook = 1 in {
1412 defm V_LSHL_B32 : VOP2Inst <0x00000019, "V_LSHL_B32", VOP_I32_I32_I32, shl>;
1415 defm V_LSHLREV_B32 : VOP2Inst <
1416 0x0000001a, "V_LSHLREV_B32", VOP_I32_I32_I32, null_frag, "V_LSHL_B32"
1419 defm V_AND_B32 : VOP2Inst <0x0000001b, "V_AND_B32",
1420 VOP_I32_I32_I32, and>;
1421 defm V_OR_B32 : VOP2Inst <0x0000001c, "V_OR_B32",
1424 defm V_XOR_B32 : VOP2Inst <0x0000001d, "V_XOR_B32",
1425 VOP_I32_I32_I32, xor
1428 } // End isCommutable = 1
1430 defm V_BFM_B32 : VOP2Inst <0x0000001e, "V_BFM_B32",
1431 VOP_I32_I32_I32, AMDGPUbfm>;
1432 defm V_MAC_F32 : VOP2Inst <0x0000001f, "V_MAC_F32", VOP_F32_F32_F32>;
1433 defm V_MADMK_F32 : VOP2Inst <0x00000020, "V_MADMK_F32", VOP_F32_F32_F32>;
1434 defm V_MADAK_F32 : VOP2Inst <0x00000021, "V_MADAK_F32", VOP_F32_F32_F32>;
1435 defm V_BCNT_U32_B32 : VOP2Inst <0x00000022, "V_BCNT_U32_B32", VOP_I32_I32_I32>;
1436 defm V_MBCNT_LO_U32_B32 : VOP2Inst <0x00000023, "V_MBCNT_LO_U32_B32",
1439 defm V_MBCNT_HI_U32_B32 : VOP2Inst <0x00000024, "V_MBCNT_HI_U32_B32",
1443 let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC
1444 // No patterns so that the scalar instructions are always selected.
1445 // The scalar versions will be replaced with vector when needed later.
1446 defm V_ADD_I32 : VOP2bInst <0x00000025, "V_ADD_I32",
1447 VOP_I32_I32_I32, add
1449 defm V_SUB_I32 : VOP2bInst <0x00000026, "V_SUB_I32",
1450 VOP_I32_I32_I32, sub
1452 defm V_SUBREV_I32 : VOP2bInst <0x00000027, "V_SUBREV_I32",
1453 VOP_I32_I32_I32, null_frag, "V_SUB_I32"
1456 let Uses = [VCC] in { // Carry-in comes from VCC
1457 defm V_ADDC_U32 : VOP2bInst <0x00000028, "V_ADDC_U32",
1458 VOP_I32_I32_I32_VCC, adde
1460 defm V_SUBB_U32 : VOP2bInst <0x00000029, "V_SUBB_U32",
1461 VOP_I32_I32_I32_VCC, sube
1463 defm V_SUBBREV_U32 : VOP2bInst <0x0000002a, "V_SUBBREV_U32",
1464 VOP_I32_I32_I32_VCC, null_frag, "V_SUBB_U32"
1467 } // End Uses = [VCC]
1468 } // End isCommutable = 1, Defs = [VCC]
1470 defm V_LDEXP_F32 : VOP2Inst <0x0000002b, "V_LDEXP_F32",
1471 VOP_F32_F32_I32, AMDGPUldexp
1473 ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>;
1474 ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>;
1475 ////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>;
1476 defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <0x0000002f, "V_CVT_PKRTZ_F16_F32",
1477 VOP_I32_F32_F32, int_SI_packf16
1479 ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>;
1480 ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>;
1482 //===----------------------------------------------------------------------===//
1483 // VOP3 Instructions
1484 //===----------------------------------------------------------------------===//
1486 defm V_MAD_LEGACY_F32 : VOP3Inst <0x00000140, "V_MAD_LEGACY_F32",
1489 defm V_MAD_F32 : VOP3Inst <0x00000141, "V_MAD_F32",
1490 VOP_F32_F32_F32_F32, fmad
1492 defm V_MAD_I32_I24 : VOP3Inst <0x00000142, "V_MAD_I32_I24",
1493 VOP_I32_I32_I32_I32, AMDGPUmad_i24
1495 defm V_MAD_U32_U24 : VOP3Inst <0x00000143, "V_MAD_U32_U24",
1496 VOP_I32_I32_I32_I32, AMDGPUmad_u24
1499 defm V_CUBEID_F32 : VOP3Inst <0x00000144, "V_CUBEID_F32",
1502 defm V_CUBESC_F32 : VOP3Inst <0x00000145, "V_CUBESC_F32",
1505 defm V_CUBETC_F32 : VOP3Inst <0x00000146, "V_CUBETC_F32",
1508 defm V_CUBEMA_F32 : VOP3Inst <0x00000147, "V_CUBEMA_F32",
1512 let neverHasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
1513 defm V_BFE_U32 : VOP3Inst <0x00000148, "V_BFE_U32",
1514 VOP_I32_I32_I32_I32, AMDGPUbfe_u32
1516 defm V_BFE_I32 : VOP3Inst <0x00000149, "V_BFE_I32",
1517 VOP_I32_I32_I32_I32, AMDGPUbfe_i32
1521 defm V_BFI_B32 : VOP3Inst <0x0000014a, "V_BFI_B32",
1522 VOP_I32_I32_I32_I32, AMDGPUbfi
1524 defm V_FMA_F32 : VOP3Inst <0x0000014b, "V_FMA_F32",
1525 VOP_F32_F32_F32_F32, fma
1527 defm V_FMA_F64 : VOP3Inst <0x0000014c, "V_FMA_F64",
1528 VOP_F64_F64_F64_F64, fma
1530 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>;
1531 defm V_ALIGNBIT_B32 : VOP3Inst <0x0000014e, "V_ALIGNBIT_B32",
1534 defm V_ALIGNBYTE_B32 : VOP3Inst <0x0000014f, "V_ALIGNBYTE_B32",
1537 defm V_MULLIT_F32 : VOP3Inst <0x00000150, "V_MULLIT_F32",
1538 VOP_F32_F32_F32_F32>;
1539 ////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>;
1540 ////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>;
1541 ////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>;
1542 ////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>;
1543 ////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>;
1544 ////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>;
1545 ////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>;
1546 ////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>;
1547 ////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>;
1548 //def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>;
1549 //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>;
1550 //def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>;
1551 defm V_SAD_U32 : VOP3Inst <0x0000015d, "V_SAD_U32",
1554 ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>;
1555 defm V_DIV_FIXUP_F32 : VOP3Inst <
1556 0x0000015f, "V_DIV_FIXUP_F32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup
1558 defm V_DIV_FIXUP_F64 : VOP3Inst <
1559 0x00000160, "V_DIV_FIXUP_F64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup
1562 defm V_LSHL_B64 : VOP3Inst <0x00000161, "V_LSHL_B64",
1563 VOP_I64_I64_I32, shl
1565 defm V_LSHR_B64 : VOP3Inst <0x00000162, "V_LSHR_B64",
1566 VOP_I64_I64_I32, srl
1568 defm V_ASHR_I64 : VOP3Inst <0x00000163, "V_ASHR_I64",
1569 VOP_I64_I64_I32, sra
1572 let isCommutable = 1 in {
1574 defm V_ADD_F64 : VOP3Inst <0x00000164, "V_ADD_F64",
1575 VOP_F64_F64_F64, fadd
1577 defm V_MUL_F64 : VOP3Inst <0x00000165, "V_MUL_F64",
1578 VOP_F64_F64_F64, fmul
1580 defm V_MIN_F64 : VOP3Inst <0x00000166, "V_MIN_F64",
1583 defm V_MAX_F64 : VOP3Inst <0x00000167, "V_MAX_F64",
1587 } // isCommutable = 1
1589 defm V_LDEXP_F64 : VOP3Inst <0x00000168, "V_LDEXP_F64",
1590 VOP_F64_F64_I32, AMDGPUldexp
1593 let isCommutable = 1 in {
1595 defm V_MUL_LO_U32 : VOP3Inst <0x00000169, "V_MUL_LO_U32",
1598 defm V_MUL_HI_U32 : VOP3Inst <0x0000016a, "V_MUL_HI_U32",
1601 defm V_MUL_LO_I32 : VOP3Inst <0x0000016b, "V_MUL_LO_I32",
1604 defm V_MUL_HI_I32 : VOP3Inst <0x0000016c, "V_MUL_HI_I32",
1608 } // isCommutable = 1
1610 defm V_DIV_SCALE_F32 : VOP3b_32 <0x0000016d, "V_DIV_SCALE_F32", []>;
1612 // Double precision division pre-scale.
1613 defm V_DIV_SCALE_F64 : VOP3b_64 <0x0000016e, "V_DIV_SCALE_F64", []>;
1615 defm V_DIV_FMAS_F32 : VOP3Inst <0x0000016f, "V_DIV_FMAS_F32",
1616 VOP_F32_F32_F32_F32, AMDGPUdiv_fmas
1618 defm V_DIV_FMAS_F64 : VOP3Inst <0x00000170, "V_DIV_FMAS_F64",
1619 VOP_F64_F64_F64_F64, AMDGPUdiv_fmas
1621 //def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>;
1622 //def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>;
1623 //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>;
1624 defm V_TRIG_PREOP_F64 : VOP3Inst <
1625 0x00000174, "V_TRIG_PREOP_F64", VOP_F64_F64_I32, AMDGPUtrig_preop
1628 //===----------------------------------------------------------------------===//
1629 // Pseudo Instructions
1630 //===----------------------------------------------------------------------===//
1632 let isCodeGenOnly = 1, isPseudo = 1 in {
1634 def V_MOV_I1 : InstSI <
1637 "", [(set i1:$dst, (imm:$src))]
1640 def V_AND_I1 : InstSI <
1641 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1642 [(set i1:$dst, (and i1:$src0, i1:$src1))]
1645 def V_OR_I1 : InstSI <
1646 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1647 [(set i1:$dst, (or i1:$src0, i1:$src1))]
1650 def V_XOR_I1 : InstSI <
1651 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1652 [(set i1:$dst, (xor i1:$src0, i1:$src1))]
1655 // SI pseudo instructions. These are used by the CFG structurizer pass
1656 // and should be lowered to ISA instructions prior to codegen.
1658 let mayLoad = 1, mayStore = 1, hasSideEffects = 1,
1659 Uses = [EXEC], Defs = [EXEC] in {
1661 let isBranch = 1, isTerminator = 1 in {
1664 (outs SReg_64:$dst),
1665 (ins SReg_64:$vcc, brtarget:$target),
1667 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))]
1670 def SI_ELSE : InstSI <
1671 (outs SReg_64:$dst),
1672 (ins SReg_64:$src, brtarget:$target),
1674 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]
1676 let Constraints = "$src = $dst";
1679 def SI_LOOP : InstSI <
1681 (ins SReg_64:$saved, brtarget:$target),
1682 "SI_LOOP $saved, $target",
1683 [(int_SI_loop i64:$saved, bb:$target)]
1686 } // end isBranch = 1, isTerminator = 1
1688 def SI_BREAK : InstSI <
1689 (outs SReg_64:$dst),
1691 "SI_ELSE $dst, $src",
1692 [(set i64:$dst, (int_SI_break i64:$src))]
1695 def SI_IF_BREAK : InstSI <
1696 (outs SReg_64:$dst),
1697 (ins SReg_64:$vcc, SReg_64:$src),
1698 "SI_IF_BREAK $dst, $vcc, $src",
1699 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))]
1702 def SI_ELSE_BREAK : InstSI <
1703 (outs SReg_64:$dst),
1704 (ins SReg_64:$src0, SReg_64:$src1),
1705 "SI_ELSE_BREAK $dst, $src0, $src1",
1706 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))]
1709 def SI_END_CF : InstSI <
1711 (ins SReg_64:$saved),
1713 [(int_SI_end_cf i64:$saved)]
1716 def SI_KILL : InstSI <
1720 [(int_AMDGPU_kill f32:$src)]
1723 } // end mayLoad = 1, mayStore = 1, hasSideEffects = 1
1724 // Uses = [EXEC], Defs = [EXEC]
1726 let Uses = [EXEC], Defs = [EXEC,VCC,M0] in {
1728 //defm SI_ : RegisterLoadStore <VReg_32, FRAMEri, ADDRIndirect>;
1730 let UseNamedOperandTable = 1 in {
1732 def SI_RegisterLoad : InstSI <
1733 (outs VReg_32:$dst, SReg_64:$temp),
1734 (ins FRAMEri32:$addr, i32imm:$chan),
1737 let isRegisterLoad = 1;
1741 class SIRegStore<dag outs> : InstSI <
1743 (ins VReg_32:$val, FRAMEri32:$addr, i32imm:$chan),
1746 let isRegisterStore = 1;
1750 let usesCustomInserter = 1 in {
1751 def SI_RegisterStorePseudo : SIRegStore<(outs)>;
1752 } // End usesCustomInserter = 1
1753 def SI_RegisterStore : SIRegStore<(outs SReg_64:$temp)>;
1756 } // End UseNamedOperandTable = 1
1758 def SI_INDIRECT_SRC : InstSI <
1759 (outs VReg_32:$dst, SReg_64:$temp),
1760 (ins unknown:$src, VSrc_32:$idx, i32imm:$off),
1761 "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off",
1765 class SI_INDIRECT_DST<RegisterClass rc> : InstSI <
1766 (outs rc:$dst, SReg_64:$temp),
1767 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val),
1768 "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val",
1771 let Constraints = "$src = $dst";
1774 def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VReg_32>;
1775 def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
1776 def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
1777 def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
1778 def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
1780 } // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0]
1782 let usesCustomInserter = 1 in {
1784 // This pseudo instruction takes a pointer as input and outputs a resource
1785 // constant that can be used with the ADDR64 MUBUF instructions.
1786 def SI_ADDR64_RSRC : InstSI <
1787 (outs SReg_128:$srsrc),
1792 def SI_BUFFER_RSRC : InstSI <
1793 (outs SReg_128:$srsrc),
1794 (ins SReg_32:$ptr_lo, SReg_32:$ptr_hi, SSrc_32:$data_lo, SSrc_32:$data_hi),
1798 def V_SUB_F64 : InstSI <
1799 (outs VReg_64:$dst),
1800 (ins VReg_64:$src0, VReg_64:$src1),
1801 "V_SUB_F64 $dst, $src0, $src1",
1802 [(set f64:$dst, (fsub f64:$src0, f64:$src1))]
1805 } // end usesCustomInserter
1807 multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
1809 def _SAVE : InstSI <
1811 (ins sgpr_class:$src, i32imm:$frame_idx),
1815 def _RESTORE : InstSI <
1816 (outs sgpr_class:$dst),
1817 (ins i32imm:$frame_idx),
1823 defm SI_SPILL_S32 : SI_SPILL_SGPR <SReg_32>;
1824 defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>;
1825 defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>;
1826 defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>;
1827 defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;
1829 multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> {
1830 def _SAVE : InstSI <
1832 (ins vgpr_class:$src, i32imm:$frame_idx),
1836 def _RESTORE : InstSI <
1837 (outs vgpr_class:$dst),
1838 (ins i32imm:$frame_idx),
1843 defm SI_SPILL_V32 : SI_SPILL_VGPR <VReg_32>;
1844 defm SI_SPILL_V64 : SI_SPILL_VGPR <VReg_64>;
1845 defm SI_SPILL_V96 : SI_SPILL_VGPR <VReg_96>;
1846 defm SI_SPILL_V128 : SI_SPILL_VGPR <VReg_128>;
1847 defm SI_SPILL_V256 : SI_SPILL_VGPR <VReg_256>;
1848 defm SI_SPILL_V512 : SI_SPILL_VGPR <VReg_512>;
1850 let Defs = [SCC] in {
1852 def SI_CONSTDATA_PTR : InstSI <
1853 (outs SReg_64:$dst),
1855 "", [(set SReg_64:$dst, (i64 SIconstdata_ptr))]
1858 } // End Defs = [SCC]
1860 } // end IsCodeGenOnly, isPseudo
1862 } // end SubtargetPredicate = SI
1864 let Predicates = [isSI] in {
1867 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2),
1868 (V_CNDMASK_B32_e64 $src2, $src1,
1869 (V_CMP_GT_F32_e64 SRCMODS.NONE, 0, SRCMODS.NONE, $src0,
1870 DSTCLAMP.NONE, DSTOMOD.NONE))
1875 (SI_KILL 0xbf800000)
1878 /* int_SI_vs_load_input */
1880 (SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr),
1881 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0)
1886 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
1887 f32:$src0, f32:$src1, f32:$src2, f32:$src3),
1888 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
1889 $src0, $src1, $src2, $src3)
1892 //===----------------------------------------------------------------------===//
1894 //===----------------------------------------------------------------------===//
1896 multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
1898 // 1. Offset as 8bit DWORD immediate
1900 (constant_load (add i64:$sbase, (i64 IMM8bitDWORD:$offset))),
1901 (vt (Instr_IMM $sbase, (as_dword_i32imm $offset)))
1904 // 2. Offset loaded in an 32bit SGPR
1906 (constant_load (add i64:$sbase, (i64 IMM32bit:$offset))),
1907 (vt (Instr_SGPR $sbase, (S_MOV_B32 (i32 (as_i32imm $offset)))))
1910 // 3. No offset at all
1912 (constant_load i64:$sbase),
1913 (vt (Instr_IMM $sbase, 0))
1917 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>;
1918 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
1919 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>;
1920 defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>;
1921 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
1922 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>;
1923 defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
1925 // 1. Offset as 8bit DWORD immediate
1927 (SIload_constant v4i32:$sbase, IMM8bitDWORD:$offset),
1928 (S_BUFFER_LOAD_DWORD_IMM $sbase, (as_dword_i32imm $offset))
1931 // 2. Offset loaded in an 32bit SGPR
1933 (SIload_constant v4i32:$sbase, imm:$offset),
1934 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset))
1937 } // Predicates = [isSI] in {
1939 //===----------------------------------------------------------------------===//
1941 //===----------------------------------------------------------------------===//
1943 let Predicates = [isSI, isCFDepth0] in {
1946 (i64 (ctpop i64:$src)),
1947 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1948 (S_BCNT1_I32_B64 $src), sub0),
1949 (S_MOV_B32 0), sub1)
1952 //===----------------------------------------------------------------------===//
1954 //===----------------------------------------------------------------------===//
1956 // V_ADD_I32_e32/S_ADD_U32 produces carry in VCC/SCC. For the vector
1957 // case, the sgpr-copies pass will fix this to use the vector version.
1959 (i32 (addc i32:$src0, i32:$src1)),
1960 (S_ADD_U32 $src0, $src1)
1963 } // Predicates = [isSI, isCFDepth0]
1965 let Predicates = [isSI] in {
1967 //===----------------------------------------------------------------------===//
1969 //===----------------------------------------------------------------------===//
1972 (int_AMDGPU_barrier_global),
1976 //===----------------------------------------------------------------------===//
1978 //===----------------------------------------------------------------------===//
1980 let Predicates = [UnsafeFPMath] in {
1981 def : RcpPat<V_RCP_F64_e32, f64>;
1982 defm : RsqPat<V_RSQ_F64_e32, f64>;
1983 defm : RsqPat<V_RSQ_F32_e32, f32>;
1986 //===----------------------------------------------------------------------===//
1988 //===----------------------------------------------------------------------===//
1990 class BinOp64Pat <SDNode node, Instruction inst> : Pat <
1991 (node i64:$src0, i64:$src1),
1992 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1993 (inst (EXTRACT_SUBREG i64:$src0, sub0),
1994 (EXTRACT_SUBREG i64:$src1, sub0)), sub0),
1995 (inst (EXTRACT_SUBREG i64:$src0, sub1),
1996 (EXTRACT_SUBREG i64:$src1, sub1)), sub1)
1999 def : BinOp64Pat <and, V_AND_B32_e64>;
2000 def : BinOp64Pat <or, V_OR_B32_e64>;
2001 def : BinOp64Pat <xor, V_XOR_B32_e64>;
2003 class SextInReg <ValueType vt, int ShiftAmt> : Pat <
2004 (sext_inreg i32:$src0, vt),
2005 (V_ASHRREV_I32_e32 ShiftAmt, (V_LSHLREV_B32_e32 ShiftAmt, $src0))
2008 def : SextInReg <i8, 24>;
2009 def : SextInReg <i16, 16>;
2012 (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)),
2013 (V_BCNT_U32_B32_e64 $popcnt, $val)
2017 (i32 (ctpop i32:$popcnt)),
2018 (V_BCNT_U32_B32_e64 $popcnt, 0)
2022 (i64 (ctpop i64:$src)),
2024 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2025 (V_BCNT_U32_B32_e32 (EXTRACT_SUBREG $src, sub1),
2026 (V_BCNT_U32_B32_e64 (EXTRACT_SUBREG $src, sub0), 0)),
2028 (V_MOV_B32_e32 0), sub1)
2032 (addc i32:$src0, i32:$src1),
2033 (V_ADD_I32_e64 $src0, $src1)
2036 /********** ======================= **********/
2037 /********** Image sampling patterns **********/
2038 /********** ======================= **********/
2041 class SampleRawPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
2042 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i32:$unorm,
2043 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
2044 (opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da),
2045 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc),
2046 $addr, $rsrc, $sampler)
2049 multiclass SampleRawPatterns<SDPatternOperator name, string opcode> {
2050 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
2051 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
2052 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
2053 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V8), v8i32>;
2054 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V16), v16i32>;
2058 class ImagePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
2059 (name vt:$addr, v8i32:$rsrc, i32:$dmask, i32:$unorm,
2060 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
2061 (opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da),
2062 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc),
2066 multiclass ImagePatterns<SDPatternOperator name, string opcode> {
2067 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
2068 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
2069 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
2073 defm : SampleRawPatterns<int_SI_image_sample, "IMAGE_SAMPLE">;
2074 defm : SampleRawPatterns<int_SI_image_sample_cl, "IMAGE_SAMPLE_CL">;
2075 defm : SampleRawPatterns<int_SI_image_sample_d, "IMAGE_SAMPLE_D">;
2076 defm : SampleRawPatterns<int_SI_image_sample_d_cl, "IMAGE_SAMPLE_D_CL">;
2077 defm : SampleRawPatterns<int_SI_image_sample_l, "IMAGE_SAMPLE_L">;
2078 defm : SampleRawPatterns<int_SI_image_sample_b, "IMAGE_SAMPLE_B">;
2079 defm : SampleRawPatterns<int_SI_image_sample_b_cl, "IMAGE_SAMPLE_B_CL">;
2080 defm : SampleRawPatterns<int_SI_image_sample_lz, "IMAGE_SAMPLE_LZ">;
2081 defm : SampleRawPatterns<int_SI_image_sample_cd, "IMAGE_SAMPLE_CD">;
2082 defm : SampleRawPatterns<int_SI_image_sample_cd_cl, "IMAGE_SAMPLE_CD_CL">;
2084 // Sample with comparison
2085 defm : SampleRawPatterns<int_SI_image_sample_c, "IMAGE_SAMPLE_C">;
2086 defm : SampleRawPatterns<int_SI_image_sample_c_cl, "IMAGE_SAMPLE_C_CL">;
2087 defm : SampleRawPatterns<int_SI_image_sample_c_d, "IMAGE_SAMPLE_C_D">;
2088 defm : SampleRawPatterns<int_SI_image_sample_c_d_cl, "IMAGE_SAMPLE_C_D_CL">;
2089 defm : SampleRawPatterns<int_SI_image_sample_c_l, "IMAGE_SAMPLE_C_L">;
2090 defm : SampleRawPatterns<int_SI_image_sample_c_b, "IMAGE_SAMPLE_C_B">;
2091 defm : SampleRawPatterns<int_SI_image_sample_c_b_cl, "IMAGE_SAMPLE_C_B_CL">;
2092 defm : SampleRawPatterns<int_SI_image_sample_c_lz, "IMAGE_SAMPLE_C_LZ">;
2093 defm : SampleRawPatterns<int_SI_image_sample_c_cd, "IMAGE_SAMPLE_C_CD">;
2094 defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl, "IMAGE_SAMPLE_C_CD_CL">;
2096 // Sample with offsets
2097 defm : SampleRawPatterns<int_SI_image_sample_o, "IMAGE_SAMPLE_O">;
2098 defm : SampleRawPatterns<int_SI_image_sample_cl_o, "IMAGE_SAMPLE_CL_O">;
2099 defm : SampleRawPatterns<int_SI_image_sample_d_o, "IMAGE_SAMPLE_D_O">;
2100 defm : SampleRawPatterns<int_SI_image_sample_d_cl_o, "IMAGE_SAMPLE_D_CL_O">;
2101 defm : SampleRawPatterns<int_SI_image_sample_l_o, "IMAGE_SAMPLE_L_O">;
2102 defm : SampleRawPatterns<int_SI_image_sample_b_o, "IMAGE_SAMPLE_B_O">;
2103 defm : SampleRawPatterns<int_SI_image_sample_b_cl_o, "IMAGE_SAMPLE_B_CL_O">;
2104 defm : SampleRawPatterns<int_SI_image_sample_lz_o, "IMAGE_SAMPLE_LZ_O">;
2105 defm : SampleRawPatterns<int_SI_image_sample_cd_o, "IMAGE_SAMPLE_CD_O">;
2106 defm : SampleRawPatterns<int_SI_image_sample_cd_cl_o, "IMAGE_SAMPLE_CD_CL_O">;
2108 // Sample with comparison and offsets
2109 defm : SampleRawPatterns<int_SI_image_sample_c_o, "IMAGE_SAMPLE_C_O">;
2110 defm : SampleRawPatterns<int_SI_image_sample_c_cl_o, "IMAGE_SAMPLE_C_CL_O">;
2111 defm : SampleRawPatterns<int_SI_image_sample_c_d_o, "IMAGE_SAMPLE_C_D_O">;
2112 defm : SampleRawPatterns<int_SI_image_sample_c_d_cl_o, "IMAGE_SAMPLE_C_D_CL_O">;
2113 defm : SampleRawPatterns<int_SI_image_sample_c_l_o, "IMAGE_SAMPLE_C_L_O">;
2114 defm : SampleRawPatterns<int_SI_image_sample_c_b_o, "IMAGE_SAMPLE_C_B_O">;
2115 defm : SampleRawPatterns<int_SI_image_sample_c_b_cl_o, "IMAGE_SAMPLE_C_B_CL_O">;
2116 defm : SampleRawPatterns<int_SI_image_sample_c_lz_o, "IMAGE_SAMPLE_C_LZ_O">;
2117 defm : SampleRawPatterns<int_SI_image_sample_c_cd_o, "IMAGE_SAMPLE_C_CD_O">;
2118 defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl_o, "IMAGE_SAMPLE_C_CD_CL_O">;
2121 // Only the variants which make sense are defined.
2122 def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V2, v2i32>;
2123 def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V4, v4i32>;
2124 def : SampleRawPattern<int_SI_gather4_cl, IMAGE_GATHER4_CL_V4_V4, v4i32>;
2125 def : SampleRawPattern<int_SI_gather4_l, IMAGE_GATHER4_L_V4_V4, v4i32>;
2126 def : SampleRawPattern<int_SI_gather4_b, IMAGE_GATHER4_B_V4_V4, v4i32>;
2127 def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V4, v4i32>;
2128 def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V8, v8i32>;
2129 def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V2, v2i32>;
2130 def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V4, v4i32>;
2132 def : SampleRawPattern<int_SI_gather4_c, IMAGE_GATHER4_C_V4_V4, v4i32>;
2133 def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V4, v4i32>;
2134 def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V8, v8i32>;
2135 def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V4, v4i32>;
2136 def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V8, v8i32>;
2137 def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V4, v4i32>;
2138 def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V8, v8i32>;
2139 def : SampleRawPattern<int_SI_gather4_c_b_cl, IMAGE_GATHER4_C_B_CL_V4_V8, v8i32>;
2140 def : SampleRawPattern<int_SI_gather4_c_lz, IMAGE_GATHER4_C_LZ_V4_V4, v4i32>;
2142 def : SampleRawPattern<int_SI_gather4_o, IMAGE_GATHER4_O_V4_V4, v4i32>;
2143 def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V4, v4i32>;
2144 def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V8, v8i32>;
2145 def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V4, v4i32>;
2146 def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V8, v8i32>;
2147 def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V4, v4i32>;
2148 def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V8, v8i32>;
2149 def : SampleRawPattern<int_SI_gather4_b_cl_o, IMAGE_GATHER4_B_CL_O_V4_V8, v8i32>;
2150 def : SampleRawPattern<int_SI_gather4_lz_o, IMAGE_GATHER4_LZ_O_V4_V4, v4i32>;
2152 def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V4, v4i32>;
2153 def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V8, v8i32>;
2154 def : SampleRawPattern<int_SI_gather4_c_cl_o, IMAGE_GATHER4_C_CL_O_V4_V8, v8i32>;
2155 def : SampleRawPattern<int_SI_gather4_c_l_o, IMAGE_GATHER4_C_L_O_V4_V8, v8i32>;
2156 def : SampleRawPattern<int_SI_gather4_c_b_o, IMAGE_GATHER4_C_B_O_V4_V8, v8i32>;
2157 def : SampleRawPattern<int_SI_gather4_c_b_cl_o, IMAGE_GATHER4_C_B_CL_O_V4_V8, v8i32>;
2158 def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V4, v4i32>;
2159 def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V8, v8i32>;
2161 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V1, i32>;
2162 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V2, v2i32>;
2163 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V4, v4i32>;
2165 def : ImagePattern<int_SI_getresinfo, IMAGE_GET_RESINFO_V4_V1, i32>;
2166 defm : ImagePatterns<int_SI_image_load, "IMAGE_LOAD">;
2167 defm : ImagePatterns<int_SI_image_load_mip, "IMAGE_LOAD_MIP">;
2169 /* SIsample for simple 1D texture lookup */
2171 (SIsample i32:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
2172 (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2175 class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
2176 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
2177 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2180 class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
2181 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_RECT),
2182 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2185 class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
2186 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_ARRAY),
2187 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2190 class SampleShadowPattern<SDNode name, MIMG opcode,
2191 ValueType vt> : Pat <
2192 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW),
2193 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2196 class SampleShadowArrayPattern<SDNode name, MIMG opcode,
2197 ValueType vt> : Pat <
2198 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
2199 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2202 /* SIsample* for texture lookups consuming more address parameters */
2203 multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l,
2204 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b,
2205 MIMG sample_d, MIMG sample_c_d, ValueType addr_type> {
2206 def : SamplePattern <SIsample, sample, addr_type>;
2207 def : SampleRectPattern <SIsample, sample, addr_type>;
2208 def : SampleArrayPattern <SIsample, sample, addr_type>;
2209 def : SampleShadowPattern <SIsample, sample_c, addr_type>;
2210 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>;
2212 def : SamplePattern <SIsamplel, sample_l, addr_type>;
2213 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>;
2214 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>;
2215 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>;
2217 def : SamplePattern <SIsampleb, sample_b, addr_type>;
2218 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>;
2219 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>;
2220 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>;
2222 def : SamplePattern <SIsampled, sample_d, addr_type>;
2223 def : SampleArrayPattern <SIsampled, sample_d, addr_type>;
2224 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>;
2225 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>;
2228 defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2,
2229 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2,
2230 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2,
2231 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2,
2233 defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4,
2234 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4,
2235 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4,
2236 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4,
2238 defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8,
2239 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8,
2240 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8,
2241 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8,
2243 defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16,
2244 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16,
2245 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16,
2246 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16,
2249 /* int_SI_imageload for texture fetches consuming varying address parameters */
2250 class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2251 (name addr_type:$addr, v32i8:$rsrc, imm),
2252 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
2255 class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2256 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY),
2257 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
2260 class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2261 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA),
2262 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
2265 class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2266 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA),
2267 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
2270 multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> {
2271 def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>;
2272 def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>;
2275 multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> {
2276 def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>;
2277 def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>;
2280 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V2, v2i32>;
2281 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V4, v4i32>;
2283 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V2, v2i32>;
2284 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V4, v4i32>;
2286 /* Image resource information */
2288 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm),
2289 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
2293 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY),
2294 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
2298 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA),
2299 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
2302 /********** ============================================ **********/
2303 /********** Extraction, Insertion, Building and Casting **********/
2304 /********** ============================================ **********/
2306 foreach Index = 0-2 in {
2307 def Extract_Element_v2i32_#Index : Extract_Element <
2308 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
2310 def Insert_Element_v2i32_#Index : Insert_Element <
2311 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
2314 def Extract_Element_v2f32_#Index : Extract_Element <
2315 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
2317 def Insert_Element_v2f32_#Index : Insert_Element <
2318 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
2322 foreach Index = 0-3 in {
2323 def Extract_Element_v4i32_#Index : Extract_Element <
2324 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
2326 def Insert_Element_v4i32_#Index : Insert_Element <
2327 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
2330 def Extract_Element_v4f32_#Index : Extract_Element <
2331 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
2333 def Insert_Element_v4f32_#Index : Insert_Element <
2334 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
2338 foreach Index = 0-7 in {
2339 def Extract_Element_v8i32_#Index : Extract_Element <
2340 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
2342 def Insert_Element_v8i32_#Index : Insert_Element <
2343 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
2346 def Extract_Element_v8f32_#Index : Extract_Element <
2347 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
2349 def Insert_Element_v8f32_#Index : Insert_Element <
2350 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
2354 foreach Index = 0-15 in {
2355 def Extract_Element_v16i32_#Index : Extract_Element <
2356 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
2358 def Insert_Element_v16i32_#Index : Insert_Element <
2359 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
2362 def Extract_Element_v16f32_#Index : Extract_Element <
2363 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
2365 def Insert_Element_v16f32_#Index : Insert_Element <
2366 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
2370 def : BitConvert <i32, f32, SReg_32>;
2371 def : BitConvert <i32, f32, VReg_32>;
2373 def : BitConvert <f32, i32, SReg_32>;
2374 def : BitConvert <f32, i32, VReg_32>;
2376 def : BitConvert <i64, f64, VReg_64>;
2378 def : BitConvert <f64, i64, VReg_64>;
2380 def : BitConvert <v2f32, v2i32, VReg_64>;
2381 def : BitConvert <v2i32, v2f32, VReg_64>;
2382 def : BitConvert <v2i32, i64, VReg_64>;
2383 def : BitConvert <i64, v2i32, VReg_64>;
2384 def : BitConvert <v2f32, i64, VReg_64>;
2385 def : BitConvert <i64, v2f32, VReg_64>;
2386 def : BitConvert <v2i32, f64, VReg_64>;
2387 def : BitConvert <f64, v2i32, VReg_64>;
2388 def : BitConvert <v4f32, v4i32, VReg_128>;
2389 def : BitConvert <v4i32, v4f32, VReg_128>;
2391 def : BitConvert <v8f32, v8i32, SReg_256>;
2392 def : BitConvert <v8i32, v8f32, SReg_256>;
2393 def : BitConvert <v8i32, v32i8, SReg_256>;
2394 def : BitConvert <v32i8, v8i32, SReg_256>;
2395 def : BitConvert <v8i32, v32i8, VReg_256>;
2396 def : BitConvert <v8i32, v8f32, VReg_256>;
2397 def : BitConvert <v8f32, v8i32, VReg_256>;
2398 def : BitConvert <v32i8, v8i32, VReg_256>;
2400 def : BitConvert <v16i32, v16f32, VReg_512>;
2401 def : BitConvert <v16f32, v16i32, VReg_512>;
2403 /********** =================== **********/
2404 /********** Src & Dst modifiers **********/
2405 /********** =================== **********/
2407 def FCLAMP_SI : AMDGPUShaderInst <
2408 (outs VReg_32:$dst),
2409 (ins VSrc_32:$src0),
2410 "FCLAMP_SI $dst, $src0",
2413 let usesCustomInserter = 1;
2417 (AMDGPUclamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)),
2418 (FCLAMP_SI f32:$src)
2421 /********** ================================ **********/
2422 /********** Floating point absolute/negative **********/
2423 /********** ================================ **********/
2425 // Prevent expanding both fneg and fabs.
2427 // FIXME: Should use S_OR_B32
2429 (fneg (fabs f32:$src)),
2430 (V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
2433 // FIXME: Should use S_OR_B32
2435 (fneg (fabs f64:$src)),
2437 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2438 (i32 (EXTRACT_SUBREG f64:$src, sub0)), sub0),
2439 (V_OR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
2440 (V_MOV_B32_e32 0x80000000)), sub1)) // Set sign bit.
2445 (V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff))
2450 (V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000))
2456 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2457 (i32 (EXTRACT_SUBREG f64:$src, sub0)), sub0),
2458 (V_AND_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
2459 (V_MOV_B32_e32 0x7fffffff)), sub1)) // Set sign bit.
2465 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2466 (i32 (EXTRACT_SUBREG f64:$src, sub0)), sub0),
2467 (V_XOR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
2468 (V_MOV_B32_e32 0x80000000)), sub1))
2471 /********** ================== **********/
2472 /********** Immediate Patterns **********/
2473 /********** ================== **********/
2476 (SGPRImm<(i32 imm)>:$imm),
2477 (S_MOV_B32 imm:$imm)
2481 (SGPRImm<(f32 fpimm)>:$imm),
2482 (S_MOV_B32 fpimm:$imm)
2487 (V_MOV_B32_e32 imm:$imm)
2492 (V_MOV_B32_e32 fpimm:$imm)
2496 (i64 InlineImm<i64>:$imm),
2497 (S_MOV_B64 InlineImm<i64>:$imm)
2500 /********** ===================== **********/
2501 /********** Interpolation Paterns **********/
2502 /********** ===================== **********/
2505 (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params),
2506 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, $params)
2510 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, v2i32:$ij),
2511 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0),
2512 imm:$attr_chan, imm:$attr, i32:$params),
2513 (EXTRACT_SUBREG $ij, sub1),
2514 imm:$attr_chan, imm:$attr, $params)
2517 /********** ================== **********/
2518 /********** Intrinsic Patterns **********/
2519 /********** ================== **********/
2521 /* llvm.AMDGPU.pow */
2522 def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>;
2525 (int_AMDGPU_div f32:$src0, f32:$src1),
2526 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1))
2530 (fdiv f64:$src0, f64:$src1),
2531 (V_MUL_F64 0 /* src0_modifiers */, $src0,
2532 0 /* src1_modifiers */, (V_RCP_F64_e32 $src1),
2533 0 /* clamp */, 0 /* omod */)
2537 (int_AMDGPU_cube v4f32:$src),
2538 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2539 (V_CUBETC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
2540 0 /* src1_modifiers */, (EXTRACT_SUBREG $src, sub1),
2541 0 /* src2_modifiers */, (EXTRACT_SUBREG $src, sub2),
2542 0 /* clamp */, 0 /* omod */),
2544 (V_CUBESC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
2545 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2546 0 /* src2_modifiers */,(EXTRACT_SUBREG $src, sub2),
2547 0 /* clamp */, 0 /* omod */),
2549 (V_CUBEMA_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0),
2550 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2551 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2),
2552 0 /* clamp */, 0 /* omod */),
2554 (V_CUBEID_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0),
2555 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2556 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2),
2557 0 /* clamp */, 0 /* omod */),
2562 (i32 (sext i1:$src0)),
2563 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
2566 class Ext32Pat <SDNode ext> : Pat <
2567 (i32 (ext i1:$src0)),
2568 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0)
2571 def : Ext32Pat <zext>;
2572 def : Ext32Pat <anyext>;
2574 // Offset in an 32Bit VGPR
2576 (SIload_constant v4i32:$sbase, i32:$voff),
2577 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0, 0)
2580 // The multiplication scales from [0,1] to the unsigned integer range
2582 (AMDGPUurecip i32:$src0),
2584 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1,
2585 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
2590 (V_MBCNT_HI_U32_B32_e32 0xffffffff,
2591 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0))
2594 //===----------------------------------------------------------------------===//
2596 //===----------------------------------------------------------------------===//
2598 def : IMad24Pat<V_MAD_I32_I24>;
2599 def : UMad24Pat<V_MAD_U32_U24>;
2602 (mul i32:$src0, i32:$src1),
2603 (V_MUL_LO_I32 $src0, $src1)
2607 (mulhu i32:$src0, i32:$src1),
2608 (V_MUL_HI_U32 $src0, $src1)
2612 (mulhs i32:$src0, i32:$src1),
2613 (V_MUL_HI_I32 $src0, $src1)
2616 def : Vop3ModPat<V_MAD_F32, VOP_F32_F32_F32_F32, AMDGPUmad>;
2619 defm : BFIPatterns <V_BFI_B32, S_MOV_B32>;
2620 def : ROTRPattern <V_ALIGNBIT_B32>;
2622 /********** ======================= **********/
2623 /********** Load/Store Patterns **********/
2624 /********** ======================= **********/
2626 class DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat <
2627 (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
2628 (inst (i1 0), $ptr, (as_i16imm $offset))
2631 def : DSReadPat <DS_READ_I8, i32, sextloadi8_local>;
2632 def : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>;
2633 def : DSReadPat <DS_READ_I16, i32, sextloadi16_local>;
2634 def : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>;
2635 def : DSReadPat <DS_READ_B32, i32, local_load>;
2637 let AddedComplexity = 100 in {
2639 def : DSReadPat <DS_READ_B64, v2i32, local_load_aligned8bytes>;
2641 } // End AddedComplexity = 100
2644 (v2i32 (local_load (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
2646 (DS_READ2_B32 (i1 0), $ptr, $offset0, $offset1)
2649 class DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat <
2650 (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
2651 (inst (i1 0), $ptr, $value, (as_i16imm $offset))
2654 def : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>;
2655 def : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>;
2656 def : DSWritePat <DS_WRITE_B32, i32, local_store>;
2658 let AddedComplexity = 100 in {
2660 def : DSWritePat <DS_WRITE_B64, v2i32, local_store_aligned8bytes>;
2661 } // End AddedComplexity = 100
2664 (local_store v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
2666 (DS_WRITE2_B32 (i1 0), $ptr, (EXTRACT_SUBREG $value, sub0),
2667 (EXTRACT_SUBREG $value, sub1), $offset0, $offset1)
2670 class DSAtomicRetPat<DS inst, ValueType vt, PatFrag frag> : Pat <
2671 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
2672 (inst (i1 0), $ptr, $value, (as_i16imm $offset))
2675 // Special case of DSAtomicRetPat for add / sub 1 -> inc / dec
2677 // We need to use something for the data0, so we set a register to
2678 // -1. For the non-rtn variants, the manual says it does
2679 // DS[A] = (DS[A] >= D0) ? 0 : DS[A] + 1, and setting D0 to uint_max
2680 // will always do the increment so I'm assuming it's the same.
2682 // We also load this -1 with s_mov_b32 / s_mov_b64 even though this
2683 // needs to be a VGPR. The SGPR copy pass will fix this, and it's
2684 // easier since there is no v_mov_b64.
2685 class DSAtomicIncRetPat<DS inst, ValueType vt,
2686 Instruction LoadImm, PatFrag frag> : Pat <
2687 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), (vt 1)),
2688 (inst (i1 0), $ptr, (LoadImm (vt -1)), (as_i16imm $offset))
2692 class DSAtomicCmpXChg <DS inst, ValueType vt, PatFrag frag> : Pat <
2693 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
2694 (inst (i1 0), $ptr, $cmp, $swap, (as_i16imm $offset))
2699 def : DSAtomicIncRetPat<DS_INC_RTN_U32, i32,
2700 S_MOV_B32, atomic_load_add_local>;
2701 def : DSAtomicIncRetPat<DS_DEC_RTN_U32, i32,
2702 S_MOV_B32, atomic_load_sub_local>;
2704 def : DSAtomicRetPat<DS_WRXCHG_RTN_B32, i32, atomic_swap_local>;
2705 def : DSAtomicRetPat<DS_ADD_RTN_U32, i32, atomic_load_add_local>;
2706 def : DSAtomicRetPat<DS_SUB_RTN_U32, i32, atomic_load_sub_local>;
2707 def : DSAtomicRetPat<DS_AND_RTN_B32, i32, atomic_load_and_local>;
2708 def : DSAtomicRetPat<DS_OR_RTN_B32, i32, atomic_load_or_local>;
2709 def : DSAtomicRetPat<DS_XOR_RTN_B32, i32, atomic_load_xor_local>;
2710 def : DSAtomicRetPat<DS_MIN_RTN_I32, i32, atomic_load_min_local>;
2711 def : DSAtomicRetPat<DS_MAX_RTN_I32, i32, atomic_load_max_local>;
2712 def : DSAtomicRetPat<DS_MIN_RTN_U32, i32, atomic_load_umin_local>;
2713 def : DSAtomicRetPat<DS_MAX_RTN_U32, i32, atomic_load_umax_local>;
2715 def : DSAtomicCmpXChg<DS_CMPST_RTN_B32, i32, atomic_cmp_swap_32_local>;
2718 def : DSAtomicIncRetPat<DS_INC_RTN_U64, i64,
2719 S_MOV_B64, atomic_load_add_local>;
2720 def : DSAtomicIncRetPat<DS_DEC_RTN_U64, i64,
2721 S_MOV_B64, atomic_load_sub_local>;
2723 def : DSAtomicRetPat<DS_WRXCHG_RTN_B64, i64, atomic_swap_local>;
2724 def : DSAtomicRetPat<DS_ADD_RTN_U64, i64, atomic_load_add_local>;
2725 def : DSAtomicRetPat<DS_SUB_RTN_U64, i64, atomic_load_sub_local>;
2726 def : DSAtomicRetPat<DS_AND_RTN_B64, i64, atomic_load_and_local>;
2727 def : DSAtomicRetPat<DS_OR_RTN_B64, i64, atomic_load_or_local>;
2728 def : DSAtomicRetPat<DS_XOR_RTN_B64, i64, atomic_load_xor_local>;
2729 def : DSAtomicRetPat<DS_MIN_RTN_I64, i64, atomic_load_min_local>;
2730 def : DSAtomicRetPat<DS_MAX_RTN_I64, i64, atomic_load_max_local>;
2731 def : DSAtomicRetPat<DS_MIN_RTN_U64, i64, atomic_load_umin_local>;
2732 def : DSAtomicRetPat<DS_MAX_RTN_U64, i64, atomic_load_umax_local>;
2734 def : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, atomic_cmp_swap_64_local>;
2737 //===----------------------------------------------------------------------===//
2739 //===----------------------------------------------------------------------===//
2741 multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
2742 PatFrag constant_ld> {
2744 (vt (constant_ld (add i64:$ptr, i64:$offset))),
2745 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0)
2750 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, sextloadi8_constant>;
2751 defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, az_extloadi8_constant>;
2752 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_constant>;
2753 defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, az_extloadi16_constant>;
2754 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32, constant_load>;
2755 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32, constant_load>;
2756 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32, constant_load>;
2758 class MUBUFScratchLoadPat <MUBUF Instr, ValueType vt, PatFrag ld> : Pat <
2759 (vt (ld (MUBUFScratch v4i32:$srsrc, i32:$vaddr,
2760 i32:$soffset, u16imm:$offset))),
2761 (Instr $srsrc, $vaddr, $soffset, $offset, 0, 0, 0)
2764 def : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, i32, sextloadi8_private>;
2765 def : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, i32, extloadi8_private>;
2766 def : MUBUFScratchLoadPat <BUFFER_LOAD_SSHORT_OFFEN, i32, sextloadi16_private>;
2767 def : MUBUFScratchLoadPat <BUFFER_LOAD_USHORT_OFFEN, i32, extloadi16_private>;
2768 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORD_OFFEN, i32, load_private>;
2769 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX2_OFFEN, v2i32, load_private>;
2770 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX4_OFFEN, v4i32, load_private>;
2772 // BUFFER_LOAD_DWORD*, addr64=0
2773 multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen,
2777 (vt (int_SI_buffer_load_dword v4i32:$rsrc, (i32 imm), i32:$soffset,
2778 imm:$offset, 0, 0, imm:$glc, imm:$slc,
2780 (offset $rsrc, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2781 (as_i1imm $slc), (as_i1imm $tfe))
2785 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2786 imm:$offset, 1, 0, imm:$glc, imm:$slc,
2788 (offen $rsrc, $vaddr, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc),
2793 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2794 imm:$offset, 0, 1, imm:$glc, imm:$slc,
2796 (idxen $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2797 (as_i1imm $slc), (as_i1imm $tfe))
2801 (vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset,
2802 imm, 1, 1, imm:$glc, imm:$slc,
2804 (bothen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
2809 defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN,
2810 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
2811 defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN,
2812 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>;
2813 defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN,
2814 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
2816 class MUBUFScratchStorePat <MUBUF Instr, ValueType vt, PatFrag st> : Pat <
2817 (st vt:$value, (MUBUFScratch v4i32:$srsrc, i32:$vaddr, i32:$soffset,
2819 (Instr $value, $srsrc, $vaddr, $soffset, $offset, 0, 0, 0)
2822 def : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, i32, truncstorei8_private>;
2823 def : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, i32, truncstorei16_private>;
2824 def : MUBUFScratchStorePat <BUFFER_STORE_DWORD_OFFEN, i32, store_private>;
2825 def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX2_OFFEN, v2i32, store_private>;
2826 def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, v4i32, store_private>;
2829 class MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> : Pat <
2830 (st vt:$value, (MUBUFScratch v4i32:$srsrc, i64:$vaddr, u16imm:$offset)),
2831 (Instr $value, $srsrc, $vaddr, $offset)
2834 def : MUBUFStore_Pattern <BUFFER_STORE_BYTE_ADDR64, i32, truncstorei8_private>;
2835 def : MUBUFStore_Pattern <BUFFER_STORE_SHORT_ADDR64, i32, truncstorei16_private>;
2836 def : MUBUFStore_Pattern <BUFFER_STORE_DWORD_ADDR64, i32, store_private>;
2837 def : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2_ADDR64, v2i32, store_private>;
2838 def : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4_ADDR64, v4i32, store_private>;
2842 //===----------------------------------------------------------------------===//
2844 //===----------------------------------------------------------------------===//
2846 // TBUFFER_STORE_FORMAT_*, addr64=0
2847 class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat<
2848 (SItbuffer_store v4i32:$rsrc, vt:$vdata, num_channels, i32:$vaddr,
2849 i32:$soffset, imm:$inst_offset, imm:$dfmt,
2850 imm:$nfmt, imm:$offen, imm:$idxen,
2851 imm:$glc, imm:$slc, imm:$tfe),
2853 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen),
2854 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc,
2855 (as_i1imm $slc), (as_i1imm $tfe), $soffset)
2858 def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>;
2859 def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>;
2860 def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>;
2861 def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>;
2863 let SubtargetPredicate = isCI in {
2865 // Sea island new arithmetic instructinos
2866 defm V_TRUNC_F64 : VOP1Inst <0x00000017, "V_TRUNC_F64",
2869 defm V_CEIL_F64 : VOP1Inst <0x00000018, "V_CEIL_F64",
2872 defm V_FLOOR_F64 : VOP1Inst <0x0000001A, "V_FLOOR_F64",
2875 defm V_RNDNE_F64 : VOP1Inst <0x00000019, "V_RNDNE_F64",
2879 defm V_QSAD_PK_U16_U8 : VOP3Inst <0x00000173, "V_QSAD_PK_U16_U8",
2882 defm V_MQSAD_U16_U8 : VOP3Inst <0x000000172, "V_MQSAD_U16_U8",
2885 defm V_MQSAD_U32_U8 : VOP3Inst <0x00000175, "V_MQSAD_U32_U8",
2888 defm V_MAD_U64_U32 : VOP3Inst <0x00000176, "V_MAD_U64_U32",
2892 // XXX - Does this set VCC?
2893 defm V_MAD_I64_I32 : VOP3Inst <0x00000177, "V_MAD_I64_I32",
2897 // Remaining instructions:
2899 // S_CBRANCH_CDBGUSER
2900 // S_CBRANCH_CDBGSYS
2901 // S_CBRANCH_CDBGSYS_OR_USER
2902 // S_CBRANCH_CDBGSYS_AND_USER
2907 // DS_GWS_SEMA_RELEASE_ALL
2909 // DS_CNDXCHG32_RTN_B64
2912 // DS_CONDXCHG32_RTN_B128
2915 // BUFFER_LOAD_DWORDX3
2916 // BUFFER_STORE_DWORDX3
2920 //===----------------------------------------------------------------------===//
2922 //===----------------------------------------------------------------------===//
2924 class FLATLoad_Pattern <FLAT Instr_ADDR64, ValueType vt,
2926 Pat <(vt (flat_ld i64:$ptr)),
2930 def : FLATLoad_Pattern <FLAT_LOAD_SBYTE, i32, sextloadi8_flat>;
2931 def : FLATLoad_Pattern <FLAT_LOAD_UBYTE, i32, az_extloadi8_flat>;
2932 def : FLATLoad_Pattern <FLAT_LOAD_SSHORT, i32, sextloadi16_flat>;
2933 def : FLATLoad_Pattern <FLAT_LOAD_USHORT, i32, az_extloadi16_flat>;
2934 def : FLATLoad_Pattern <FLAT_LOAD_DWORD, i32, flat_load>;
2935 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX2, i64, flat_load>;
2936 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX2, i64, az_extloadi32_flat>;
2937 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX2, v2i32, flat_load>;
2938 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX4, v4i32, flat_load>;
2940 class FLATStore_Pattern <FLAT Instr, ValueType vt, PatFrag st> :
2941 Pat <(st vt:$value, i64:$ptr),
2942 (Instr $value, $ptr)
2945 def : FLATStore_Pattern <FLAT_STORE_BYTE, i32, truncstorei8_flat>;
2946 def : FLATStore_Pattern <FLAT_STORE_SHORT, i32, truncstorei16_flat>;
2947 def : FLATStore_Pattern <FLAT_STORE_DWORD, i32, flat_store>;
2948 def : FLATStore_Pattern <FLAT_STORE_DWORDX2, i64, flat_store>;
2949 def : FLATStore_Pattern <FLAT_STORE_DWORDX2, v2i32, flat_store>;
2950 def : FLATStore_Pattern <FLAT_STORE_DWORDX4, v4i32, flat_store>;
2952 /********** ====================== **********/
2953 /********** Indirect adressing **********/
2954 /********** ====================== **********/
2956 multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, SI_INDIRECT_DST IndDst> {
2958 // 1. Extract with offset
2960 (vector_extract vt:$vec, (add i32:$idx, imm:$off)),
2961 (eltvt (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off))
2964 // 2. Extract without offset
2966 (vector_extract vt:$vec, i32:$idx),
2967 (eltvt (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0))
2970 // 3. Insert with offset
2972 (vector_insert vt:$vec, eltvt:$val, (add i32:$idx, imm:$off)),
2973 (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val)
2976 // 4. Insert without offset
2978 (vector_insert vt:$vec, eltvt:$val, i32:$idx),
2979 (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val)
2983 defm : SI_INDIRECT_Pattern <v2f32, f32, SI_INDIRECT_DST_V2>;
2984 defm : SI_INDIRECT_Pattern <v4f32, f32, SI_INDIRECT_DST_V4>;
2985 defm : SI_INDIRECT_Pattern <v8f32, f32, SI_INDIRECT_DST_V8>;
2986 defm : SI_INDIRECT_Pattern <v16f32, f32, SI_INDIRECT_DST_V16>;
2988 defm : SI_INDIRECT_Pattern <v2i32, i32, SI_INDIRECT_DST_V2>;
2989 defm : SI_INDIRECT_Pattern <v4i32, i32, SI_INDIRECT_DST_V4>;
2990 defm : SI_INDIRECT_Pattern <v8i32, i32, SI_INDIRECT_DST_V8>;
2991 defm : SI_INDIRECT_Pattern <v16i32, i32, SI_INDIRECT_DST_V16>;
2993 //===----------------------------------------------------------------------===//
2994 // Conversion Patterns
2995 //===----------------------------------------------------------------------===//
2997 def : Pat<(i32 (sext_inreg i32:$src, i1)),
2998 (S_BFE_I32 i32:$src, 65536)>; // 0 | 1 << 16
3000 // TODO: Match 64-bit BFE. SI has a 64-bit BFE, but it's scalar only so it
3001 // might not be worth the effort, and will need to expand to shifts when
3002 // fixing SGPR copies.
3004 // Handle sext_inreg in i64
3006 (i64 (sext_inreg i64:$src, i1)),
3007 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
3008 (S_BFE_I32 (EXTRACT_SUBREG i64:$src, sub0), 65536), sub0), // 0 | 1 << 16
3009 (S_MOV_B32 -1), sub1)
3013 (i64 (sext_inreg i64:$src, i8)),
3014 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
3015 (S_SEXT_I32_I8 (EXTRACT_SUBREG i64:$src, sub0)), sub0),
3016 (S_MOV_B32 -1), sub1)
3020 (i64 (sext_inreg i64:$src, i16)),
3021 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
3022 (S_SEXT_I32_I16 (EXTRACT_SUBREG i64:$src, sub0)), sub0),
3023 (S_MOV_B32 -1), sub1)
3026 class ZExt_i64_i32_Pat <SDNode ext> : Pat <
3027 (i64 (ext i32:$src)),
3028 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $src, sub0),
3029 (S_MOV_B32 0), sub1)
3032 class ZExt_i64_i1_Pat <SDNode ext> : Pat <
3033 (i64 (ext i1:$src)),
3035 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
3036 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src), sub0),
3037 (S_MOV_B32 0), sub1)
3041 def : ZExt_i64_i32_Pat<zext>;
3042 def : ZExt_i64_i32_Pat<anyext>;
3043 def : ZExt_i64_i1_Pat<zext>;
3044 def : ZExt_i64_i1_Pat<anyext>;
3047 (i64 (sext i32:$src)),
3049 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $src, sub0),
3050 (S_ASHR_I32 $src, 31), sub1)
3054 (i64 (sext i1:$src)),
3057 (i64 (IMPLICIT_DEF)),
3058 (V_CNDMASK_B32_e64 0, -1, $src), sub0),
3059 (V_CNDMASK_B32_e64 0, -1, $src), sub1)
3063 (f32 (sint_to_fp i1:$src)),
3064 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_NEG_ONE, $src)
3068 (f32 (uint_to_fp i1:$src)),
3069 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_ONE, $src)
3073 (f64 (sint_to_fp i1:$src)),
3074 (V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src))
3078 (f64 (uint_to_fp i1:$src)),
3079 (V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src))
3082 //===----------------------------------------------------------------------===//
3083 // Miscellaneous Patterns
3084 //===----------------------------------------------------------------------===//
3087 (i32 (trunc i64:$a)),
3088 (EXTRACT_SUBREG $a, sub0)
3092 (i1 (trunc i32:$a)),
3093 (V_CMP_EQ_I32_e64 (V_AND_B32_e64 (i32 1), $a), 1)
3096 //============================================================================//
3097 // Miscellaneous Optimization Patterns
3098 //============================================================================//
3100 def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e64>;
3102 } // End isSI predicate