1 //===-- SIInstructions.td - SI Instruction Defintions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This file was originally auto-generated from a GPU register header file and
10 // all the instruction definitions were originally commented out. Instructions
11 // that are not yet supported remain commented out.
12 //===----------------------------------------------------------------------===//
19 def INTERP : InterpSlots;
21 def InterpSlot : Operand<i32> {
22 let PrintMethod = "printInterpSlot";
25 def SendMsgImm : Operand<i32> {
26 let PrintMethod = "printSendMsg";
29 def isSI : Predicate<"Subtarget.getGeneration() "
30 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">;
32 def isCI : Predicate<"Subtarget.getGeneration() "
33 ">= AMDGPUSubtarget::SEA_ISLANDS">;
35 def isCFDepth0 : Predicate<"isCFDepth0()">;
37 def WAIT_FLAG : InstFlag<"printWaitFlag">;
39 let SubtargetPredicate = isSI in {
40 let OtherPredicates = [isCFDepth0] in {
42 //===----------------------------------------------------------------------===//
44 //===----------------------------------------------------------------------===//
48 // We are using the SGPR_32 and not the SReg_32 register class for 32-bit
49 // SMRD instructions, because the SGPR_32 register class does not include M0
50 // and writing to M0 from an SMRD instruction will hang the GPU.
51 defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SGPR_32>;
52 defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>;
53 defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>;
54 defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>;
55 defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>;
57 defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
58 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SGPR_32
61 defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
62 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64
65 defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper <
66 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128
69 defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <
70 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256
73 defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
74 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512
79 //def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>;
80 //def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>;
82 //===----------------------------------------------------------------------===//
84 //===----------------------------------------------------------------------===//
86 let neverHasSideEffects = 1 in {
88 let isMoveImm = 1 in {
89 def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>;
90 def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>;
91 def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>;
92 def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>;
93 } // End isMoveImm = 1
95 def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32",
96 [(set i32:$dst, (not i32:$src0))]
99 def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64",
100 [(set i64:$dst, (not i64:$src0))]
102 def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>;
103 def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>;
104 def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>;
105 def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>;
106 } // End neverHasSideEffects = 1
108 ////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>;
109 ////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>;
110 ////def S_BCNT1_I32_B32 : SOP1_BCNT1 <0x0000000f, "S_BCNT1_I32_B32", []>;
111 ////def S_BCNT1_I32_B64 : SOP1_BCNT1 <0x00000010, "S_BCNT1_I32_B64", []>;
112 ////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>;
113 ////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>;
114 ////def S_FF1_I32_B32 : SOP1_FF1 <0x00000013, "S_FF1_I32_B32", []>;
115 ////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>;
116 //def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", []>;
117 //def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>;
118 def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>;
119 //def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>;
120 def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8",
121 [(set i32:$dst, (sext_inreg i32:$src0, i8))]
123 def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16",
124 [(set i32:$dst, (sext_inreg i32:$src0, i16))]
127 ////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>;
128 ////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>;
129 ////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>;
130 ////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>;
131 def S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>;
132 def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>;
133 def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>;
134 def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>;
136 let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in {
138 def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>;
139 def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>;
140 def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>;
141 def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>;
142 def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>;
143 def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>;
144 def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>;
145 def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>;
147 } // End hasSideEffects = 1
149 def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>;
150 def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>;
151 def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>;
152 def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>;
153 def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>;
154 def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>;
155 //def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>;
156 def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>;
157 def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>;
158 def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>;
160 //===----------------------------------------------------------------------===//
162 //===----------------------------------------------------------------------===//
164 let Defs = [SCC] in { // Carry out goes to SCC
165 let isCommutable = 1 in {
166 def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>;
167 def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32",
168 [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))]
170 } // End isCommutable = 1
172 def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>;
173 def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32",
174 [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))]
177 let Uses = [SCC] in { // Carry in comes from SCC
178 let isCommutable = 1 in {
179 def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32",
180 [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
181 } // End isCommutable = 1
183 def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32",
184 [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
185 } // End Uses = [SCC]
186 } // End Defs = [SCC]
188 def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32",
189 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]
191 def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32",
192 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]
194 def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32",
195 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]
197 def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32",
198 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]
201 def S_CSELECT_B32 : SOP2 <
202 0x0000000a, (outs SReg_32:$dst),
203 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32",
207 def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>;
209 def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32",
210 [(set i32:$dst, (and i32:$src0, i32:$src1))]
213 def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64",
214 [(set i64:$dst, (and i64:$src0, i64:$src1))]
217 def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32",
218 [(set i32:$dst, (or i32:$src0, i32:$src1))]
221 def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64",
222 [(set i64:$dst, (or i64:$src0, i64:$src1))]
225 def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32",
226 [(set i32:$dst, (xor i32:$src0, i32:$src1))]
229 def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64",
230 [(set i64:$dst, (xor i64:$src0, i64:$src1))]
232 def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>;
233 def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>;
234 def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>;
235 def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>;
236 def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>;
237 def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>;
238 def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>;
239 def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>;
240 def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>;
241 def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>;
243 // Use added complexity so these patterns are preferred to the VALU patterns.
244 let AddedComplexity = 1 in {
246 def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32",
247 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
249 def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "S_LSHL_B64",
250 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
252 def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32",
253 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
255 def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "S_LSHR_B64",
256 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
258 def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32",
259 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
261 def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64",
262 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
265 } // End AddedComplexity = 1
267 def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>;
268 def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>;
269 def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>;
270 def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>;
271 def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>;
272 def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>;
273 def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>;
274 //def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>;
275 def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>;
277 //===----------------------------------------------------------------------===//
279 //===----------------------------------------------------------------------===//
281 def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32">;
282 def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32">;
283 def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32">;
284 def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32">;
285 def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32">;
286 def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32">;
287 def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32">;
288 def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32">;
289 def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32">;
290 def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32">;
291 def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32">;
292 def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32">;
293 ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>;
294 ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>;
295 ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>;
296 ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>;
297 //def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>;
299 //===----------------------------------------------------------------------===//
301 //===----------------------------------------------------------------------===//
303 def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>;
304 def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>;
307 This instruction is disabled for now until we can figure out how to teach
308 the instruction selector to correctly use the S_CMP* vs V_CMP*
311 When this instruction is enabled the code generator sometimes produces this
314 SCC = S_CMPK_EQ_I32 SGPR0, imm
316 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
318 def S_CMPK_EQ_I32 : SOPK <
319 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1),
321 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))]
325 let isCompare = 1 in {
326 def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>;
327 def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>;
328 def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>;
329 def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>;
330 def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>;
331 def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>;
332 def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>;
333 def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>;
334 def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>;
335 def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>;
336 def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>;
337 } // End isCompare = 1
339 let Defs = [SCC], isCommutable = 1 in {
340 def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>;
341 def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>;
344 //def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>;
345 def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>;
346 def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>;
347 def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>;
348 //def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>;
349 //def EXP : EXP_ <0x00000000, "EXP", []>;
351 } // End let OtherPredicates = [isCFDepth0]
353 //===----------------------------------------------------------------------===//
355 //===----------------------------------------------------------------------===//
357 def S_NOP : SOPP <0x00000000, (ins i16imm:$SIMM16), "S_NOP $SIMM16", []>;
359 let isTerminator = 1 in {
361 def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM",
368 let isBranch = 1 in {
369 def S_BRANCH : SOPP <
370 0x00000002, (ins brtarget:$target), "S_BRANCH $target",
375 let DisableEncoding = "$scc" in {
376 def S_CBRANCH_SCC0 : SOPP <
377 0x00000004, (ins brtarget:$target, SCCReg:$scc),
378 "S_CBRANCH_SCC0 $target", []
380 def S_CBRANCH_SCC1 : SOPP <
381 0x00000005, (ins brtarget:$target, SCCReg:$scc),
382 "S_CBRANCH_SCC1 $target",
385 } // End DisableEncoding = "$scc"
387 def S_CBRANCH_VCCZ : SOPP <
388 0x00000006, (ins brtarget:$target, VCCReg:$vcc),
389 "S_CBRANCH_VCCZ $target",
392 def S_CBRANCH_VCCNZ : SOPP <
393 0x00000007, (ins brtarget:$target, VCCReg:$vcc),
394 "S_CBRANCH_VCCNZ $target",
398 let DisableEncoding = "$exec" in {
399 def S_CBRANCH_EXECZ : SOPP <
400 0x00000008, (ins brtarget:$target, EXECReg:$exec),
401 "S_CBRANCH_EXECZ $target",
404 def S_CBRANCH_EXECNZ : SOPP <
405 0x00000009, (ins brtarget:$target, EXECReg:$exec),
406 "S_CBRANCH_EXECNZ $target",
409 } // End DisableEncoding = "$exec"
412 } // End isBranch = 1
413 } // End isTerminator = 1
415 let hasSideEffects = 1 in {
416 def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER",
417 [(int_AMDGPU_barrier_local)]
426 def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16",
429 //def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>;
430 //def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>;
431 //def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>;
433 let Uses = [EXEC] in {
434 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "S_SENDMSG $simm16",
435 [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)]
437 let DisableEncoding = "$m0";
439 } // End Uses = [EXEC]
441 //def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>;
442 //def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>;
443 //def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>;
444 //def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>;
445 //def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>;
446 //def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
447 } // End hasSideEffects
449 //===----------------------------------------------------------------------===//
451 //===----------------------------------------------------------------------===//
453 let isCompare = 1 in {
455 defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">;
456 defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_OLT>;
457 defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", f32, COND_OEQ>;
458 defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", f32, COND_OLE>;
459 defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", f32, COND_OGT>;
460 defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32">;
461 defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", f32, COND_OGE>;
462 defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32", f32, COND_O>;
463 defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32", f32, COND_UO>;
464 defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32">;
465 defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32">;
466 defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32">;
467 defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32">;
468 defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", f32, COND_UNE>;
469 defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">;
470 defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">;
472 let hasSideEffects = 1, Defs = [EXEC] in {
474 defm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32">;
475 defm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32">;
476 defm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32">;
477 defm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32">;
478 defm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32">;
479 defm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32">;
480 defm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32">;
481 defm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32">;
482 defm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32">;
483 defm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32">;
484 defm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32">;
485 defm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32">;
486 defm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32">;
487 defm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32">;
488 defm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32">;
489 defm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32">;
491 } // End hasSideEffects = 1, Defs = [EXEC]
493 defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">;
494 defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64", f64, COND_OLT>;
495 defm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64", f64, COND_OEQ>;
496 defm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64", f64, COND_OLE>;
497 defm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64", f64, COND_OGT>;
498 defm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64">;
499 defm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64", f64, COND_OGE>;
500 defm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64", f64, COND_O>;
501 defm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64", f64, COND_UO>;
502 defm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64">;
503 defm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64">;
504 defm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64">;
505 defm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64">;
506 defm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64", f64, COND_UNE>;
507 defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">;
508 defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">;
510 let hasSideEffects = 1, Defs = [EXEC] in {
512 defm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64">;
513 defm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64">;
514 defm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64">;
515 defm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64">;
516 defm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64">;
517 defm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64">;
518 defm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64">;
519 defm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64">;
520 defm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64">;
521 defm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64">;
522 defm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64">;
523 defm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64">;
524 defm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64">;
525 defm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64">;
526 defm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64">;
527 defm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64">;
529 } // End hasSideEffects = 1, Defs = [EXEC]
531 defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">;
532 defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">;
533 defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32">;
534 defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32">;
535 defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32">;
536 defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32">;
537 defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32">;
538 defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32">;
539 defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32">;
540 defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32">;
541 defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32">;
542 defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32">;
543 defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32">;
544 defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">;
545 defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">;
546 defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">;
548 let hasSideEffects = 1, Defs = [EXEC] in {
550 defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32">;
551 defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32">;
552 defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32">;
553 defm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32">;
554 defm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32">;
555 defm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32">;
556 defm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32">;
557 defm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32">;
558 defm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32">;
559 defm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32">;
560 defm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32">;
561 defm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32">;
562 defm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32">;
563 defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32">;
564 defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32">;
565 defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32">;
567 } // End hasSideEffects = 1, Defs = [EXEC]
569 defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">;
570 defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">;
571 defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">;
572 defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64">;
573 defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64">;
574 defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64">;
575 defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64">;
576 defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64">;
577 defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64">;
578 defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64">;
579 defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64">;
580 defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64">;
581 defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64">;
582 defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">;
583 defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">;
584 defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">;
586 let hasSideEffects = 1, Defs = [EXEC] in {
588 defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">;
589 defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">;
590 defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">;
591 defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64">;
592 defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64">;
593 defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64">;
594 defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64">;
595 defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64">;
596 defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64">;
597 defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64">;
598 defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64">;
599 defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64">;
600 defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64">;
601 defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">;
602 defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">;
603 defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">;
605 } // End hasSideEffects = 1, Defs = [EXEC]
607 defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">;
608 defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_SLT>;
609 defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>;
610 defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", i32, COND_SLE>;
611 defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", i32, COND_SGT>;
612 defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", i32, COND_NE>;
613 defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_SGE>;
614 defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">;
616 let hasSideEffects = 1, Defs = [EXEC] in {
618 defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32">;
619 defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32">;
620 defm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32">;
621 defm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32">;
622 defm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32">;
623 defm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32">;
624 defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32">;
625 defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32">;
627 } // End hasSideEffects = 1, Defs = [EXEC]
629 defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">;
630 defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64", i64, COND_SLT>;
631 defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64", i64, COND_EQ>;
632 defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64", i64, COND_SLE>;
633 defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64", i64, COND_SGT>;
634 defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64", i64, COND_NE>;
635 defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64", i64, COND_SGE>;
636 defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">;
638 let hasSideEffects = 1, Defs = [EXEC] in {
640 defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64">;
641 defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64">;
642 defm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64">;
643 defm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64">;
644 defm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64">;
645 defm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64">;
646 defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64">;
647 defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64">;
649 } // End hasSideEffects = 1, Defs = [EXEC]
651 defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">;
652 defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32", i32, COND_ULT>;
653 defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32", i32, COND_EQ>;
654 defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32", i32, COND_ULE>;
655 defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32", i32, COND_UGT>;
656 defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32", i32, COND_NE>;
657 defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32", i32, COND_UGE>;
658 defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">;
660 let hasSideEffects = 1, Defs = [EXEC] in {
662 defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32">;
663 defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32">;
664 defm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32">;
665 defm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32">;
666 defm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32">;
667 defm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32">;
668 defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32">;
669 defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32">;
671 } // End hasSideEffects = 1, Defs = [EXEC]
673 defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">;
674 defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64", i64, COND_ULT>;
675 defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64", i64, COND_EQ>;
676 defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64", i64, COND_ULE>;
677 defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64", i64, COND_UGT>;
678 defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64", i64, COND_NE>;
679 defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64", i64, COND_UGE>;
680 defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">;
682 let hasSideEffects = 1, Defs = [EXEC] in {
684 defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64">;
685 defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64">;
686 defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64">;
687 defm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64">;
688 defm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64">;
689 defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64">;
690 defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64">;
691 defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64">;
693 } // End hasSideEffects = 1, Defs = [EXEC]
695 defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">;
697 let hasSideEffects = 1, Defs = [EXEC] in {
698 defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">;
699 } // End hasSideEffects = 1, Defs = [EXEC]
701 defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">;
703 let hasSideEffects = 1, Defs = [EXEC] in {
704 defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">;
705 } // End hasSideEffects = 1, Defs = [EXEC]
707 } // End isCompare = 1
709 //===----------------------------------------------------------------------===//
711 //===----------------------------------------------------------------------===//
713 def DS_ADD_U32_RTN : DS_1A1D_RET <0x20, "DS_ADD_U32_RTN", VReg_32>;
714 def DS_SUB_U32_RTN : DS_1A1D_RET <0x21, "DS_SUB_U32_RTN", VReg_32>;
715 def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>;
716 def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "DS_WRITE_B8", VReg_32>;
717 def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "DS_WRITE_B16", VReg_32>;
718 def DS_WRITE_B64 : DS_Store_Helper <0x00000004d, "DS_WRITE_B64", VReg_64>;
720 def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>;
721 def DS_READ_I8 : DS_Load_Helper <0x00000039, "DS_READ_I8", VReg_32>;
722 def DS_READ_U8 : DS_Load_Helper <0x0000003a, "DS_READ_U8", VReg_32>;
723 def DS_READ_I16 : DS_Load_Helper <0x0000003b, "DS_READ_I16", VReg_32>;
724 def DS_READ_U16 : DS_Load_Helper <0x0000003c, "DS_READ_U16", VReg_32>;
725 def DS_READ_B64 : DS_Load_Helper <0x00000076, "DS_READ_B64", VReg_64>;
728 def DS_WRITE2_B32 : DS_Load2_Helper <0x0000000E, "DS_WRITE2_B32", VReg_64>;
729 def DS_WRITE2_B64 : DS_Load2_Helper <0x0000004E, "DS_WRITE2_B64", VReg_128>;
731 def DS_READ2_B32 : DS_Load2_Helper <0x00000037, "DS_READ2_B32", VReg_64>;
732 def DS_READ2_B64 : DS_Load2_Helper <0x00000075, "DS_READ2_B64", VReg_128>;
734 // TODO: DS_READ2ST64_B32, DS_READ2ST64_B64,
735 // DS_WRITE2ST64_B32, DS_WRITE2ST64_B64
737 //===----------------------------------------------------------------------===//
738 // MUBUF Instructions
739 //===----------------------------------------------------------------------===//
741 //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>;
742 //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>;
743 //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>;
744 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>;
745 //def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>;
746 //def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>;
747 //def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>;
748 //def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>;
749 defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <0x00000008, "BUFFER_LOAD_UBYTE", VReg_32>;
750 defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <0x00000009, "BUFFER_LOAD_SBYTE", VReg_32>;
751 defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <0x0000000a, "BUFFER_LOAD_USHORT", VReg_32>;
752 defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32>;
753 defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <0x0000000c, "BUFFER_LOAD_DWORD", VReg_32>;
754 defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64>;
755 defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128>;
757 def BUFFER_STORE_BYTE : MUBUF_Store_Helper <
758 0x00000018, "BUFFER_STORE_BYTE", VReg_32
761 def BUFFER_STORE_SHORT : MUBUF_Store_Helper <
762 0x0000001a, "BUFFER_STORE_SHORT", VReg_32
765 def BUFFER_STORE_DWORD : MUBUF_Store_Helper <
766 0x0000001c, "BUFFER_STORE_DWORD", VReg_32
769 def BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper <
770 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64
773 def BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper <
774 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128
776 //def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>;
777 //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>;
778 //def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>;
779 //def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>;
780 //def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>;
781 //def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>;
782 //def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>;
783 //def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>;
784 //def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>;
785 //def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>;
786 //def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>;
787 //def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>;
788 //def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>;
789 //def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>;
790 //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>;
791 //def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>;
792 //def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>;
793 //def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>;
794 //def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>;
795 //def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>;
796 //def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>;
797 //def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>;
798 //def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>;
799 //def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>;
800 //def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>;
801 //def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>;
802 //def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>;
803 //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>;
804 //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>;
805 //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>;
806 //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>;
807 //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>;
808 //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>;
809 //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>;
810 //def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>;
811 //def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>;
813 //===----------------------------------------------------------------------===//
814 // MTBUF Instructions
815 //===----------------------------------------------------------------------===//
817 //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>;
818 //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>;
819 //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>;
820 def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>;
821 def TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "TBUFFER_STORE_FORMAT_X", VReg_32>;
822 def TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FORMAT_XY", VReg_64>;
823 def TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>;
824 def TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>;
826 //===----------------------------------------------------------------------===//
828 //===----------------------------------------------------------------------===//
830 defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "IMAGE_LOAD">;
831 defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "IMAGE_LOAD_MIP">;
832 //def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>;
833 //def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>;
834 //def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>;
835 //def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>;
836 //def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>;
837 //def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>;
838 //def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>;
839 //def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>;
840 defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "IMAGE_GET_RESINFO">;
841 //def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>;
842 //def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>;
843 //def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>;
844 //def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>;
845 //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>;
846 //def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>;
847 //def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>;
848 //def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>;
849 //def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>;
850 //def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>;
851 //def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>;
852 //def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>;
853 //def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>;
854 //def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>;
855 //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>;
856 //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>;
857 //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>;
858 defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">;
859 //def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>;
860 defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">;
861 //def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>;
862 defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">;
863 defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">;
864 //def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>;
865 //def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>;
866 defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">;
867 //def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>;
868 defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">;
869 //def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>;
870 defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">;
871 defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">;
872 //def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>;
873 //def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>;
874 //def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>;
875 //def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>;
876 //def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>;
877 //def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>;
878 //def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>;
879 //def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>;
880 //def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>;
881 //def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>;
882 //def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>;
883 //def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>;
884 //def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>;
885 //def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>;
886 //def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>;
887 //def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>;
888 //def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>;
889 //def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>;
890 //def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>;
891 //def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>;
892 //def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>;
893 //def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>;
894 //def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>;
895 //def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>;
896 //def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>;
897 //def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>;
898 //def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>;
899 //def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>;
900 //def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>;
901 //def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>;
902 //def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>;
903 //def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>;
904 //def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>;
905 //def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>;
906 //def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>;
907 //def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>;
908 //def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>;
909 //def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>;
910 //def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>;
911 //def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>;
912 //def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>;
913 //def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>;
914 //def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>;
915 //def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>;
916 //def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>;
917 //def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>;
918 //def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>;
919 //def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>;
920 //def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>;
921 //def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>;
922 //def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>;
923 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>;
924 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>;
926 //===----------------------------------------------------------------------===//
928 //===----------------------------------------------------------------------===//
930 //def V_NOP : VOP1_ <0x00000000, "V_NOP", []>;
932 let neverHasSideEffects = 1, isMoveImm = 1 in {
933 defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>;
934 } // End neverHasSideEffects = 1, isMoveImm = 1
936 let Uses = [EXEC] in {
938 def V_READFIRSTLANE_B32 : VOP1 <
940 (outs SReg_32:$vdst),
942 "V_READFIRSTLANE_B32 $vdst, $src0",
948 defm V_CVT_I32_F64 : VOP1_32_64 <0x00000003, "V_CVT_I32_F64",
949 [(set i32:$dst, (fp_to_sint f64:$src0))]
951 defm V_CVT_F64_I32 : VOP1_64_32 <0x00000004, "V_CVT_F64_I32",
952 [(set f64:$dst, (sint_to_fp i32:$src0))]
954 defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32",
955 [(set f32:$dst, (sint_to_fp i32:$src0))]
957 defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32",
958 [(set f32:$dst, (uint_to_fp i32:$src0))]
960 defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32",
961 [(set i32:$dst, (fp_to_uint f32:$src0))]
963 defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32",
964 [(set i32:$dst, (fp_to_sint f32:$src0))]
966 defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>;
967 ////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>;
968 //defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>;
969 //defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>;
970 //defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>;
971 //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>;
972 defm V_CVT_F32_F64 : VOP1_32_64 <0x0000000f, "V_CVT_F32_F64",
973 [(set f32:$dst, (fround f64:$src0))]
975 defm V_CVT_F64_F32 : VOP1_64_32 <0x00000010, "V_CVT_F64_F32",
976 [(set f64:$dst, (fextend f32:$src0))]
978 //defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0", []>;
979 //defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1", []>;
980 //defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2", []>;
981 //defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", []>;
982 defm V_CVT_U32_F64 : VOP1_32_64 <0x00000015, "V_CVT_U32_F64",
983 [(set i32:$dst, (fp_to_uint f64:$src0))]
985 defm V_CVT_F64_U32 : VOP1_64_32 <0x00000016, "V_CVT_F64_U32",
986 [(set f64:$dst, (uint_to_fp i32:$src0))]
989 defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32",
990 [(set f32:$dst, (AMDGPUfract f32:$src0))]
992 defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32",
993 [(set f32:$dst, (int_AMDGPU_trunc f32:$src0))]
995 defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32",
996 [(set f32:$dst, (fceil f32:$src0))]
998 defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32",
999 [(set f32:$dst, (frint f32:$src0))]
1001 defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32",
1002 [(set f32:$dst, (ffloor f32:$src0))]
1004 defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32",
1005 [(set f32:$dst, (fexp2 f32:$src0))]
1007 defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>;
1008 defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32",
1009 [(set f32:$dst, (flog2 f32:$src0))]
1011 defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>;
1012 defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>;
1013 defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32",
1014 [(set f32:$dst, (fdiv FP_ONE, f32:$src0))]
1016 defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>;
1017 defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>;
1018 defm V_RSQ_LEGACY_F32 : VOP1_32 <
1019 0x0000002d, "V_RSQ_LEGACY_F32",
1020 [(set f32:$dst, (int_AMDGPU_rsq f32:$src0))]
1022 defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32",
1023 [(set f32:$dst, (fdiv FP_ONE, (fsqrt f32:$src0)))]
1025 defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64",
1026 [(set f64:$dst, (fdiv FP_ONE, f64:$src0))]
1028 defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>;
1029 defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64",
1030 [(set f64:$dst, (fdiv FP_ONE, (fsqrt f64:$src0)))]
1032 defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>;
1033 defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32",
1034 [(set f32:$dst, (fsqrt f32:$src0))]
1036 defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64",
1037 [(set f64:$dst, (fsqrt f64:$src0))]
1039 defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>;
1040 defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>;
1041 defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>;
1042 defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>;
1043 defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>;
1044 defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>;
1045 defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>;
1046 //defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>;
1047 defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>;
1048 defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>;
1049 //defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>;
1050 defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>;
1051 //def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>;
1052 defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>;
1053 defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>;
1054 defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>;
1057 //===----------------------------------------------------------------------===//
1058 // VINTRP Instructions
1059 //===----------------------------------------------------------------------===//
1061 def V_INTERP_P1_F32 : VINTRP <
1063 (outs VReg_32:$dst),
1064 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1065 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]",
1067 let DisableEncoding = "$m0";
1070 def V_INTERP_P2_F32 : VINTRP <
1072 (outs VReg_32:$dst),
1073 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1074 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]",
1077 let Constraints = "$src0 = $dst";
1078 let DisableEncoding = "$src0,$m0";
1082 def V_INTERP_MOV_F32 : VINTRP <
1084 (outs VReg_32:$dst),
1085 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1086 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]",
1088 let DisableEncoding = "$m0";
1091 //===----------------------------------------------------------------------===//
1092 // VOP2 Instructions
1093 //===----------------------------------------------------------------------===//
1095 def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
1096 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc),
1097 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]",
1100 let DisableEncoding = "$vcc";
1103 def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst),
1104 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2,
1105 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
1106 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg",
1107 [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))]
1109 let src0_modifiers = 0;
1110 let src1_modifiers = 0;
1111 let src2_modifiers = 0;
1114 def V_READLANE_B32 : VOP2 <
1116 (outs SReg_32:$vdst),
1117 (ins VReg_32:$src0, SSrc_32:$vsrc1),
1118 "V_READLANE_B32 $vdst, $src0, $vsrc1",
1122 def V_WRITELANE_B32 : VOP2 <
1124 (outs VReg_32:$vdst),
1125 (ins SReg_32:$src0, SSrc_32:$vsrc1),
1126 "V_WRITELANE_B32 $vdst, $src0, $vsrc1",
1130 let isCommutable = 1 in {
1131 defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32",
1132 [(set f32:$dst, (fadd f32:$src0, f32:$src1))]
1135 defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32",
1136 [(set f32:$dst, (fsub f32:$src0, f32:$src1))]
1138 defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", [], "V_SUB_F32">;
1139 } // End isCommutable = 1
1141 defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>;
1143 let isCommutable = 1 in {
1145 defm V_MUL_LEGACY_F32 : VOP2_32 <
1146 0x00000007, "V_MUL_LEGACY_F32",
1147 [(set f32:$dst, (int_AMDGPU_mul f32:$src0, f32:$src1))]
1150 defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32",
1151 [(set f32:$dst, (fmul f32:$src0, f32:$src1))]
1155 defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24",
1156 [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))]
1158 //defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>;
1159 defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24",
1160 [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))]
1162 //defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>;
1165 defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32",
1166 [(set f32:$dst, (AMDGPUfmin f32:$src0, f32:$src1))]
1169 defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32",
1170 [(set f32:$dst, (AMDGPUfmax f32:$src0, f32:$src1))]
1173 defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>;
1174 defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>;
1175 defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32",
1176 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]>;
1177 defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32",
1178 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]>;
1179 defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32",
1180 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]>;
1181 defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32",
1182 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]>;
1184 defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32",
1185 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
1188 defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">;
1190 defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32",
1191 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
1193 defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">;
1195 let hasPostISelHook = 1 in {
1197 defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32",
1198 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
1202 defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">;
1204 defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32",
1205 [(set i32:$dst, (and i32:$src0, i32:$src1))]>;
1206 defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32",
1207 [(set i32:$dst, (or i32:$src0, i32:$src1))]
1209 defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32",
1210 [(set i32:$dst, (xor i32:$src0, i32:$src1))]
1213 } // End isCommutable = 1
1215 defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32",
1216 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))]>;
1217 defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>;
1218 defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>;
1219 defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>;
1220 //defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>;
1221 defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>;
1222 defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>;
1224 let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC
1225 // No patterns so that the scalar instructions are always selected.
1226 // The scalar versions will be replaced with vector when needed later.
1227 defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32",
1228 [(set i32:$dst, (add i32:$src0, i32:$src1))], VSrc_32>;
1229 defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32",
1230 [(set i32:$dst, (sub i32:$src0, i32:$src1))], VSrc_32>;
1231 defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], VSrc_32,
1234 let Uses = [VCC] in { // Carry-in comes from VCC
1235 defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32",
1236 [(set i32:$dst, (adde i32:$src0, i32:$src1))], VReg_32>;
1237 defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32",
1238 [(set i32:$dst, (sube i32:$src0, i32:$src1))], VReg_32>;
1239 defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], VReg_32,
1241 } // End Uses = [VCC]
1242 } // End isCommutable = 1, Defs = [VCC]
1244 defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>;
1245 ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>;
1246 ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>;
1247 ////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>;
1248 defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32",
1249 [(set i32:$dst, (int_SI_packf16 f32:$src0, f32:$src1))]
1251 ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>;
1252 ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>;
1254 //===----------------------------------------------------------------------===//
1255 // VOP3 Instructions
1256 //===----------------------------------------------------------------------===//
1258 let neverHasSideEffects = 1 in {
1260 defm V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>;
1261 defm V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32",
1262 [(set f32:$dst, (fadd (fmul f32:$src0, f32:$src1), f32:$src2))]
1264 defm V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24",
1265 [(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))]
1267 defm V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24",
1268 [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))]
1271 } // End neverHasSideEffects
1273 defm V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>;
1274 defm V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>;
1275 defm V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>;
1276 defm V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>;
1278 let neverHasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
1279 defm V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32",
1280 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))]>;
1281 defm V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32",
1282 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))]>;
1285 defm V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32",
1286 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))]>;
1287 defm V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32",
1288 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))]
1290 def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64",
1291 [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
1293 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>;
1294 defm V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>;
1296 defm V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>;
1297 defm V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>;
1298 ////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>;
1299 ////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>;
1300 ////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>;
1301 ////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>;
1302 ////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>;
1303 ////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>;
1304 ////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>;
1305 ////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>;
1306 ////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>;
1307 //def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>;
1308 //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>;
1309 //def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>;
1310 defm V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>;
1311 ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>;
1312 defm V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>;
1313 def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>;
1315 def V_LSHL_B64 : VOP3_64_32 <0x00000161, "V_LSHL_B64",
1316 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
1318 def V_LSHR_B64 : VOP3_64_32 <0x00000162, "V_LSHR_B64",
1319 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
1321 def V_ASHR_I64 : VOP3_64_32 <0x00000163, "V_ASHR_I64",
1322 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
1325 let isCommutable = 1 in {
1327 def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>;
1328 def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>;
1329 def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>;
1330 def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>;
1332 } // isCommutable = 1
1334 def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>;
1336 let isCommutable = 1 in {
1338 defm V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>;
1339 defm V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>;
1340 defm V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>;
1341 defm V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>;
1343 } // isCommutable = 1
1345 defm V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>;
1346 def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>;
1347 defm V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>;
1348 def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>;
1349 //def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>;
1350 //def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>;
1351 //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>;
1352 def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>;
1354 //===----------------------------------------------------------------------===//
1355 // Pseudo Instructions
1356 //===----------------------------------------------------------------------===//
1358 let isCodeGenOnly = 1, isPseudo = 1 in {
1360 def V_MOV_I1 : InstSI <
1363 "", [(set i1:$dst, (imm:$src))]
1366 def V_AND_I1 : InstSI <
1367 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1368 [(set i1:$dst, (and i1:$src0, i1:$src1))]
1371 def V_OR_I1 : InstSI <
1372 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1373 [(set i1:$dst, (or i1:$src0, i1:$src1))]
1376 // SI pseudo instructions. These are used by the CFG structurizer pass
1377 // and should be lowered to ISA instructions prior to codegen.
1379 let mayLoad = 1, mayStore = 1, hasSideEffects = 1,
1380 Uses = [EXEC], Defs = [EXEC] in {
1382 let isBranch = 1, isTerminator = 1 in {
1385 (outs SReg_64:$dst),
1386 (ins SReg_64:$vcc, brtarget:$target),
1388 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))]
1391 def SI_ELSE : InstSI <
1392 (outs SReg_64:$dst),
1393 (ins SReg_64:$src, brtarget:$target),
1395 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]
1397 let Constraints = "$src = $dst";
1400 def SI_LOOP : InstSI <
1402 (ins SReg_64:$saved, brtarget:$target),
1403 "SI_LOOP $saved, $target",
1404 [(int_SI_loop i64:$saved, bb:$target)]
1407 } // end isBranch = 1, isTerminator = 1
1409 def SI_BREAK : InstSI <
1410 (outs SReg_64:$dst),
1412 "SI_ELSE $dst, $src",
1413 [(set i64:$dst, (int_SI_break i64:$src))]
1416 def SI_IF_BREAK : InstSI <
1417 (outs SReg_64:$dst),
1418 (ins SReg_64:$vcc, SReg_64:$src),
1419 "SI_IF_BREAK $dst, $vcc, $src",
1420 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))]
1423 def SI_ELSE_BREAK : InstSI <
1424 (outs SReg_64:$dst),
1425 (ins SReg_64:$src0, SReg_64:$src1),
1426 "SI_ELSE_BREAK $dst, $src0, $src1",
1427 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))]
1430 def SI_END_CF : InstSI <
1432 (ins SReg_64:$saved),
1434 [(int_SI_end_cf i64:$saved)]
1437 def SI_KILL : InstSI <
1441 [(int_AMDGPU_kill f32:$src)]
1444 } // end mayLoad = 1, mayStore = 1, hasSideEffects = 1
1445 // Uses = [EXEC], Defs = [EXEC]
1447 let Uses = [EXEC], Defs = [EXEC,VCC,M0] in {
1449 //defm SI_ : RegisterLoadStore <VReg_32, FRAMEri, ADDRIndirect>;
1451 let UseNamedOperandTable = 1 in {
1453 def SI_RegisterLoad : InstSI <
1454 (outs VReg_32:$dst, SReg_64:$temp),
1455 (ins FRAMEri32:$addr, i32imm:$chan),
1458 let isRegisterLoad = 1;
1462 class SIRegStore<dag outs> : InstSI <
1464 (ins VReg_32:$val, FRAMEri32:$addr, i32imm:$chan),
1467 let isRegisterStore = 1;
1471 let usesCustomInserter = 1 in {
1472 def SI_RegisterStorePseudo : SIRegStore<(outs)>;
1473 } // End usesCustomInserter = 1
1474 def SI_RegisterStore : SIRegStore<(outs SReg_64:$temp)>;
1477 } // End UseNamedOperandTable = 1
1479 def SI_INDIRECT_SRC : InstSI <
1480 (outs VReg_32:$dst, SReg_64:$temp),
1481 (ins unknown:$src, VSrc_32:$idx, i32imm:$off),
1482 "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off",
1486 class SI_INDIRECT_DST<RegisterClass rc> : InstSI <
1487 (outs rc:$dst, SReg_64:$temp),
1488 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val),
1489 "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val",
1492 let Constraints = "$src = $dst";
1495 def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VReg_32>;
1496 def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
1497 def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
1498 def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
1499 def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
1501 } // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0]
1503 let usesCustomInserter = 1 in {
1505 // This pseudo instruction takes a pointer as input and outputs a resource
1506 // constant that can be used with the ADDR64 MUBUF instructions.
1507 def SI_ADDR64_RSRC : InstSI <
1508 (outs SReg_128:$srsrc),
1513 def V_SUB_F64 : InstSI <
1514 (outs VReg_64:$dst),
1515 (ins VReg_64:$src0, VReg_64:$src1),
1516 "V_SUB_F64 $dst, $src0, $src1",
1520 } // end usesCustomInserter
1522 multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
1524 def _SAVE : InstSI <
1525 (outs VReg_32:$dst),
1526 (ins sgpr_class:$src, i32imm:$frame_idx),
1530 def _RESTORE : InstSI <
1531 (outs sgpr_class:$dst),
1532 (ins VReg_32:$src, i32imm:$frame_idx),
1538 defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>;
1539 defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>;
1540 defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>;
1541 defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;
1543 } // end IsCodeGenOnly, isPseudo
1545 } // end SubtargetPredicate = SI
1547 let Predicates = [isSI] in {
1550 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2),
1551 (V_CNDMASK_B32_e64 $src2, $src1, (V_CMP_GT_F32_e64 0, $src0))
1556 (SI_KILL 0xbf800000)
1559 /* int_SI_vs_load_input */
1561 (SIload_input v4i32:$tlst, IMM12bit:$attr_offset, i32:$buf_idx_vgpr),
1562 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0)
1567 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
1568 f32:$src0, f32:$src1, f32:$src2, f32:$src3),
1569 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
1570 $src0, $src1, $src2, $src3)
1574 (f64 (fsub f64:$src0, f64:$src1)),
1575 (V_SUB_F64 $src0, $src1)
1578 //===----------------------------------------------------------------------===//
1580 //===----------------------------------------------------------------------===//
1582 multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
1584 // 1. Offset as 8bit DWORD immediate
1586 (constant_load (add i64:$sbase, (i64 IMM8bitDWORD:$offset))),
1587 (vt (Instr_IMM $sbase, (as_dword_i32imm $offset)))
1590 // 2. Offset loaded in an 32bit SGPR
1592 (constant_load (add i64:$sbase, (i64 IMM32bit:$offset))),
1593 (vt (Instr_SGPR $sbase, (S_MOV_B32 (i32 (as_i32imm $offset)))))
1596 // 3. No offset at all
1598 (constant_load i64:$sbase),
1599 (vt (Instr_IMM $sbase, 0))
1603 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>;
1604 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
1605 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, i64>;
1606 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>;
1607 defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>;
1608 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
1609 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>;
1610 defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
1612 // 1. Offset as 8bit DWORD immediate
1614 (SIload_constant v4i32:$sbase, IMM8bitDWORD:$offset),
1615 (S_BUFFER_LOAD_DWORD_IMM $sbase, (as_dword_i32imm $offset))
1618 // 2. Offset loaded in an 32bit SGPR
1620 (SIload_constant v4i32:$sbase, imm:$offset),
1621 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset))
1624 //===----------------------------------------------------------------------===//
1626 //===----------------------------------------------------------------------===//
1629 (i1 (xor i1:$src0, i1:$src1)),
1630 (S_XOR_B64 $src0, $src1)
1633 //===----------------------------------------------------------------------===//
1635 //===----------------------------------------------------------------------===//
1638 (or i64:$src0, i64:$src1),
1639 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1640 (V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub0),
1641 (EXTRACT_SUBREG i64:$src1, sub0)), sub0),
1642 (V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub1),
1643 (EXTRACT_SUBREG i64:$src1, sub1)), sub1)
1646 class SextInReg <ValueType vt, int ShiftAmt> : Pat <
1647 (sext_inreg i32:$src0, vt),
1648 (V_ASHRREV_I32_e32 ShiftAmt, (V_LSHLREV_B32_e32 ShiftAmt, $src0))
1651 def : SextInReg <i8, 24>;
1652 def : SextInReg <i16, 16>;
1654 /********** ======================= **********/
1655 /********** Image sampling patterns **********/
1656 /********** ======================= **********/
1658 /* SIsample for simple 1D texture lookup */
1660 (SIsample i32:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
1661 (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1664 class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1665 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
1666 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1669 class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1670 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_RECT),
1671 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1674 class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1675 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_ARRAY),
1676 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1679 class SampleShadowPattern<SDNode name, MIMG opcode,
1680 ValueType vt> : Pat <
1681 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW),
1682 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1685 class SampleShadowArrayPattern<SDNode name, MIMG opcode,
1686 ValueType vt> : Pat <
1687 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
1688 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1691 /* SIsample* for texture lookups consuming more address parameters */
1692 multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l,
1693 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b,
1694 MIMG sample_d, MIMG sample_c_d, ValueType addr_type> {
1695 def : SamplePattern <SIsample, sample, addr_type>;
1696 def : SampleRectPattern <SIsample, sample, addr_type>;
1697 def : SampleArrayPattern <SIsample, sample, addr_type>;
1698 def : SampleShadowPattern <SIsample, sample_c, addr_type>;
1699 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>;
1701 def : SamplePattern <SIsamplel, sample_l, addr_type>;
1702 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>;
1703 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>;
1704 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>;
1706 def : SamplePattern <SIsampleb, sample_b, addr_type>;
1707 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>;
1708 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>;
1709 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>;
1711 def : SamplePattern <SIsampled, sample_d, addr_type>;
1712 def : SampleArrayPattern <SIsampled, sample_d, addr_type>;
1713 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>;
1714 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>;
1717 defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2,
1718 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2,
1719 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2,
1720 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2,
1722 defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4,
1723 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4,
1724 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4,
1725 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4,
1727 defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8,
1728 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8,
1729 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8,
1730 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8,
1732 defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16,
1733 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16,
1734 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16,
1735 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16,
1738 /* int_SI_imageload for texture fetches consuming varying address parameters */
1739 class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1740 (name addr_type:$addr, v32i8:$rsrc, imm),
1741 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
1744 class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1745 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY),
1746 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
1749 class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1750 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA),
1751 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
1754 class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1755 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA),
1756 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
1759 multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> {
1760 def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>;
1761 def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>;
1764 multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> {
1765 def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>;
1766 def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>;
1769 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V2, v2i32>;
1770 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V4, v4i32>;
1772 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V2, v2i32>;
1773 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V4, v4i32>;
1775 /* Image resource information */
1777 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm),
1778 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1782 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY),
1783 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1787 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA),
1788 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1791 /********** ============================================ **********/
1792 /********** Extraction, Insertion, Building and Casting **********/
1793 /********** ============================================ **********/
1795 foreach Index = 0-2 in {
1796 def Extract_Element_v2i32_#Index : Extract_Element <
1797 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
1799 def Insert_Element_v2i32_#Index : Insert_Element <
1800 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
1803 def Extract_Element_v2f32_#Index : Extract_Element <
1804 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
1806 def Insert_Element_v2f32_#Index : Insert_Element <
1807 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
1811 foreach Index = 0-3 in {
1812 def Extract_Element_v4i32_#Index : Extract_Element <
1813 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
1815 def Insert_Element_v4i32_#Index : Insert_Element <
1816 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
1819 def Extract_Element_v4f32_#Index : Extract_Element <
1820 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
1822 def Insert_Element_v4f32_#Index : Insert_Element <
1823 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
1827 foreach Index = 0-7 in {
1828 def Extract_Element_v8i32_#Index : Extract_Element <
1829 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
1831 def Insert_Element_v8i32_#Index : Insert_Element <
1832 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
1835 def Extract_Element_v8f32_#Index : Extract_Element <
1836 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
1838 def Insert_Element_v8f32_#Index : Insert_Element <
1839 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
1843 foreach Index = 0-15 in {
1844 def Extract_Element_v16i32_#Index : Extract_Element <
1845 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
1847 def Insert_Element_v16i32_#Index : Insert_Element <
1848 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
1851 def Extract_Element_v16f32_#Index : Extract_Element <
1852 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
1854 def Insert_Element_v16f32_#Index : Insert_Element <
1855 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
1859 def : BitConvert <i32, f32, SReg_32>;
1860 def : BitConvert <i32, f32, VReg_32>;
1862 def : BitConvert <f32, i32, SReg_32>;
1863 def : BitConvert <f32, i32, VReg_32>;
1865 def : BitConvert <i64, f64, VReg_64>;
1867 def : BitConvert <f64, i64, VReg_64>;
1869 def : BitConvert <v2f32, v2i32, VReg_64>;
1870 def : BitConvert <v2i32, v2f32, VReg_64>;
1871 def : BitConvert <v2i32, i64, VReg_64>;
1872 def : BitConvert <i64, v2i32, VReg_64>;
1874 def : BitConvert <v4f32, v4i32, VReg_128>;
1875 def : BitConvert <v4i32, v4f32, VReg_128>;
1877 def : BitConvert <v8f32, v8i32, SReg_256>;
1878 def : BitConvert <v8i32, v8f32, SReg_256>;
1879 def : BitConvert <v8i32, v32i8, SReg_256>;
1880 def : BitConvert <v32i8, v8i32, SReg_256>;
1881 def : BitConvert <v8i32, v32i8, VReg_256>;
1882 def : BitConvert <v8i32, v8f32, VReg_256>;
1883 def : BitConvert <v8f32, v8i32, VReg_256>;
1884 def : BitConvert <v32i8, v8i32, VReg_256>;
1886 def : BitConvert <v16i32, v16f32, VReg_512>;
1887 def : BitConvert <v16f32, v16i32, VReg_512>;
1889 /********** =================== **********/
1890 /********** Src & Dst modifiers **********/
1891 /********** =================== **********/
1893 def FCLAMP_SI : AMDGPUShaderInst <
1894 (outs VReg_32:$dst),
1895 (ins VSrc_32:$src0),
1896 "FCLAMP_SI $dst, $src0",
1899 let usesCustomInserter = 1;
1903 (int_AMDIL_clamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)),
1904 (FCLAMP_SI f32:$src)
1907 /********** ================================ **********/
1908 /********** Floating point absolute/negative **********/
1909 /********** ================================ **********/
1911 // Manipulate the sign bit directly, as e.g. using the source negation modifier
1912 // in V_ADD_F32_e64 $src, 0, [...] does not result in -0.0 for $src == +0.0,
1913 // breaking the piglit *s-floatBitsToInt-neg* tests
1915 // TODO: Look into not implementing isFNegFree/isFAbsFree for SI, and possibly
1916 // removing these patterns
1919 (fneg (fabs f32:$src)),
1920 (V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
1923 def FABS_SI : AMDGPUShaderInst <
1924 (outs VReg_32:$dst),
1925 (ins VSrc_32:$src0),
1926 "FABS_SI $dst, $src0",
1929 let usesCustomInserter = 1;
1937 def FNEG_SI : AMDGPUShaderInst <
1938 (outs VReg_32:$dst),
1939 (ins VSrc_32:$src0),
1940 "FNEG_SI $dst, $src0",
1943 let usesCustomInserter = 1;
1951 /********** ================== **********/
1952 /********** Immediate Patterns **********/
1953 /********** ================== **********/
1956 (SGPRImm<(i32 imm)>:$imm),
1957 (S_MOV_B32 imm:$imm)
1961 (SGPRImm<(f32 fpimm)>:$imm),
1962 (S_MOV_B32 fpimm:$imm)
1967 (V_MOV_B32_e32 imm:$imm)
1972 (V_MOV_B32_e32 fpimm:$imm)
1976 (i64 InlineImm<i64>:$imm),
1977 (S_MOV_B64 InlineImm<i64>:$imm)
1980 /********** ===================== **********/
1981 /********** Interpolation Paterns **********/
1982 /********** ===================== **********/
1985 (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params),
1986 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, $params)
1990 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, v2i32:$ij),
1991 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0),
1992 imm:$attr_chan, imm:$attr, i32:$params),
1993 (EXTRACT_SUBREG $ij, sub1),
1994 imm:$attr_chan, imm:$attr, $params)
1997 /********** ================== **********/
1998 /********** Intrinsic Patterns **********/
1999 /********** ================== **********/
2001 /* llvm.AMDGPU.pow */
2002 def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>;
2005 (int_AMDGPU_div f32:$src0, f32:$src1),
2006 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1))
2010 (fdiv f32:$src0, f32:$src1),
2011 (V_MUL_F32_e32 $src0, (V_RCP_F32_e32 $src1))
2015 (fdiv f64:$src0, f64:$src1),
2016 (V_MUL_F64 $src0, (V_RCP_F64_e32 $src1), (i64 0))
2021 (V_COS_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
2026 (V_SIN_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
2030 (int_AMDGPU_cube v4f32:$src),
2031 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2032 (V_CUBETC_F32 (EXTRACT_SUBREG $src, sub0),
2033 (EXTRACT_SUBREG $src, sub1),
2034 (EXTRACT_SUBREG $src, sub2)),
2036 (V_CUBESC_F32 (EXTRACT_SUBREG $src, sub0),
2037 (EXTRACT_SUBREG $src, sub1),
2038 (EXTRACT_SUBREG $src, sub2)),
2040 (V_CUBEMA_F32 (EXTRACT_SUBREG $src, sub0),
2041 (EXTRACT_SUBREG $src, sub1),
2042 (EXTRACT_SUBREG $src, sub2)),
2044 (V_CUBEID_F32 (EXTRACT_SUBREG $src, sub0),
2045 (EXTRACT_SUBREG $src, sub1),
2046 (EXTRACT_SUBREG $src, sub2)),
2051 (i32 (sext i1:$src0)),
2052 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
2055 class Ext32Pat <SDNode ext> : Pat <
2056 (i32 (ext i1:$src0)),
2057 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0)
2060 def : Ext32Pat <zext>;
2061 def : Ext32Pat <anyext>;
2063 // Offset in an 32Bit VGPR
2065 (SIload_constant v4i32:$sbase, i32:$voff),
2066 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0)
2069 // The multiplication scales from [0,1] to the unsigned integer range
2071 (AMDGPUurecip i32:$src0),
2073 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1,
2074 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
2079 (V_MBCNT_HI_U32_B32_e32 0xffffffff,
2080 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0, 0, 0))
2083 //===----------------------------------------------------------------------===//
2085 //===----------------------------------------------------------------------===//
2087 def : IMad24Pat<V_MAD_I32_I24>;
2088 def : UMad24Pat<V_MAD_U32_U24>;
2091 (fadd f64:$src0, f64:$src1),
2092 (V_ADD_F64 $src0, $src1, (i64 0))
2096 (fmul f64:$src0, f64:$src1),
2097 (V_MUL_F64 $src0, $src1, (i64 0))
2101 (mul i32:$src0, i32:$src1),
2102 (V_MUL_LO_I32 $src0, $src1, (i32 0))
2106 (mulhu i32:$src0, i32:$src1),
2107 (V_MUL_HI_U32 $src0, $src1, (i32 0))
2111 (mulhs i32:$src0, i32:$src1),
2112 (V_MUL_HI_I32 $src0, $src1, (i32 0))
2115 defm : BFIPatterns <V_BFI_B32>;
2116 def : ROTRPattern <V_ALIGNBIT_B32>;
2118 /********** ======================= **********/
2119 /********** Load/Store Patterns **********/
2120 /********** ======================= **********/
2122 multiclass DSReadPat <DS inst, ValueType vt, PatFrag frag> {
2124 (vt (frag (add i32:$ptr, (i32 IMM16bit:$offset)))),
2125 (inst (i1 0), $ptr, (as_i16imm $offset))
2130 (vt (inst 0, $src0, 0))
2134 defm : DSReadPat <DS_READ_I8, i32, sextloadi8_local>;
2135 defm : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>;
2136 defm : DSReadPat <DS_READ_I16, i32, sextloadi16_local>;
2137 defm : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>;
2138 defm : DSReadPat <DS_READ_B32, i32, local_load>;
2139 defm : DSReadPat <DS_READ_B64, i64, local_load>;
2141 multiclass DSWritePat <DS inst, ValueType vt, PatFrag frag> {
2143 (frag vt:$value, (add i32:$ptr, (i32 IMM16bit:$offset))),
2144 (inst (i1 0), $ptr, $value, (as_i16imm $offset))
2148 (frag vt:$val, i32:$ptr),
2149 (inst 0, $ptr, $val, 0)
2153 defm : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>;
2154 defm : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>;
2155 defm : DSWritePat <DS_WRITE_B32, i32, local_store>;
2156 defm : DSWritePat <DS_WRITE_B64, i64, local_store>;
2158 def : Pat <(atomic_load_add_local i32:$ptr, i32:$val),
2159 (DS_ADD_U32_RTN 0, $ptr, $val, 0)>;
2161 def : Pat <(atomic_load_sub_local i32:$ptr, i32:$val),
2162 (DS_SUB_U32_RTN 0, $ptr, $val, 0)>;
2164 //===----------------------------------------------------------------------===//
2166 //===----------------------------------------------------------------------===//
2168 multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
2169 PatFrag global_ld, PatFrag constant_ld> {
2171 (vt (global_ld (mubuf_vaddr_offset i64:$ptr, i64:$offset, IMM12bit:$imm_offset))),
2172 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, (as_i16imm $imm_offset))
2176 (vt (global_ld (add i64:$ptr, (i64 IMM12bit:$offset)))),
2177 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset))
2181 (vt (global_ld i64:$ptr)),
2182 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, 0)
2186 (vt (global_ld (add i64:$ptr, i64:$offset))),
2187 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0)
2191 (vt (constant_ld (add i64:$ptr, i64:$offset))),
2192 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0)
2196 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32,
2197 sextloadi8_global, sextloadi8_constant>;
2198 defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32,
2199 az_extloadi8_global, az_extloadi8_constant>;
2200 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32,
2201 sextloadi16_global, sextloadi16_constant>;
2202 defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32,
2203 az_extloadi16_global, az_extloadi16_constant>;
2204 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32,
2205 global_load, constant_load>;
2206 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64,
2207 global_load, constant_load>;
2208 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64,
2209 az_extloadi32_global, az_extloadi32_constant>;
2210 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32,
2211 global_load, constant_load>;
2212 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32,
2213 global_load, constant_load>;
2215 multiclass MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> {
2218 (st vt:$value, (mubuf_vaddr_offset i64:$ptr, i64:$offset, IMM12bit:$imm_offset)),
2219 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, (as_i16imm $imm_offset))
2223 (st vt:$value, (add i64:$ptr, IMM12bit:$offset)),
2224 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset))
2228 (st vt:$value, i64:$ptr),
2229 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, 0)
2233 (st vt:$value, (add i64:$ptr, i64:$offset)),
2234 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, 0)
2238 defm : MUBUFStore_Pattern <BUFFER_STORE_BYTE, i32, truncstorei8_global>;
2239 defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT, i32, truncstorei16_global>;
2240 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORD, i32, global_store>;
2241 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, i64, global_store>;
2242 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, v2i32, global_store>;
2243 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4, v4i32, global_store>;
2245 // BUFFER_LOAD_DWORD*, addr64=0
2246 multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen,
2250 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2251 imm:$offset, 0, 0, imm:$glc, imm:$slc,
2253 (offset $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2254 (as_i1imm $slc), (as_i1imm $tfe))
2258 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2259 imm, 1, 0, imm:$glc, imm:$slc,
2261 (offen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
2266 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2267 imm:$offset, 0, 1, imm:$glc, imm:$slc,
2269 (idxen $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2270 (as_i1imm $slc), (as_i1imm $tfe))
2274 (vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset,
2275 imm, 1, 1, imm:$glc, imm:$slc,
2277 (bothen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
2282 defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN,
2283 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
2284 defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN,
2285 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>;
2286 defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN,
2287 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
2289 //===----------------------------------------------------------------------===//
2291 //===----------------------------------------------------------------------===//
2293 // TBUFFER_STORE_FORMAT_*, addr64=0
2294 class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat<
2295 (SItbuffer_store v4i32:$rsrc, vt:$vdata, num_channels, i32:$vaddr,
2296 i32:$soffset, imm:$inst_offset, imm:$dfmt,
2297 imm:$nfmt, imm:$offen, imm:$idxen,
2298 imm:$glc, imm:$slc, imm:$tfe),
2300 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen),
2301 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc,
2302 (as_i1imm $slc), (as_i1imm $tfe), $soffset)
2305 def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>;
2306 def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>;
2307 def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>;
2308 def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>;
2310 let Predicates = [isCI] in {
2312 // Sea island new arithmetic instructinos
2313 let neverHasSideEffects = 1 in {
2314 defm V_TRUNC_F64 : VOP1_64 <0x00000017, "V_TRUNC_F64",
2315 [(set f64:$dst, (ftrunc f64:$src0))]
2317 defm V_CEIL_F64 : VOP1_64 <0x00000018, "V_CEIL_F64",
2318 [(set f64:$dst, (fceil f64:$src0))]
2320 defm V_FLOOR_F64 : VOP1_64 <0x0000001A, "V_FLOOR_F64",
2321 [(set f64:$dst, (ffloor f64:$src0))]
2323 defm V_RNDNE_F64 : VOP1_64 <0x00000019, "V_RNDNE_F64",
2324 [(set f64:$dst, (frint f64:$src0))]
2327 defm V_QSAD_PK_U16_U8 : VOP3_32 <0x00000173, "V_QSAD_PK_U16_U8", []>;
2328 defm V_MQSAD_U16_U8 : VOP3_32 <0x000000172, "V_MQSAD_U16_U8", []>;
2329 defm V_MQSAD_U32_U8 : VOP3_32 <0x00000175, "V_MQSAD_U32_U8", []>;
2330 def V_MAD_U64_U32 : VOP3_64 <0x00000176, "V_MAD_U64_U32", []>;
2332 // XXX - Does this set VCC?
2333 def V_MAD_I64_I32 : VOP3_64 <0x00000177, "V_MAD_I64_I32", []>;
2334 } // End neverHasSideEffects = 1
2336 // Remaining instructions:
2338 // S_CBRANCH_CDBGUSER
2339 // S_CBRANCH_CDBGSYS
2340 // S_CBRANCH_CDBGSYS_OR_USER
2341 // S_CBRANCH_CDBGSYS_AND_USER
2346 // DS_GWS_SEMA_RELEASE_ALL
2348 // DS_CNDXCHG32_RTN_B64
2351 // DS_CONDXCHG32_RTN_B128
2354 // BUFFER_LOAD_DWORDX3
2355 // BUFFER_STORE_DWORDX3
2357 } // End Predicates = [isCI]
2360 /********** ====================== **********/
2361 /********** Indirect adressing **********/
2362 /********** ====================== **********/
2364 multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, SI_INDIRECT_DST IndDst> {
2366 // 1. Extract with offset
2368 (vector_extract vt:$vec, (add i32:$idx, imm:$off)),
2369 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off))
2372 // 2. Extract without offset
2374 (vector_extract vt:$vec, i32:$idx),
2375 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0))
2378 // 3. Insert with offset
2380 (vector_insert vt:$vec, eltvt:$val, (add i32:$idx, imm:$off)),
2381 (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val)
2384 // 4. Insert without offset
2386 (vector_insert vt:$vec, eltvt:$val, i32:$idx),
2387 (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val)
2391 defm : SI_INDIRECT_Pattern <v2f32, f32, SI_INDIRECT_DST_V2>;
2392 defm : SI_INDIRECT_Pattern <v4f32, f32, SI_INDIRECT_DST_V4>;
2393 defm : SI_INDIRECT_Pattern <v8f32, f32, SI_INDIRECT_DST_V8>;
2394 defm : SI_INDIRECT_Pattern <v16f32, f32, SI_INDIRECT_DST_V16>;
2396 defm : SI_INDIRECT_Pattern <v2i32, i32, SI_INDIRECT_DST_V2>;
2397 defm : SI_INDIRECT_Pattern <v4i32, i32, SI_INDIRECT_DST_V4>;
2398 defm : SI_INDIRECT_Pattern <v8i32, i32, SI_INDIRECT_DST_V8>;
2399 defm : SI_INDIRECT_Pattern <v16i32, i32, SI_INDIRECT_DST_V16>;
2401 //===----------------------------------------------------------------------===//
2402 // Conversion Patterns
2403 //===----------------------------------------------------------------------===//
2405 def : Pat<(i32 (sext_inreg i32:$src, i1)),
2406 (S_BFE_I32 i32:$src, 65536)>; // 0 | 1 << 16
2408 // TODO: Match 64-bit BFE. SI has a 64-bit BFE, but it's scalar only so it
2409 // might not be worth the effort, and will need to expand to shifts when
2410 // fixing SGPR copies.
2412 // Handle sext_inreg in i64
2414 (i64 (sext_inreg i64:$src, i1)),
2415 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2416 (S_BFE_I32 (EXTRACT_SUBREG i64:$src, sub0), 65536), sub0), // 0 | 1 << 16
2417 (S_MOV_B32 -1), sub1)
2421 (i64 (sext_inreg i64:$src, i8)),
2422 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2423 (S_SEXT_I32_I8 (EXTRACT_SUBREG i64:$src, sub0)), sub0),
2424 (S_MOV_B32 -1), sub1)
2428 (i64 (sext_inreg i64:$src, i16)),
2429 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2430 (S_SEXT_I32_I16 (EXTRACT_SUBREG i64:$src, sub0)), sub0),
2431 (S_MOV_B32 -1), sub1)
2435 (f32 (sint_to_fp i1:$src)),
2436 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_NEG_ONE, $src)
2440 (f32 (uint_to_fp i1:$src)),
2441 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_ONE, $src)
2445 (f64 (sint_to_fp i1:$src)),
2446 (V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src))
2450 (f64 (uint_to_fp i1:$src)),
2451 (V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src))
2454 //===----------------------------------------------------------------------===//
2455 // Miscellaneous Patterns
2456 //===----------------------------------------------------------------------===//
2459 (i32 (trunc i64:$a)),
2460 (EXTRACT_SUBREG $a, sub0)
2464 (i1 (trunc i32:$a)),
2465 (V_CMP_EQ_I32_e64 (V_AND_B32_e32 (i32 1), $a), 1)
2468 // V_ADD_I32_e32/S_ADD_I32 produces carry in VCC/SCC. For the vector
2469 // case, the sgpr-copies pass will fix this to use the vector version.
2471 (i32 (addc i32:$src0, i32:$src1)),
2472 (S_ADD_I32 $src0, $src1)
2475 //============================================================================//
2476 // Miscellaneous Optimization Patterns
2477 //============================================================================//
2479 def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e32>;
2481 } // End isSI predicate