1 //===-- SIInstructions.td - SI Instruction Defintions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This file was originally auto-generated from a GPU register header file and
10 // all the instruction definitions were originally commented out. Instructions
11 // that are not yet supported remain commented out.
12 //===----------------------------------------------------------------------===//
19 def INTERP : InterpSlots;
21 def InterpSlot : Operand<i32> {
22 let PrintMethod = "printInterpSlot";
25 def SendMsgImm : Operand<i32> {
26 let PrintMethod = "printSendMsg";
29 def isSI : Predicate<"Subtarget.getGeneration() "
30 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">;
32 def isCI : Predicate<"Subtarget.getGeneration() "
33 ">= AMDGPUSubtarget::SEA_ISLANDS">;
35 def isCFDepth0 : Predicate<"isCFDepth0()">;
37 def WAIT_FLAG : InstFlag<"printWaitFlag">;
39 let SubtargetPredicate = isSI in {
40 let OtherPredicates = [isCFDepth0] in {
42 //===----------------------------------------------------------------------===//
44 //===----------------------------------------------------------------------===//
48 // We are using the SGPR_32 and not the SReg_32 register class for 32-bit
49 // SMRD instructions, because the SGPR_32 register class does not include M0
50 // and writing to M0 from an SMRD instruction will hang the GPU.
51 defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SGPR_32>;
52 defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>;
53 defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>;
54 defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>;
55 defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>;
57 defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
58 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SGPR_32
61 defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
62 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64
65 defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper <
66 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128
69 defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <
70 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256
73 defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
74 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512
79 //def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>;
80 //def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>;
82 //===----------------------------------------------------------------------===//
84 //===----------------------------------------------------------------------===//
86 let neverHasSideEffects = 1 in {
88 let isMoveImm = 1 in {
89 def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>;
90 def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>;
91 def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>;
92 def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>;
93 } // End isMoveImm = 1
95 def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32",
96 [(set i32:$dst, (not i32:$src0))]
99 def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64",
100 [(set i64:$dst, (not i64:$src0))]
102 def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>;
103 def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>;
104 def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>;
105 def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>;
106 } // End neverHasSideEffects = 1
108 ////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>;
109 ////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>;
110 def S_BCNT1_I32_B32 : SOP1_32 <0x0000000f, "S_BCNT1_I32_B32",
111 [(set i32:$dst, (ctpop i32:$src0))]
113 def S_BCNT1_I32_B64 : SOP1_32_64 <0x00000010, "S_BCNT1_I32_B64", []>;
115 ////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>;
116 ////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>;
117 ////def S_FF1_I32_B32 : SOP1_FF1 <0x00000013, "S_FF1_I32_B32", []>;
118 ////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>;
119 //def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", []>;
120 //def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>;
121 def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>;
122 //def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>;
123 def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8",
124 [(set i32:$dst, (sext_inreg i32:$src0, i8))]
126 def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16",
127 [(set i32:$dst, (sext_inreg i32:$src0, i16))]
130 ////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>;
131 ////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>;
132 ////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>;
133 ////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>;
134 def S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>;
135 def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>;
136 def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>;
137 def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>;
139 let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in {
141 def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>;
142 def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>;
143 def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>;
144 def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>;
145 def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>;
146 def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>;
147 def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>;
148 def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>;
150 } // End hasSideEffects = 1
152 def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>;
153 def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>;
154 def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>;
155 def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>;
156 def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>;
157 def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>;
158 //def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>;
159 def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>;
160 def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>;
161 def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>;
163 //===----------------------------------------------------------------------===//
165 //===----------------------------------------------------------------------===//
167 let Defs = [SCC] in { // Carry out goes to SCC
168 let isCommutable = 1 in {
169 def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>;
170 def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32",
171 [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))]
173 } // End isCommutable = 1
175 def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>;
176 def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32",
177 [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))]
180 let Uses = [SCC] in { // Carry in comes from SCC
181 let isCommutable = 1 in {
182 def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32",
183 [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
184 } // End isCommutable = 1
186 def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32",
187 [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
188 } // End Uses = [SCC]
189 } // End Defs = [SCC]
191 def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32",
192 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]
194 def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32",
195 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]
197 def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32",
198 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]
200 def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32",
201 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]
204 def S_CSELECT_B32 : SOP2 <
205 0x0000000a, (outs SReg_32:$dst),
206 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32",
210 def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>;
212 def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32",
213 [(set i32:$dst, (and i32:$src0, i32:$src1))]
216 def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64",
217 [(set i64:$dst, (and i64:$src0, i64:$src1))]
220 def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32",
221 [(set i32:$dst, (or i32:$src0, i32:$src1))]
224 def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64",
225 [(set i64:$dst, (or i64:$src0, i64:$src1))]
228 def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32",
229 [(set i32:$dst, (xor i32:$src0, i32:$src1))]
232 def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64",
233 [(set i64:$dst, (xor i64:$src0, i64:$src1))]
235 def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>;
236 def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>;
237 def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>;
238 def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>;
239 def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>;
240 def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>;
241 def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>;
242 def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>;
243 def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>;
244 def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>;
246 // Use added complexity so these patterns are preferred to the VALU patterns.
247 let AddedComplexity = 1 in {
249 def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32",
250 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
252 def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "S_LSHL_B64",
253 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
255 def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32",
256 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
258 def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "S_LSHR_B64",
259 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
261 def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32",
262 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
264 def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64",
265 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
268 } // End AddedComplexity = 1
270 def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>;
271 def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>;
272 def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>;
273 def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>;
274 def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>;
275 def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>;
276 def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>;
277 //def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>;
278 def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>;
280 //===----------------------------------------------------------------------===//
282 //===----------------------------------------------------------------------===//
284 def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32">;
285 def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32">;
286 def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32">;
287 def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32">;
288 def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32">;
289 def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32">;
290 def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32">;
291 def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32">;
292 def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32">;
293 def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32">;
294 def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32">;
295 def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32">;
296 ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>;
297 ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>;
298 ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>;
299 ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>;
300 //def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>;
302 //===----------------------------------------------------------------------===//
304 //===----------------------------------------------------------------------===//
306 def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>;
307 def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>;
310 This instruction is disabled for now until we can figure out how to teach
311 the instruction selector to correctly use the S_CMP* vs V_CMP*
314 When this instruction is enabled the code generator sometimes produces this
317 SCC = S_CMPK_EQ_I32 SGPR0, imm
319 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
321 def S_CMPK_EQ_I32 : SOPK <
322 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1),
324 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))]
328 let isCompare = 1 in {
329 def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>;
330 def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>;
331 def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>;
332 def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>;
333 def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>;
334 def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>;
335 def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>;
336 def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>;
337 def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>;
338 def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>;
339 def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>;
340 } // End isCompare = 1
342 let Defs = [SCC], isCommutable = 1 in {
343 def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>;
344 def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>;
347 //def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>;
348 def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>;
349 def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>;
350 def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>;
351 //def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>;
352 //def EXP : EXP_ <0x00000000, "EXP", []>;
354 } // End let OtherPredicates = [isCFDepth0]
356 //===----------------------------------------------------------------------===//
358 //===----------------------------------------------------------------------===//
360 def S_NOP : SOPP <0x00000000, (ins i16imm:$SIMM16), "S_NOP $SIMM16", []>;
362 let isTerminator = 1 in {
364 def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM",
371 let isBranch = 1 in {
372 def S_BRANCH : SOPP <
373 0x00000002, (ins brtarget:$target), "S_BRANCH $target",
378 let DisableEncoding = "$scc" in {
379 def S_CBRANCH_SCC0 : SOPP <
380 0x00000004, (ins brtarget:$target, SCCReg:$scc),
381 "S_CBRANCH_SCC0 $target", []
383 def S_CBRANCH_SCC1 : SOPP <
384 0x00000005, (ins brtarget:$target, SCCReg:$scc),
385 "S_CBRANCH_SCC1 $target",
388 } // End DisableEncoding = "$scc"
390 def S_CBRANCH_VCCZ : SOPP <
391 0x00000006, (ins brtarget:$target, VCCReg:$vcc),
392 "S_CBRANCH_VCCZ $target",
395 def S_CBRANCH_VCCNZ : SOPP <
396 0x00000007, (ins brtarget:$target, VCCReg:$vcc),
397 "S_CBRANCH_VCCNZ $target",
401 let DisableEncoding = "$exec" in {
402 def S_CBRANCH_EXECZ : SOPP <
403 0x00000008, (ins brtarget:$target, EXECReg:$exec),
404 "S_CBRANCH_EXECZ $target",
407 def S_CBRANCH_EXECNZ : SOPP <
408 0x00000009, (ins brtarget:$target, EXECReg:$exec),
409 "S_CBRANCH_EXECNZ $target",
412 } // End DisableEncoding = "$exec"
415 } // End isBranch = 1
416 } // End isTerminator = 1
418 let hasSideEffects = 1 in {
419 def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER",
420 [(int_AMDGPU_barrier_local)]
429 def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16",
432 //def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>;
433 //def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>;
434 //def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>;
436 let Uses = [EXEC] in {
437 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "S_SENDMSG $simm16",
438 [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)]
440 let DisableEncoding = "$m0";
442 } // End Uses = [EXEC]
444 //def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>;
445 //def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>;
446 //def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>;
447 //def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>;
448 //def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>;
449 //def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
450 } // End hasSideEffects
452 //===----------------------------------------------------------------------===//
454 //===----------------------------------------------------------------------===//
456 let isCompare = 1 in {
458 defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">;
459 defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_OLT>;
460 defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", f32, COND_OEQ>;
461 defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", f32, COND_OLE>;
462 defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", f32, COND_OGT>;
463 defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32">;
464 defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", f32, COND_OGE>;
465 defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32", f32, COND_O>;
466 defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32", f32, COND_UO>;
467 defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32">;
468 defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32">;
469 defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32">;
470 defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32">;
471 defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", f32, COND_UNE>;
472 defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">;
473 defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">;
475 let hasSideEffects = 1, Defs = [EXEC] in {
477 defm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32">;
478 defm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32">;
479 defm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32">;
480 defm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32">;
481 defm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32">;
482 defm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32">;
483 defm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32">;
484 defm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32">;
485 defm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32">;
486 defm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32">;
487 defm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32">;
488 defm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32">;
489 defm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32">;
490 defm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32">;
491 defm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32">;
492 defm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32">;
494 } // End hasSideEffects = 1, Defs = [EXEC]
496 defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">;
497 defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64", f64, COND_OLT>;
498 defm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64", f64, COND_OEQ>;
499 defm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64", f64, COND_OLE>;
500 defm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64", f64, COND_OGT>;
501 defm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64">;
502 defm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64", f64, COND_OGE>;
503 defm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64", f64, COND_O>;
504 defm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64", f64, COND_UO>;
505 defm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64">;
506 defm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64">;
507 defm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64">;
508 defm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64">;
509 defm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64", f64, COND_UNE>;
510 defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">;
511 defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">;
513 let hasSideEffects = 1, Defs = [EXEC] in {
515 defm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64">;
516 defm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64">;
517 defm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64">;
518 defm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64">;
519 defm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64">;
520 defm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64">;
521 defm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64">;
522 defm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64">;
523 defm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64">;
524 defm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64">;
525 defm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64">;
526 defm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64">;
527 defm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64">;
528 defm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64">;
529 defm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64">;
530 defm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64">;
532 } // End hasSideEffects = 1, Defs = [EXEC]
534 defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">;
535 defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">;
536 defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32">;
537 defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32">;
538 defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32">;
539 defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32">;
540 defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32">;
541 defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32">;
542 defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32">;
543 defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32">;
544 defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32">;
545 defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32">;
546 defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32">;
547 defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">;
548 defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">;
549 defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">;
551 let hasSideEffects = 1, Defs = [EXEC] in {
553 defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32">;
554 defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32">;
555 defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32">;
556 defm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32">;
557 defm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32">;
558 defm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32">;
559 defm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32">;
560 defm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32">;
561 defm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32">;
562 defm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32">;
563 defm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32">;
564 defm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32">;
565 defm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32">;
566 defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32">;
567 defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32">;
568 defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32">;
570 } // End hasSideEffects = 1, Defs = [EXEC]
572 defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">;
573 defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">;
574 defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">;
575 defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64">;
576 defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64">;
577 defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64">;
578 defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64">;
579 defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64">;
580 defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64">;
581 defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64">;
582 defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64">;
583 defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64">;
584 defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64">;
585 defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">;
586 defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">;
587 defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">;
589 let hasSideEffects = 1, Defs = [EXEC] in {
591 defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">;
592 defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">;
593 defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">;
594 defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64">;
595 defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64">;
596 defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64">;
597 defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64">;
598 defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64">;
599 defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64">;
600 defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64">;
601 defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64">;
602 defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64">;
603 defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64">;
604 defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">;
605 defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">;
606 defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">;
608 } // End hasSideEffects = 1, Defs = [EXEC]
610 defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">;
611 defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_SLT>;
612 defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>;
613 defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", i32, COND_SLE>;
614 defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", i32, COND_SGT>;
615 defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", i32, COND_NE>;
616 defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_SGE>;
617 defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">;
619 let hasSideEffects = 1, Defs = [EXEC] in {
621 defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32">;
622 defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32">;
623 defm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32">;
624 defm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32">;
625 defm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32">;
626 defm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32">;
627 defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32">;
628 defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32">;
630 } // End hasSideEffects = 1, Defs = [EXEC]
632 defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">;
633 defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64", i64, COND_SLT>;
634 defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64", i64, COND_EQ>;
635 defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64", i64, COND_SLE>;
636 defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64", i64, COND_SGT>;
637 defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64", i64, COND_NE>;
638 defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64", i64, COND_SGE>;
639 defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">;
641 let hasSideEffects = 1, Defs = [EXEC] in {
643 defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64">;
644 defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64">;
645 defm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64">;
646 defm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64">;
647 defm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64">;
648 defm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64">;
649 defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64">;
650 defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64">;
652 } // End hasSideEffects = 1, Defs = [EXEC]
654 defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">;
655 defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32", i32, COND_ULT>;
656 defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32", i32, COND_EQ>;
657 defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32", i32, COND_ULE>;
658 defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32", i32, COND_UGT>;
659 defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32", i32, COND_NE>;
660 defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32", i32, COND_UGE>;
661 defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">;
663 let hasSideEffects = 1, Defs = [EXEC] in {
665 defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32">;
666 defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32">;
667 defm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32">;
668 defm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32">;
669 defm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32">;
670 defm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32">;
671 defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32">;
672 defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32">;
674 } // End hasSideEffects = 1, Defs = [EXEC]
676 defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">;
677 defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64", i64, COND_ULT>;
678 defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64", i64, COND_EQ>;
679 defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64", i64, COND_ULE>;
680 defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64", i64, COND_UGT>;
681 defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64", i64, COND_NE>;
682 defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64", i64, COND_UGE>;
683 defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">;
685 let hasSideEffects = 1, Defs = [EXEC] in {
687 defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64">;
688 defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64">;
689 defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64">;
690 defm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64">;
691 defm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64">;
692 defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64">;
693 defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64">;
694 defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64">;
696 } // End hasSideEffects = 1, Defs = [EXEC]
698 defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">;
700 let hasSideEffects = 1, Defs = [EXEC] in {
701 defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">;
702 } // End hasSideEffects = 1, Defs = [EXEC]
704 defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">;
706 let hasSideEffects = 1, Defs = [EXEC] in {
707 defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">;
708 } // End hasSideEffects = 1, Defs = [EXEC]
710 } // End isCompare = 1
712 //===----------------------------------------------------------------------===//
714 //===----------------------------------------------------------------------===//
716 def DS_ADD_U32_RTN : DS_1A1D_RET <0x20, "DS_ADD_U32_RTN", VReg_32>;
717 def DS_SUB_U32_RTN : DS_1A1D_RET <0x21, "DS_SUB_U32_RTN", VReg_32>;
718 def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>;
719 def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "DS_WRITE_B8", VReg_32>;
720 def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "DS_WRITE_B16", VReg_32>;
721 def DS_WRITE_B64 : DS_Store_Helper <0x00000004d, "DS_WRITE_B64", VReg_64>;
723 def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>;
724 def DS_READ_I8 : DS_Load_Helper <0x00000039, "DS_READ_I8", VReg_32>;
725 def DS_READ_U8 : DS_Load_Helper <0x0000003a, "DS_READ_U8", VReg_32>;
726 def DS_READ_I16 : DS_Load_Helper <0x0000003b, "DS_READ_I16", VReg_32>;
727 def DS_READ_U16 : DS_Load_Helper <0x0000003c, "DS_READ_U16", VReg_32>;
728 def DS_READ_B64 : DS_Load_Helper <0x00000076, "DS_READ_B64", VReg_64>;
731 def DS_WRITE2_B32 : DS_Load2_Helper <0x0000000E, "DS_WRITE2_B32", VReg_64>;
732 def DS_WRITE2_B64 : DS_Load2_Helper <0x0000004E, "DS_WRITE2_B64", VReg_128>;
734 def DS_READ2_B32 : DS_Load2_Helper <0x00000037, "DS_READ2_B32", VReg_64>;
735 def DS_READ2_B64 : DS_Load2_Helper <0x00000075, "DS_READ2_B64", VReg_128>;
737 // TODO: DS_READ2ST64_B32, DS_READ2ST64_B64,
738 // DS_WRITE2ST64_B32, DS_WRITE2ST64_B64
740 //===----------------------------------------------------------------------===//
741 // MUBUF Instructions
742 //===----------------------------------------------------------------------===//
744 //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>;
745 //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>;
746 //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>;
747 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>;
748 //def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>;
749 //def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>;
750 //def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>;
751 //def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>;
752 defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <0x00000008, "BUFFER_LOAD_UBYTE", VReg_32>;
753 defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <0x00000009, "BUFFER_LOAD_SBYTE", VReg_32>;
754 defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <0x0000000a, "BUFFER_LOAD_USHORT", VReg_32>;
755 defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32>;
756 defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <0x0000000c, "BUFFER_LOAD_DWORD", VReg_32>;
757 defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64>;
758 defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128>;
760 def BUFFER_STORE_BYTE : MUBUF_Store_Helper <
761 0x00000018, "BUFFER_STORE_BYTE", VReg_32
764 def BUFFER_STORE_SHORT : MUBUF_Store_Helper <
765 0x0000001a, "BUFFER_STORE_SHORT", VReg_32
768 def BUFFER_STORE_DWORD : MUBUF_Store_Helper <
769 0x0000001c, "BUFFER_STORE_DWORD", VReg_32
772 def BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper <
773 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64
776 def BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper <
777 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128
779 //def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>;
780 //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>;
781 //def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>;
782 //def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>;
783 //def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>;
784 //def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>;
785 //def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>;
786 //def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>;
787 //def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>;
788 //def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>;
789 //def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>;
790 //def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>;
791 //def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>;
792 //def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>;
793 //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>;
794 //def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>;
795 //def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>;
796 //def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>;
797 //def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>;
798 //def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>;
799 //def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>;
800 //def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>;
801 //def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>;
802 //def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>;
803 //def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>;
804 //def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>;
805 //def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>;
806 //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>;
807 //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>;
808 //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>;
809 //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>;
810 //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>;
811 //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>;
812 //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>;
813 //def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>;
814 //def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>;
816 //===----------------------------------------------------------------------===//
817 // MTBUF Instructions
818 //===----------------------------------------------------------------------===//
820 //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>;
821 //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>;
822 //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>;
823 def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>;
824 def TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "TBUFFER_STORE_FORMAT_X", VReg_32>;
825 def TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FORMAT_XY", VReg_64>;
826 def TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>;
827 def TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>;
829 //===----------------------------------------------------------------------===//
831 //===----------------------------------------------------------------------===//
833 defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "IMAGE_LOAD">;
834 defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "IMAGE_LOAD_MIP">;
835 //def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>;
836 //def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>;
837 //def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>;
838 //def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>;
839 //def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>;
840 //def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>;
841 //def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>;
842 //def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>;
843 defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "IMAGE_GET_RESINFO">;
844 //def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>;
845 //def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>;
846 //def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>;
847 //def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>;
848 //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>;
849 //def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>;
850 //def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>;
851 //def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>;
852 //def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>;
853 //def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>;
854 //def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>;
855 //def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>;
856 //def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>;
857 //def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>;
858 //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>;
859 //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>;
860 //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>;
861 defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">;
862 //def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>;
863 defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">;
864 //def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>;
865 defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">;
866 defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">;
867 //def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>;
868 //def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>;
869 defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">;
870 //def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>;
871 defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">;
872 //def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>;
873 defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">;
874 defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">;
875 //def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>;
876 //def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>;
877 //def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>;
878 //def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>;
879 //def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>;
880 //def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>;
881 //def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>;
882 //def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>;
883 //def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>;
884 //def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>;
885 //def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>;
886 //def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>;
887 //def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>;
888 //def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>;
889 //def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>;
890 //def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>;
891 //def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>;
892 //def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>;
893 //def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>;
894 //def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>;
895 //def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>;
896 //def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>;
897 //def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>;
898 //def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>;
899 //def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>;
900 //def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>;
901 //def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>;
902 //def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>;
903 //def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>;
904 //def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>;
905 //def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>;
906 //def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>;
907 //def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>;
908 //def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>;
909 //def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>;
910 //def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>;
911 //def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>;
912 //def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>;
913 //def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>;
914 //def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>;
915 //def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>;
916 //def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>;
917 //def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>;
918 //def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>;
919 //def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>;
920 //def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>;
921 //def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>;
922 //def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>;
923 //def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>;
924 //def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>;
925 //def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>;
926 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>;
927 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>;
929 //===----------------------------------------------------------------------===//
931 //===----------------------------------------------------------------------===//
933 //def V_NOP : VOP1_ <0x00000000, "V_NOP", []>;
935 let neverHasSideEffects = 1, isMoveImm = 1 in {
936 defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>;
937 } // End neverHasSideEffects = 1, isMoveImm = 1
939 let Uses = [EXEC] in {
941 def V_READFIRSTLANE_B32 : VOP1 <
943 (outs SReg_32:$vdst),
945 "V_READFIRSTLANE_B32 $vdst, $src0",
951 defm V_CVT_I32_F64 : VOP1_32_64 <0x00000003, "V_CVT_I32_F64",
952 [(set i32:$dst, (fp_to_sint f64:$src0))]
954 defm V_CVT_F64_I32 : VOP1_64_32 <0x00000004, "V_CVT_F64_I32",
955 [(set f64:$dst, (sint_to_fp i32:$src0))]
957 defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32",
958 [(set f32:$dst, (sint_to_fp i32:$src0))]
960 defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32",
961 [(set f32:$dst, (uint_to_fp i32:$src0))]
963 defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32",
964 [(set i32:$dst, (fp_to_uint f32:$src0))]
966 defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32",
967 [(set i32:$dst, (fp_to_sint f32:$src0))]
969 defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>;
970 ////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>;
971 //defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>;
972 //defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>;
973 //defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>;
974 //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>;
975 defm V_CVT_F32_F64 : VOP1_32_64 <0x0000000f, "V_CVT_F32_F64",
976 [(set f32:$dst, (fround f64:$src0))]
978 defm V_CVT_F64_F32 : VOP1_64_32 <0x00000010, "V_CVT_F64_F32",
979 [(set f64:$dst, (fextend f32:$src0))]
981 defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0",
982 [(set f32:$dst, (AMDGPUcvt_f32_ubyte0 i32:$src0))]
984 defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1",
985 [(set f32:$dst, (AMDGPUcvt_f32_ubyte1 i32:$src0))]
987 defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2",
988 [(set f32:$dst, (AMDGPUcvt_f32_ubyte2 i32:$src0))]
990 defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3",
991 [(set f32:$dst, (AMDGPUcvt_f32_ubyte3 i32:$src0))]
993 defm V_CVT_U32_F64 : VOP1_32_64 <0x00000015, "V_CVT_U32_F64",
994 [(set i32:$dst, (fp_to_uint f64:$src0))]
996 defm V_CVT_F64_U32 : VOP1_64_32 <0x00000016, "V_CVT_F64_U32",
997 [(set f64:$dst, (uint_to_fp i32:$src0))]
1000 defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32",
1001 [(set f32:$dst, (AMDGPUfract f32:$src0))]
1003 defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32",
1004 [(set f32:$dst, (int_AMDGPU_trunc f32:$src0))]
1006 defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32",
1007 [(set f32:$dst, (fceil f32:$src0))]
1009 defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32",
1010 [(set f32:$dst, (frint f32:$src0))]
1012 defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32",
1013 [(set f32:$dst, (ffloor f32:$src0))]
1015 defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32",
1016 [(set f32:$dst, (fexp2 f32:$src0))]
1018 defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>;
1019 defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32",
1020 [(set f32:$dst, (flog2 f32:$src0))]
1022 defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>;
1023 defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>;
1024 defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32",
1025 [(set f32:$dst, (fdiv FP_ONE, f32:$src0))]
1027 defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>;
1028 defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>;
1029 defm V_RSQ_LEGACY_F32 : VOP1_32 <
1030 0x0000002d, "V_RSQ_LEGACY_F32",
1031 [(set f32:$dst, (int_AMDGPU_rsq f32:$src0))]
1033 defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32",
1034 [(set f32:$dst, (fdiv FP_ONE, (fsqrt f32:$src0)))]
1036 defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64",
1037 [(set f64:$dst, (fdiv FP_ONE, f64:$src0))]
1039 defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>;
1040 defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64",
1041 [(set f64:$dst, (fdiv FP_ONE, (fsqrt f64:$src0)))]
1043 defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>;
1044 defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32",
1045 [(set f32:$dst, (fsqrt f32:$src0))]
1047 defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64",
1048 [(set f64:$dst, (fsqrt f64:$src0))]
1050 defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>;
1051 defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>;
1052 defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>;
1053 defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>;
1054 defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>;
1055 defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>;
1056 defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>;
1057 //defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>;
1058 defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>;
1059 defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>;
1060 //defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>;
1061 defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>;
1062 //def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>;
1063 defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>;
1064 defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>;
1065 defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>;
1068 //===----------------------------------------------------------------------===//
1069 // VINTRP Instructions
1070 //===----------------------------------------------------------------------===//
1072 def V_INTERP_P1_F32 : VINTRP <
1074 (outs VReg_32:$dst),
1075 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1076 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]",
1078 let DisableEncoding = "$m0";
1081 def V_INTERP_P2_F32 : VINTRP <
1083 (outs VReg_32:$dst),
1084 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1085 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]",
1088 let Constraints = "$src0 = $dst";
1089 let DisableEncoding = "$src0,$m0";
1093 def V_INTERP_MOV_F32 : VINTRP <
1095 (outs VReg_32:$dst),
1096 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1097 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]",
1099 let DisableEncoding = "$m0";
1102 //===----------------------------------------------------------------------===//
1103 // VOP2 Instructions
1104 //===----------------------------------------------------------------------===//
1106 def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
1107 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc),
1108 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]",
1111 let DisableEncoding = "$vcc";
1114 def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst),
1115 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2,
1116 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
1117 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg",
1118 [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))]
1120 let src0_modifiers = 0;
1121 let src1_modifiers = 0;
1122 let src2_modifiers = 0;
1125 def V_READLANE_B32 : VOP2 <
1127 (outs SReg_32:$vdst),
1128 (ins VReg_32:$src0, SSrc_32:$vsrc1),
1129 "V_READLANE_B32 $vdst, $src0, $vsrc1",
1133 def V_WRITELANE_B32 : VOP2 <
1135 (outs VReg_32:$vdst),
1136 (ins SReg_32:$src0, SSrc_32:$vsrc1),
1137 "V_WRITELANE_B32 $vdst, $src0, $vsrc1",
1141 let isCommutable = 1 in {
1142 defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32",
1143 [(set f32:$dst, (fadd f32:$src0, f32:$src1))]
1146 defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32",
1147 [(set f32:$dst, (fsub f32:$src0, f32:$src1))]
1149 defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", [], "V_SUB_F32">;
1150 } // End isCommutable = 1
1152 defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>;
1154 let isCommutable = 1 in {
1156 defm V_MUL_LEGACY_F32 : VOP2_32 <
1157 0x00000007, "V_MUL_LEGACY_F32",
1158 [(set f32:$dst, (int_AMDGPU_mul f32:$src0, f32:$src1))]
1161 defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32",
1162 [(set f32:$dst, (fmul f32:$src0, f32:$src1))]
1166 defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24",
1167 [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))]
1169 //defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>;
1170 defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24",
1171 [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))]
1173 //defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>;
1176 defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32",
1177 [(set f32:$dst, (AMDGPUfmin f32:$src0, f32:$src1))]
1180 defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32",
1181 [(set f32:$dst, (AMDGPUfmax f32:$src0, f32:$src1))]
1184 defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>;
1185 defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>;
1186 defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32",
1187 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]>;
1188 defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32",
1189 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]>;
1190 defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32",
1191 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]>;
1192 defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32",
1193 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]>;
1195 defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32",
1196 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
1199 defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">;
1201 defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32",
1202 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
1204 defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">;
1206 let hasPostISelHook = 1 in {
1208 defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32",
1209 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
1213 defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">;
1215 defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32",
1216 [(set i32:$dst, (and i32:$src0, i32:$src1))]>;
1217 defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32",
1218 [(set i32:$dst, (or i32:$src0, i32:$src1))]
1220 defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32",
1221 [(set i32:$dst, (xor i32:$src0, i32:$src1))]
1224 } // End isCommutable = 1
1226 defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32",
1227 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))]>;
1228 defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>;
1229 defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>;
1230 defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>;
1231 defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>;
1232 defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>;
1233 defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>;
1235 let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC
1236 // No patterns so that the scalar instructions are always selected.
1237 // The scalar versions will be replaced with vector when needed later.
1238 defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32",
1239 [(set i32:$dst, (add i32:$src0, i32:$src1))], VSrc_32>;
1240 defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32",
1241 [(set i32:$dst, (sub i32:$src0, i32:$src1))], VSrc_32>;
1242 defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], VSrc_32,
1245 let Uses = [VCC] in { // Carry-in comes from VCC
1246 defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32",
1247 [(set i32:$dst, (adde i32:$src0, i32:$src1))], VReg_32>;
1248 defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32",
1249 [(set i32:$dst, (sube i32:$src0, i32:$src1))], VReg_32>;
1250 defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], VReg_32,
1252 } // End Uses = [VCC]
1253 } // End isCommutable = 1, Defs = [VCC]
1255 defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>;
1256 ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>;
1257 ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>;
1258 ////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>;
1259 defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32",
1260 [(set i32:$dst, (int_SI_packf16 f32:$src0, f32:$src1))]
1262 ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>;
1263 ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>;
1265 //===----------------------------------------------------------------------===//
1266 // VOP3 Instructions
1267 //===----------------------------------------------------------------------===//
1269 let neverHasSideEffects = 1 in {
1271 defm V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>;
1272 defm V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32",
1273 [(set f32:$dst, (fadd (fmul f32:$src0, f32:$src1), f32:$src2))]
1275 defm V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24",
1276 [(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))]
1278 defm V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24",
1279 [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))]
1282 } // End neverHasSideEffects
1284 defm V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>;
1285 defm V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>;
1286 defm V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>;
1287 defm V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>;
1289 let neverHasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
1290 defm V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32",
1291 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))]>;
1292 defm V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32",
1293 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))]>;
1296 defm V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32",
1297 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))]>;
1298 defm V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32",
1299 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))]
1301 def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64",
1302 [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
1304 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>;
1305 defm V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>;
1307 defm V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>;
1308 defm V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>;
1309 ////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>;
1310 ////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>;
1311 ////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>;
1312 ////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>;
1313 ////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>;
1314 ////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>;
1315 ////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>;
1316 ////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>;
1317 ////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>;
1318 //def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>;
1319 //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>;
1320 //def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>;
1321 defm V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>;
1322 ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>;
1323 defm V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>;
1324 def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>;
1326 def V_LSHL_B64 : VOP3_64_32 <0x00000161, "V_LSHL_B64",
1327 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
1329 def V_LSHR_B64 : VOP3_64_32 <0x00000162, "V_LSHR_B64",
1330 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
1332 def V_ASHR_I64 : VOP3_64_32 <0x00000163, "V_ASHR_I64",
1333 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
1336 let isCommutable = 1 in {
1338 def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>;
1339 def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>;
1340 def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>;
1341 def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>;
1343 } // isCommutable = 1
1345 def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>;
1347 let isCommutable = 1 in {
1349 defm V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>;
1350 defm V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>;
1351 defm V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>;
1352 defm V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>;
1354 } // isCommutable = 1
1356 defm V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>;
1357 def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>;
1358 defm V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>;
1359 def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>;
1360 //def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>;
1361 //def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>;
1362 //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>;
1363 def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>;
1365 //===----------------------------------------------------------------------===//
1366 // Pseudo Instructions
1367 //===----------------------------------------------------------------------===//
1369 let isCodeGenOnly = 1, isPseudo = 1 in {
1371 def V_MOV_I1 : InstSI <
1374 "", [(set i1:$dst, (imm:$src))]
1377 def V_AND_I1 : InstSI <
1378 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1379 [(set i1:$dst, (and i1:$src0, i1:$src1))]
1382 def V_OR_I1 : InstSI <
1383 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1384 [(set i1:$dst, (or i1:$src0, i1:$src1))]
1387 // SI pseudo instructions. These are used by the CFG structurizer pass
1388 // and should be lowered to ISA instructions prior to codegen.
1390 let mayLoad = 1, mayStore = 1, hasSideEffects = 1,
1391 Uses = [EXEC], Defs = [EXEC] in {
1393 let isBranch = 1, isTerminator = 1 in {
1396 (outs SReg_64:$dst),
1397 (ins SReg_64:$vcc, brtarget:$target),
1399 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))]
1402 def SI_ELSE : InstSI <
1403 (outs SReg_64:$dst),
1404 (ins SReg_64:$src, brtarget:$target),
1406 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]
1408 let Constraints = "$src = $dst";
1411 def SI_LOOP : InstSI <
1413 (ins SReg_64:$saved, brtarget:$target),
1414 "SI_LOOP $saved, $target",
1415 [(int_SI_loop i64:$saved, bb:$target)]
1418 } // end isBranch = 1, isTerminator = 1
1420 def SI_BREAK : InstSI <
1421 (outs SReg_64:$dst),
1423 "SI_ELSE $dst, $src",
1424 [(set i64:$dst, (int_SI_break i64:$src))]
1427 def SI_IF_BREAK : InstSI <
1428 (outs SReg_64:$dst),
1429 (ins SReg_64:$vcc, SReg_64:$src),
1430 "SI_IF_BREAK $dst, $vcc, $src",
1431 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))]
1434 def SI_ELSE_BREAK : InstSI <
1435 (outs SReg_64:$dst),
1436 (ins SReg_64:$src0, SReg_64:$src1),
1437 "SI_ELSE_BREAK $dst, $src0, $src1",
1438 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))]
1441 def SI_END_CF : InstSI <
1443 (ins SReg_64:$saved),
1445 [(int_SI_end_cf i64:$saved)]
1448 def SI_KILL : InstSI <
1452 [(int_AMDGPU_kill f32:$src)]
1455 } // end mayLoad = 1, mayStore = 1, hasSideEffects = 1
1456 // Uses = [EXEC], Defs = [EXEC]
1458 let Uses = [EXEC], Defs = [EXEC,VCC,M0] in {
1460 //defm SI_ : RegisterLoadStore <VReg_32, FRAMEri, ADDRIndirect>;
1462 let UseNamedOperandTable = 1 in {
1464 def SI_RegisterLoad : InstSI <
1465 (outs VReg_32:$dst, SReg_64:$temp),
1466 (ins FRAMEri32:$addr, i32imm:$chan),
1469 let isRegisterLoad = 1;
1473 class SIRegStore<dag outs> : InstSI <
1475 (ins VReg_32:$val, FRAMEri32:$addr, i32imm:$chan),
1478 let isRegisterStore = 1;
1482 let usesCustomInserter = 1 in {
1483 def SI_RegisterStorePseudo : SIRegStore<(outs)>;
1484 } // End usesCustomInserter = 1
1485 def SI_RegisterStore : SIRegStore<(outs SReg_64:$temp)>;
1488 } // End UseNamedOperandTable = 1
1490 def SI_INDIRECT_SRC : InstSI <
1491 (outs VReg_32:$dst, SReg_64:$temp),
1492 (ins unknown:$src, VSrc_32:$idx, i32imm:$off),
1493 "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off",
1497 class SI_INDIRECT_DST<RegisterClass rc> : InstSI <
1498 (outs rc:$dst, SReg_64:$temp),
1499 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val),
1500 "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val",
1503 let Constraints = "$src = $dst";
1506 def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VReg_32>;
1507 def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
1508 def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
1509 def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
1510 def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
1512 } // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0]
1514 let usesCustomInserter = 1 in {
1516 // This pseudo instruction takes a pointer as input and outputs a resource
1517 // constant that can be used with the ADDR64 MUBUF instructions.
1518 def SI_ADDR64_RSRC : InstSI <
1519 (outs SReg_128:$srsrc),
1524 def V_SUB_F64 : InstSI <
1525 (outs VReg_64:$dst),
1526 (ins VReg_64:$src0, VReg_64:$src1),
1527 "V_SUB_F64 $dst, $src0, $src1",
1531 } // end usesCustomInserter
1533 multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
1535 def _SAVE : InstSI <
1536 (outs VReg_32:$dst),
1537 (ins sgpr_class:$src, i32imm:$frame_idx),
1541 def _RESTORE : InstSI <
1542 (outs sgpr_class:$dst),
1543 (ins VReg_32:$src, i32imm:$frame_idx),
1549 defm SI_SPILL_S32 : SI_SPILL_SGPR <SReg_32>;
1550 defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>;
1551 defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>;
1552 defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>;
1553 defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;
1555 } // end IsCodeGenOnly, isPseudo
1557 } // end SubtargetPredicate = SI
1559 let Predicates = [isSI] in {
1562 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2),
1563 (V_CNDMASK_B32_e64 $src2, $src1, (V_CMP_GT_F32_e64 0, $src0))
1568 (SI_KILL 0xbf800000)
1571 /* int_SI_vs_load_input */
1573 (SIload_input v4i32:$tlst, IMM12bit:$attr_offset, i32:$buf_idx_vgpr),
1574 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0)
1579 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
1580 f32:$src0, f32:$src1, f32:$src2, f32:$src3),
1581 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
1582 $src0, $src1, $src2, $src3)
1586 (f64 (fsub f64:$src0, f64:$src1)),
1587 (V_SUB_F64 $src0, $src1)
1590 //===----------------------------------------------------------------------===//
1592 //===----------------------------------------------------------------------===//
1594 multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
1596 // 1. Offset as 8bit DWORD immediate
1598 (constant_load (add i64:$sbase, (i64 IMM8bitDWORD:$offset))),
1599 (vt (Instr_IMM $sbase, (as_dword_i32imm $offset)))
1602 // 2. Offset loaded in an 32bit SGPR
1604 (constant_load (add i64:$sbase, (i64 IMM32bit:$offset))),
1605 (vt (Instr_SGPR $sbase, (S_MOV_B32 (i32 (as_i32imm $offset)))))
1608 // 3. No offset at all
1610 (constant_load i64:$sbase),
1611 (vt (Instr_IMM $sbase, 0))
1615 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>;
1616 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
1617 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, i64>;
1618 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>;
1619 defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>;
1620 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
1621 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>;
1622 defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
1624 // 1. Offset as 8bit DWORD immediate
1626 (SIload_constant v4i32:$sbase, IMM8bitDWORD:$offset),
1627 (S_BUFFER_LOAD_DWORD_IMM $sbase, (as_dword_i32imm $offset))
1630 // 2. Offset loaded in an 32bit SGPR
1632 (SIload_constant v4i32:$sbase, imm:$offset),
1633 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset))
1636 //===----------------------------------------------------------------------===//
1638 //===----------------------------------------------------------------------===//
1641 (i1 (xor i1:$src0, i1:$src1)),
1642 (S_XOR_B64 $src0, $src1)
1645 //===----------------------------------------------------------------------===//
1647 //===----------------------------------------------------------------------===//
1650 (or i64:$src0, i64:$src1),
1651 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1652 (V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub0),
1653 (EXTRACT_SUBREG i64:$src1, sub0)), sub0),
1654 (V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub1),
1655 (EXTRACT_SUBREG i64:$src1, sub1)), sub1)
1658 class SextInReg <ValueType vt, int ShiftAmt> : Pat <
1659 (sext_inreg i32:$src0, vt),
1660 (V_ASHRREV_I32_e32 ShiftAmt, (V_LSHLREV_B32_e32 ShiftAmt, $src0))
1663 def : SextInReg <i8, 24>;
1664 def : SextInReg <i16, 16>;
1666 /********** ======================= **********/
1667 /********** Image sampling patterns **********/
1668 /********** ======================= **********/
1670 /* SIsample for simple 1D texture lookup */
1672 (SIsample i32:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
1673 (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1676 class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1677 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
1678 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1681 class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1682 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_RECT),
1683 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1686 class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1687 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_ARRAY),
1688 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1691 class SampleShadowPattern<SDNode name, MIMG opcode,
1692 ValueType vt> : Pat <
1693 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW),
1694 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1697 class SampleShadowArrayPattern<SDNode name, MIMG opcode,
1698 ValueType vt> : Pat <
1699 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
1700 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1703 /* SIsample* for texture lookups consuming more address parameters */
1704 multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l,
1705 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b,
1706 MIMG sample_d, MIMG sample_c_d, ValueType addr_type> {
1707 def : SamplePattern <SIsample, sample, addr_type>;
1708 def : SampleRectPattern <SIsample, sample, addr_type>;
1709 def : SampleArrayPattern <SIsample, sample, addr_type>;
1710 def : SampleShadowPattern <SIsample, sample_c, addr_type>;
1711 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>;
1713 def : SamplePattern <SIsamplel, sample_l, addr_type>;
1714 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>;
1715 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>;
1716 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>;
1718 def : SamplePattern <SIsampleb, sample_b, addr_type>;
1719 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>;
1720 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>;
1721 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>;
1723 def : SamplePattern <SIsampled, sample_d, addr_type>;
1724 def : SampleArrayPattern <SIsampled, sample_d, addr_type>;
1725 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>;
1726 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>;
1729 defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2,
1730 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2,
1731 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2,
1732 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2,
1734 defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4,
1735 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4,
1736 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4,
1737 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4,
1739 defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8,
1740 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8,
1741 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8,
1742 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8,
1744 defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16,
1745 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16,
1746 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16,
1747 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16,
1750 /* int_SI_imageload for texture fetches consuming varying address parameters */
1751 class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1752 (name addr_type:$addr, v32i8:$rsrc, imm),
1753 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
1756 class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1757 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY),
1758 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
1761 class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1762 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA),
1763 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
1766 class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1767 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA),
1768 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
1771 multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> {
1772 def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>;
1773 def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>;
1776 multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> {
1777 def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>;
1778 def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>;
1781 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V2, v2i32>;
1782 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V4, v4i32>;
1784 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V2, v2i32>;
1785 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V4, v4i32>;
1787 /* Image resource information */
1789 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm),
1790 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1794 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY),
1795 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1799 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA),
1800 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1803 /********** ============================================ **********/
1804 /********** Extraction, Insertion, Building and Casting **********/
1805 /********** ============================================ **********/
1807 foreach Index = 0-2 in {
1808 def Extract_Element_v2i32_#Index : Extract_Element <
1809 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
1811 def Insert_Element_v2i32_#Index : Insert_Element <
1812 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
1815 def Extract_Element_v2f32_#Index : Extract_Element <
1816 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
1818 def Insert_Element_v2f32_#Index : Insert_Element <
1819 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
1823 foreach Index = 0-3 in {
1824 def Extract_Element_v4i32_#Index : Extract_Element <
1825 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
1827 def Insert_Element_v4i32_#Index : Insert_Element <
1828 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
1831 def Extract_Element_v4f32_#Index : Extract_Element <
1832 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
1834 def Insert_Element_v4f32_#Index : Insert_Element <
1835 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
1839 foreach Index = 0-7 in {
1840 def Extract_Element_v8i32_#Index : Extract_Element <
1841 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
1843 def Insert_Element_v8i32_#Index : Insert_Element <
1844 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
1847 def Extract_Element_v8f32_#Index : Extract_Element <
1848 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
1850 def Insert_Element_v8f32_#Index : Insert_Element <
1851 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
1855 foreach Index = 0-15 in {
1856 def Extract_Element_v16i32_#Index : Extract_Element <
1857 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
1859 def Insert_Element_v16i32_#Index : Insert_Element <
1860 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
1863 def Extract_Element_v16f32_#Index : Extract_Element <
1864 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
1866 def Insert_Element_v16f32_#Index : Insert_Element <
1867 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
1871 def : BitConvert <i32, f32, SReg_32>;
1872 def : BitConvert <i32, f32, VReg_32>;
1874 def : BitConvert <f32, i32, SReg_32>;
1875 def : BitConvert <f32, i32, VReg_32>;
1877 def : BitConvert <i64, f64, VReg_64>;
1879 def : BitConvert <f64, i64, VReg_64>;
1881 def : BitConvert <v2f32, v2i32, VReg_64>;
1882 def : BitConvert <v2i32, v2f32, VReg_64>;
1883 def : BitConvert <v2i32, i64, VReg_64>;
1884 def : BitConvert <i64, v2i32, VReg_64>;
1885 def : BitConvert <v2f32, i64, VReg_64>;
1886 def : BitConvert <i64, v2f32, VReg_64>;
1887 def : BitConvert <v4f32, v4i32, VReg_128>;
1888 def : BitConvert <v4i32, v4f32, VReg_128>;
1890 def : BitConvert <v8f32, v8i32, SReg_256>;
1891 def : BitConvert <v8i32, v8f32, SReg_256>;
1892 def : BitConvert <v8i32, v32i8, SReg_256>;
1893 def : BitConvert <v32i8, v8i32, SReg_256>;
1894 def : BitConvert <v8i32, v32i8, VReg_256>;
1895 def : BitConvert <v8i32, v8f32, VReg_256>;
1896 def : BitConvert <v8f32, v8i32, VReg_256>;
1897 def : BitConvert <v32i8, v8i32, VReg_256>;
1899 def : BitConvert <v16i32, v16f32, VReg_512>;
1900 def : BitConvert <v16f32, v16i32, VReg_512>;
1902 /********** =================== **********/
1903 /********** Src & Dst modifiers **********/
1904 /********** =================== **********/
1906 def FCLAMP_SI : AMDGPUShaderInst <
1907 (outs VReg_32:$dst),
1908 (ins VSrc_32:$src0),
1909 "FCLAMP_SI $dst, $src0",
1912 let usesCustomInserter = 1;
1916 (int_AMDIL_clamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)),
1917 (FCLAMP_SI f32:$src)
1920 /********** ================================ **********/
1921 /********** Floating point absolute/negative **********/
1922 /********** ================================ **********/
1924 // Manipulate the sign bit directly, as e.g. using the source negation modifier
1925 // in V_ADD_F32_e64 $src, 0, [...] does not result in -0.0 for $src == +0.0,
1926 // breaking the piglit *s-floatBitsToInt-neg* tests
1928 // TODO: Look into not implementing isFNegFree/isFAbsFree for SI, and possibly
1929 // removing these patterns
1932 (fneg (fabs f32:$src)),
1933 (V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
1936 def FABS_SI : AMDGPUShaderInst <
1937 (outs VReg_32:$dst),
1938 (ins VSrc_32:$src0),
1939 "FABS_SI $dst, $src0",
1942 let usesCustomInserter = 1;
1950 def FNEG_SI : AMDGPUShaderInst <
1951 (outs VReg_32:$dst),
1952 (ins VSrc_32:$src0),
1953 "FNEG_SI $dst, $src0",
1956 let usesCustomInserter = 1;
1964 /********** ================== **********/
1965 /********** Immediate Patterns **********/
1966 /********** ================== **********/
1969 (SGPRImm<(i32 imm)>:$imm),
1970 (S_MOV_B32 imm:$imm)
1974 (SGPRImm<(f32 fpimm)>:$imm),
1975 (S_MOV_B32 fpimm:$imm)
1980 (V_MOV_B32_e32 imm:$imm)
1985 (V_MOV_B32_e32 fpimm:$imm)
1989 (i64 InlineImm<i64>:$imm),
1990 (S_MOV_B64 InlineImm<i64>:$imm)
1993 /********** ===================== **********/
1994 /********** Interpolation Paterns **********/
1995 /********** ===================== **********/
1998 (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params),
1999 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, $params)
2003 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, v2i32:$ij),
2004 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0),
2005 imm:$attr_chan, imm:$attr, i32:$params),
2006 (EXTRACT_SUBREG $ij, sub1),
2007 imm:$attr_chan, imm:$attr, $params)
2010 /********** ================== **********/
2011 /********** Intrinsic Patterns **********/
2012 /********** ================== **********/
2014 /* llvm.AMDGPU.pow */
2015 def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>;
2018 (int_AMDGPU_div f32:$src0, f32:$src1),
2019 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1))
2023 (fdiv f32:$src0, f32:$src1),
2024 (V_MUL_F32_e32 $src0, (V_RCP_F32_e32 $src1))
2028 (fdiv f64:$src0, f64:$src1),
2029 (V_MUL_F64 $src0, (V_RCP_F64_e32 $src1), (i64 0))
2034 (V_COS_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
2039 (V_SIN_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
2043 (int_AMDGPU_cube v4f32:$src),
2044 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2045 (V_CUBETC_F32 (EXTRACT_SUBREG $src, sub0),
2046 (EXTRACT_SUBREG $src, sub1),
2047 (EXTRACT_SUBREG $src, sub2)),
2049 (V_CUBESC_F32 (EXTRACT_SUBREG $src, sub0),
2050 (EXTRACT_SUBREG $src, sub1),
2051 (EXTRACT_SUBREG $src, sub2)),
2053 (V_CUBEMA_F32 (EXTRACT_SUBREG $src, sub0),
2054 (EXTRACT_SUBREG $src, sub1),
2055 (EXTRACT_SUBREG $src, sub2)),
2057 (V_CUBEID_F32 (EXTRACT_SUBREG $src, sub0),
2058 (EXTRACT_SUBREG $src, sub1),
2059 (EXTRACT_SUBREG $src, sub2)),
2064 (i32 (sext i1:$src0)),
2065 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
2068 class Ext32Pat <SDNode ext> : Pat <
2069 (i32 (ext i1:$src0)),
2070 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0)
2073 def : Ext32Pat <zext>;
2074 def : Ext32Pat <anyext>;
2076 // Offset in an 32Bit VGPR
2078 (SIload_constant v4i32:$sbase, i32:$voff),
2079 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0)
2082 // The multiplication scales from [0,1] to the unsigned integer range
2084 (AMDGPUurecip i32:$src0),
2086 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1,
2087 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
2092 (V_MBCNT_HI_U32_B32_e32 0xffffffff,
2093 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0, 0, 0))
2096 //===----------------------------------------------------------------------===//
2098 //===----------------------------------------------------------------------===//
2100 def : IMad24Pat<V_MAD_I32_I24>;
2101 def : UMad24Pat<V_MAD_U32_U24>;
2104 (fadd f64:$src0, f64:$src1),
2105 (V_ADD_F64 $src0, $src1, (i64 0))
2109 (fmul f64:$src0, f64:$src1),
2110 (V_MUL_F64 $src0, $src1, (i64 0))
2114 (mul i32:$src0, i32:$src1),
2115 (V_MUL_LO_I32 $src0, $src1, (i32 0))
2119 (mulhu i32:$src0, i32:$src1),
2120 (V_MUL_HI_U32 $src0, $src1, (i32 0))
2124 (mulhs i32:$src0, i32:$src1),
2125 (V_MUL_HI_I32 $src0, $src1, (i32 0))
2128 defm : BFIPatterns <V_BFI_B32, S_MOV_B32>;
2129 def : ROTRPattern <V_ALIGNBIT_B32>;
2131 /********** ======================= **********/
2132 /********** Load/Store Patterns **********/
2133 /********** ======================= **********/
2135 multiclass DSReadPat <DS inst, ValueType vt, PatFrag frag> {
2137 (vt (frag (add i32:$ptr, (i32 IMM16bit:$offset)))),
2138 (inst (i1 0), $ptr, (as_i16imm $offset))
2143 (vt (inst 0, $src0, 0))
2147 defm : DSReadPat <DS_READ_I8, i32, sextloadi8_local>;
2148 defm : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>;
2149 defm : DSReadPat <DS_READ_I16, i32, sextloadi16_local>;
2150 defm : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>;
2151 defm : DSReadPat <DS_READ_B32, i32, local_load>;
2152 defm : DSReadPat <DS_READ_B64, i64, local_load>;
2154 multiclass DSWritePat <DS inst, ValueType vt, PatFrag frag> {
2156 (frag vt:$value, (add i32:$ptr, (i32 IMM16bit:$offset))),
2157 (inst (i1 0), $ptr, $value, (as_i16imm $offset))
2161 (frag vt:$val, i32:$ptr),
2162 (inst 0, $ptr, $val, 0)
2166 defm : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>;
2167 defm : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>;
2168 defm : DSWritePat <DS_WRITE_B32, i32, local_store>;
2169 defm : DSWritePat <DS_WRITE_B64, i64, local_store>;
2171 multiclass DSAtomicPat<DS inst, ValueType vt, PatFrag frag> {
2173 (frag (add i32:$ptr, (i32 IMM16bit:$offset)), vt:$value),
2174 (inst (i1 0), $ptr, $value, (as_i16imm $offset))
2178 (frag i32:$ptr, vt:$val),
2179 (inst 0, $ptr, $val, 0)
2183 defm : DSAtomicPat<DS_ADD_U32_RTN, i32, atomic_load_add_local>;
2184 defm : DSAtomicPat<DS_SUB_U32_RTN, i32, atomic_load_sub_local>;
2186 //===----------------------------------------------------------------------===//
2188 //===----------------------------------------------------------------------===//
2190 multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
2191 PatFrag global_ld, PatFrag constant_ld> {
2193 (vt (global_ld (mubuf_vaddr_offset i64:$ptr, i64:$offset, IMM12bit:$imm_offset))),
2194 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, (as_i16imm $imm_offset))
2198 (vt (global_ld (add i64:$ptr, (i64 IMM12bit:$offset)))),
2199 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset))
2203 (vt (global_ld i64:$ptr)),
2204 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, 0)
2208 (vt (global_ld (add i64:$ptr, i64:$offset))),
2209 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0)
2213 (vt (constant_ld (add i64:$ptr, i64:$offset))),
2214 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0)
2218 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32,
2219 sextloadi8_global, sextloadi8_constant>;
2220 defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32,
2221 az_extloadi8_global, az_extloadi8_constant>;
2222 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32,
2223 sextloadi16_global, sextloadi16_constant>;
2224 defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32,
2225 az_extloadi16_global, az_extloadi16_constant>;
2226 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32,
2227 global_load, constant_load>;
2228 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64,
2229 global_load, constant_load>;
2230 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64,
2231 az_extloadi32_global, az_extloadi32_constant>;
2232 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32,
2233 global_load, constant_load>;
2234 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32,
2235 global_load, constant_load>;
2237 multiclass MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> {
2240 (st vt:$value, (mubuf_vaddr_offset i64:$ptr, i64:$offset, IMM12bit:$imm_offset)),
2241 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, (as_i16imm $imm_offset))
2245 (st vt:$value, (add i64:$ptr, IMM12bit:$offset)),
2246 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset))
2250 (st vt:$value, i64:$ptr),
2251 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, 0)
2255 (st vt:$value, (add i64:$ptr, i64:$offset)),
2256 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, 0)
2260 defm : MUBUFStore_Pattern <BUFFER_STORE_BYTE, i32, truncstorei8_global>;
2261 defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT, i32, truncstorei16_global>;
2262 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORD, i32, global_store>;
2263 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, i64, global_store>;
2264 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, v2i32, global_store>;
2265 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4, v4i32, global_store>;
2267 // BUFFER_LOAD_DWORD*, addr64=0
2268 multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen,
2272 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2273 imm:$offset, 0, 0, imm:$glc, imm:$slc,
2275 (offset $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2276 (as_i1imm $slc), (as_i1imm $tfe))
2280 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2281 imm, 1, 0, imm:$glc, imm:$slc,
2283 (offen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
2288 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2289 imm:$offset, 0, 1, imm:$glc, imm:$slc,
2291 (idxen $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2292 (as_i1imm $slc), (as_i1imm $tfe))
2296 (vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset,
2297 imm, 1, 1, imm:$glc, imm:$slc,
2299 (bothen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
2304 defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN,
2305 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
2306 defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN,
2307 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>;
2308 defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN,
2309 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
2311 //===----------------------------------------------------------------------===//
2313 //===----------------------------------------------------------------------===//
2315 // TBUFFER_STORE_FORMAT_*, addr64=0
2316 class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat<
2317 (SItbuffer_store v4i32:$rsrc, vt:$vdata, num_channels, i32:$vaddr,
2318 i32:$soffset, imm:$inst_offset, imm:$dfmt,
2319 imm:$nfmt, imm:$offen, imm:$idxen,
2320 imm:$glc, imm:$slc, imm:$tfe),
2322 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen),
2323 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc,
2324 (as_i1imm $slc), (as_i1imm $tfe), $soffset)
2327 def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>;
2328 def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>;
2329 def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>;
2330 def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>;
2332 let Predicates = [isCI] in {
2334 // Sea island new arithmetic instructinos
2335 let neverHasSideEffects = 1 in {
2336 defm V_TRUNC_F64 : VOP1_64 <0x00000017, "V_TRUNC_F64",
2337 [(set f64:$dst, (ftrunc f64:$src0))]
2339 defm V_CEIL_F64 : VOP1_64 <0x00000018, "V_CEIL_F64",
2340 [(set f64:$dst, (fceil f64:$src0))]
2342 defm V_FLOOR_F64 : VOP1_64 <0x0000001A, "V_FLOOR_F64",
2343 [(set f64:$dst, (ffloor f64:$src0))]
2345 defm V_RNDNE_F64 : VOP1_64 <0x00000019, "V_RNDNE_F64",
2346 [(set f64:$dst, (frint f64:$src0))]
2349 defm V_QSAD_PK_U16_U8 : VOP3_32 <0x00000173, "V_QSAD_PK_U16_U8", []>;
2350 defm V_MQSAD_U16_U8 : VOP3_32 <0x000000172, "V_MQSAD_U16_U8", []>;
2351 defm V_MQSAD_U32_U8 : VOP3_32 <0x00000175, "V_MQSAD_U32_U8", []>;
2352 def V_MAD_U64_U32 : VOP3_64 <0x00000176, "V_MAD_U64_U32", []>;
2354 // XXX - Does this set VCC?
2355 def V_MAD_I64_I32 : VOP3_64 <0x00000177, "V_MAD_I64_I32", []>;
2356 } // End neverHasSideEffects = 1
2358 // Remaining instructions:
2360 // S_CBRANCH_CDBGUSER
2361 // S_CBRANCH_CDBGSYS
2362 // S_CBRANCH_CDBGSYS_OR_USER
2363 // S_CBRANCH_CDBGSYS_AND_USER
2368 // DS_GWS_SEMA_RELEASE_ALL
2370 // DS_CNDXCHG32_RTN_B64
2373 // DS_CONDXCHG32_RTN_B128
2376 // BUFFER_LOAD_DWORDX3
2377 // BUFFER_STORE_DWORDX3
2379 } // End Predicates = [isCI]
2382 /********** ====================== **********/
2383 /********** Indirect adressing **********/
2384 /********** ====================== **********/
2386 multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, SI_INDIRECT_DST IndDst> {
2388 // 1. Extract with offset
2390 (vector_extract vt:$vec, (add i32:$idx, imm:$off)),
2391 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off))
2394 // 2. Extract without offset
2396 (vector_extract vt:$vec, i32:$idx),
2397 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0))
2400 // 3. Insert with offset
2402 (vector_insert vt:$vec, eltvt:$val, (add i32:$idx, imm:$off)),
2403 (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val)
2406 // 4. Insert without offset
2408 (vector_insert vt:$vec, eltvt:$val, i32:$idx),
2409 (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val)
2413 defm : SI_INDIRECT_Pattern <v2f32, f32, SI_INDIRECT_DST_V2>;
2414 defm : SI_INDIRECT_Pattern <v4f32, f32, SI_INDIRECT_DST_V4>;
2415 defm : SI_INDIRECT_Pattern <v8f32, f32, SI_INDIRECT_DST_V8>;
2416 defm : SI_INDIRECT_Pattern <v16f32, f32, SI_INDIRECT_DST_V16>;
2418 defm : SI_INDIRECT_Pattern <v2i32, i32, SI_INDIRECT_DST_V2>;
2419 defm : SI_INDIRECT_Pattern <v4i32, i32, SI_INDIRECT_DST_V4>;
2420 defm : SI_INDIRECT_Pattern <v8i32, i32, SI_INDIRECT_DST_V8>;
2421 defm : SI_INDIRECT_Pattern <v16i32, i32, SI_INDIRECT_DST_V16>;
2423 //===----------------------------------------------------------------------===//
2424 // Conversion Patterns
2425 //===----------------------------------------------------------------------===//
2427 def : Pat<(i32 (sext_inreg i32:$src, i1)),
2428 (S_BFE_I32 i32:$src, 65536)>; // 0 | 1 << 16
2430 // TODO: Match 64-bit BFE. SI has a 64-bit BFE, but it's scalar only so it
2431 // might not be worth the effort, and will need to expand to shifts when
2432 // fixing SGPR copies.
2434 // Handle sext_inreg in i64
2436 (i64 (sext_inreg i64:$src, i1)),
2437 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2438 (S_BFE_I32 (EXTRACT_SUBREG i64:$src, sub0), 65536), sub0), // 0 | 1 << 16
2439 (S_MOV_B32 -1), sub1)
2443 (i64 (sext_inreg i64:$src, i8)),
2444 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2445 (S_SEXT_I32_I8 (EXTRACT_SUBREG i64:$src, sub0)), sub0),
2446 (S_MOV_B32 -1), sub1)
2450 (i64 (sext_inreg i64:$src, i16)),
2451 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2452 (S_SEXT_I32_I16 (EXTRACT_SUBREG i64:$src, sub0)), sub0),
2453 (S_MOV_B32 -1), sub1)
2456 class ZExt_i64_i32_Pat <SDNode ext> : Pat <
2457 (i64 (ext i32:$src)),
2458 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $src, sub0),
2459 (S_MOV_B32 0), sub1)
2462 class ZExt_i64_i1_Pat <SDNode ext> : Pat <
2463 (i64 (ext i1:$src)),
2465 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2466 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src), sub0),
2467 (S_MOV_B32 0), sub1)
2471 def : ZExt_i64_i32_Pat<zext>;
2472 def : ZExt_i64_i32_Pat<anyext>;
2473 def : ZExt_i64_i1_Pat<zext>;
2474 def : ZExt_i64_i1_Pat<anyext>;
2477 (i64 (sext i32:$src)),
2479 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $src, sub0),
2480 (S_ASHR_I32 $src, 31), sub1)
2484 (i64 (sext i1:$src)),
2487 (i64 (IMPLICIT_DEF)),
2488 (V_CNDMASK_B32_e64 0, -1, $src), sub0),
2489 (V_CNDMASK_B32_e64 0, -1, $src), sub1)
2493 (f32 (sint_to_fp i1:$src)),
2494 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_NEG_ONE, $src)
2498 (f32 (uint_to_fp i1:$src)),
2499 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_ONE, $src)
2503 (f64 (sint_to_fp i1:$src)),
2504 (V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src))
2508 (f64 (uint_to_fp i1:$src)),
2509 (V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src))
2512 //===----------------------------------------------------------------------===//
2513 // Miscellaneous Patterns
2514 //===----------------------------------------------------------------------===//
2517 (i32 (trunc i64:$a)),
2518 (EXTRACT_SUBREG $a, sub0)
2522 (i1 (trunc i32:$a)),
2523 (V_CMP_EQ_I32_e64 (V_AND_B32_e32 (i32 1), $a), 1)
2526 // V_ADD_I32_e32/S_ADD_I32 produces carry in VCC/SCC. For the vector
2527 // case, the sgpr-copies pass will fix this to use the vector version.
2529 (i32 (addc i32:$src0, i32:$src1)),
2530 (S_ADD_I32 $src0, $src1)
2534 (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)),
2535 (V_BCNT_U32_B32_e32 $popcnt, $val)
2539 (i64 (ctpop i64:$src)),
2540 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2541 (S_BCNT1_I32_B64 $src), sub0),
2542 (S_MOV_B32 0), sub1)
2545 //============================================================================//
2546 // Miscellaneous Optimization Patterns
2547 //============================================================================//
2549 def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e32>;
2551 } // End isSI predicate