1 //===-- SIInstructions.td - SI Instruction Defintions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This file was originally auto-generated from a GPU register header file and
10 // all the instruction definitions were originally commented out. Instructions
11 // that are not yet supported remain commented out.
12 //===----------------------------------------------------------------------===//
19 def INTERP : InterpSlots;
21 def InterpSlot : Operand<i32> {
22 let PrintMethod = "printInterpSlot";
25 def SendMsgImm : Operand<i32> {
26 let PrintMethod = "printSendMsg";
29 def isSI : Predicate<"Subtarget.getGeneration() "
30 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">;
32 def isCI : Predicate<"Subtarget.getGeneration() "
33 ">= AMDGPUSubtarget::SEA_ISLANDS">;
35 def isCFDepth0 : Predicate<"isCFDepth0()">;
37 def WAIT_FLAG : InstFlag<"printWaitFlag">;
39 //===----------------------------------------------------------------------===//
41 //===----------------------------------------------------------------------===//
43 let Predicates = [isSI, isCFDepth0] in {
47 // We are using the SGPR_32 and not the SReg_32 register class for 32-bit
48 // SMRD instructions, because the SGPR_32 register class does not include M0
49 // and writing to M0 from an SMRD instruction will hang the GPU.
50 defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SGPR_32>;
51 defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>;
52 defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>;
53 defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>;
54 defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>;
56 defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
57 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SGPR_32
60 defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
61 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64
64 defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper <
65 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128
68 defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <
69 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256
72 defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
73 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512
78 //def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>;
79 //def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>;
81 } // let Predicates = [isSI, isCFDepth0]
83 //===----------------------------------------------------------------------===//
85 //===----------------------------------------------------------------------===//
87 let Predicates = [isSI, isCFDepth0] in {
89 let neverHasSideEffects = 1 in {
91 let isMoveImm = 1 in {
92 def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>;
93 def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>;
94 def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>;
95 def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>;
96 } // End isMoveImm = 1
98 def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32",
99 [(set i32:$dst, (not i32:$src0))]
102 def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", []>;
103 def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>;
104 def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>;
105 def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>;
106 def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>;
107 } // End neverHasSideEffects = 1
109 ////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>;
110 ////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>;
111 ////def S_BCNT1_I32_B32 : SOP1_BCNT1 <0x0000000f, "S_BCNT1_I32_B32", []>;
112 ////def S_BCNT1_I32_B64 : SOP1_BCNT1 <0x00000010, "S_BCNT1_I32_B64", []>;
113 ////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>;
114 ////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>;
115 ////def S_FF1_I32_B32 : SOP1_FF1 <0x00000013, "S_FF1_I32_B32", []>;
116 ////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>;
117 //def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", []>;
118 //def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>;
119 def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>;
120 //def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>;
121 def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8",
122 [(set i32:$dst, (sext_inreg i32:$src0, i8))]
124 def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16",
125 [(set i32:$dst, (sext_inreg i32:$src0, i16))]
128 ////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>;
129 ////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>;
130 ////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>;
131 ////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>;
132 def S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>;
133 def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>;
134 def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>;
135 def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>;
137 let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in {
139 def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>;
140 def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>;
141 def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>;
142 def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>;
143 def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>;
144 def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>;
145 def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>;
146 def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>;
148 } // End hasSideEffects = 1
150 def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>;
151 def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>;
152 def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>;
153 def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>;
154 def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>;
155 def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>;
156 //def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>;
157 def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>;
158 def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>;
159 def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>;
161 } // let Predicates = [isSI, isCFDepth0]
163 //===----------------------------------------------------------------------===//
165 //===----------------------------------------------------------------------===//
167 let Predicates = [isSI, isCFDepth0] in {
169 let Defs = [SCC] in { // Carry out goes to SCC
170 let isCommutable = 1 in {
171 def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>;
172 def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32",
173 [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))]
175 } // End isCommutable = 1
177 def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>;
178 def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32",
179 [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))]
182 let Uses = [SCC] in { // Carry in comes from SCC
183 let isCommutable = 1 in {
184 def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32",
185 [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
186 } // End isCommutable = 1
188 def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32",
189 [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
190 } // End Uses = [SCC]
191 } // End Defs = [SCC]
193 def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32",
194 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]
196 def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32",
197 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]
199 def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32",
200 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]
202 def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32",
203 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]
206 def S_CSELECT_B32 : SOP2 <
207 0x0000000a, (outs SReg_32:$dst),
208 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32",
212 def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>;
214 def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32",
215 [(set i32:$dst, (and i32:$src0, i32:$src1))]
218 def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64",
219 [(set i64:$dst, (and i64:$src0, i64:$src1))]
222 def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32",
223 [(set i32:$dst, (or i32:$src0, i32:$src1))]
226 def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64",
227 [(set i64:$dst, (or i64:$src0, i64:$src1))]
230 def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32",
231 [(set i32:$dst, (xor i32:$src0, i32:$src1))]
234 def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64",
235 [(set i64:$dst, (xor i64:$src0, i64:$src1))]
237 def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>;
238 def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>;
239 def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>;
240 def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>;
241 def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>;
242 def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>;
243 def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>;
244 def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>;
245 def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>;
246 def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>;
248 // Use added complexity so these patterns are preferred to the VALU patterns.
249 let AddedComplexity = 1 in {
251 def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32",
252 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
254 def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "S_LSHL_B64",
255 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
257 def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32",
258 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
260 def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "S_LSHR_B64",
261 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
263 def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32",
264 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
266 def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64",
267 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
270 } // End AddedComplexity = 1
272 def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>;
273 def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>;
274 def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>;
275 def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>;
276 def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>;
277 def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>;
278 def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>;
279 //def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>;
280 def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>;
282 } // let Predicates = [isSI, isCFDepth0]
284 //===----------------------------------------------------------------------===//
286 //===----------------------------------------------------------------------===//
288 let Predicates = [isSI, isCFDepth0] in {
290 def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32">;
291 def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32">;
292 def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32">;
293 def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32">;
294 def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32">;
295 def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32">;
296 def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32">;
297 def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32">;
298 def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32">;
299 def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32">;
300 def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32">;
301 def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32">;
302 ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>;
303 ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>;
304 ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>;
305 ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>;
306 //def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>;
308 } // let Predicates = [isSI, isCFDepth0]
310 //===----------------------------------------------------------------------===//
312 //===----------------------------------------------------------------------===//
314 let Predicates = [isSI, isCFDepth0] in {
316 def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>;
317 def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>;
320 This instruction is disabled for now until we can figure out how to teach
321 the instruction selector to correctly use the S_CMP* vs V_CMP*
324 When this instruction is enabled the code generator sometimes produces this
327 SCC = S_CMPK_EQ_I32 SGPR0, imm
329 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
331 def S_CMPK_EQ_I32 : SOPK <
332 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1),
334 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))]
338 let isCompare = 1 in {
339 def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>;
340 def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>;
341 def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>;
342 def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>;
343 def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>;
344 def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>;
345 def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>;
346 def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>;
347 def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>;
348 def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>;
349 def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>;
350 } // End isCompare = 1
352 let Defs = [SCC], isCommutable = 1 in {
353 def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>;
354 def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>;
357 //def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>;
358 def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>;
359 def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>;
360 def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>;
361 //def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>;
362 //def EXP : EXP_ <0x00000000, "EXP", []>;
364 } // let Predicates = [isSI, isCFDepth0]
366 //===----------------------------------------------------------------------===//
368 //===----------------------------------------------------------------------===//
370 let Predicates = [isSI] in {
372 //def S_NOP : SOPP_ <0x00000000, "S_NOP", []>;
374 let isTerminator = 1 in {
376 def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM",
383 let isBranch = 1 in {
384 def S_BRANCH : SOPP <
385 0x00000002, (ins brtarget:$target), "S_BRANCH $target",
390 let DisableEncoding = "$scc" in {
391 def S_CBRANCH_SCC0 : SOPP <
392 0x00000004, (ins brtarget:$target, SCCReg:$scc),
393 "S_CBRANCH_SCC0 $target", []
395 def S_CBRANCH_SCC1 : SOPP <
396 0x00000005, (ins brtarget:$target, SCCReg:$scc),
397 "S_CBRANCH_SCC1 $target",
400 } // End DisableEncoding = "$scc"
402 def S_CBRANCH_VCCZ : SOPP <
403 0x00000006, (ins brtarget:$target, VCCReg:$vcc),
404 "S_CBRANCH_VCCZ $target",
407 def S_CBRANCH_VCCNZ : SOPP <
408 0x00000007, (ins brtarget:$target, VCCReg:$vcc),
409 "S_CBRANCH_VCCNZ $target",
413 let DisableEncoding = "$exec" in {
414 def S_CBRANCH_EXECZ : SOPP <
415 0x00000008, (ins brtarget:$target, EXECReg:$exec),
416 "S_CBRANCH_EXECZ $target",
419 def S_CBRANCH_EXECNZ : SOPP <
420 0x00000009, (ins brtarget:$target, EXECReg:$exec),
421 "S_CBRANCH_EXECNZ $target",
424 } // End DisableEncoding = "$exec"
427 } // End isBranch = 1
428 } // End isTerminator = 1
430 let hasSideEffects = 1 in {
431 def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER",
432 [(int_AMDGPU_barrier_local)]
441 def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16",
444 //def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>;
445 //def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>;
446 //def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>;
448 let Uses = [EXEC] in {
449 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "S_SENDMSG $simm16",
450 [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)]
452 let DisableEncoding = "$m0";
454 } // End Uses = [EXEC]
456 //def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>;
457 //def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>;
458 //def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>;
459 //def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>;
460 //def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>;
461 //def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
462 } // End hasSideEffects
464 } // let Predicates = [isSI, isCFDepth0]
466 let Predicates = [isSI] in {
468 //===----------------------------------------------------------------------===//
470 //===----------------------------------------------------------------------===//
472 let isCompare = 1 in {
474 defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">;
475 defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_OLT>;
476 defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", f32, COND_OEQ>;
477 defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", f32, COND_OLE>;
478 defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", f32, COND_OGT>;
479 defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32">;
480 defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", f32, COND_OGE>;
481 defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32", f32, COND_O>;
482 defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32", f32, COND_UO>;
483 defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32">;
484 defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32">;
485 defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32">;
486 defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32">;
487 defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", f32, COND_UNE>;
488 defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">;
489 defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">;
491 let hasSideEffects = 1, Defs = [EXEC] in {
493 defm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32">;
494 defm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32">;
495 defm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32">;
496 defm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32">;
497 defm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32">;
498 defm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32">;
499 defm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32">;
500 defm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32">;
501 defm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32">;
502 defm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32">;
503 defm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32">;
504 defm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32">;
505 defm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32">;
506 defm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32">;
507 defm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32">;
508 defm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32">;
510 } // End hasSideEffects = 1, Defs = [EXEC]
512 defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">;
513 defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64", f64, COND_OLT>;
514 defm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64", f64, COND_OEQ>;
515 defm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64", f64, COND_OLE>;
516 defm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64", f64, COND_OGT>;
517 defm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64">;
518 defm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64", f64, COND_OGE>;
519 defm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64", f64, COND_O>;
520 defm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64", f64, COND_UO>;
521 defm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64">;
522 defm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64">;
523 defm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64">;
524 defm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64">;
525 defm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64", f64, COND_UNE>;
526 defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">;
527 defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">;
529 let hasSideEffects = 1, Defs = [EXEC] in {
531 defm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64">;
532 defm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64">;
533 defm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64">;
534 defm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64">;
535 defm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64">;
536 defm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64">;
537 defm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64">;
538 defm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64">;
539 defm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64">;
540 defm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64">;
541 defm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64">;
542 defm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64">;
543 defm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64">;
544 defm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64">;
545 defm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64">;
546 defm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64">;
548 } // End hasSideEffects = 1, Defs = [EXEC]
550 defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">;
551 defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">;
552 defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32">;
553 defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32">;
554 defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32">;
555 defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32">;
556 defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32">;
557 defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32">;
558 defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32">;
559 defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32">;
560 defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32">;
561 defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32">;
562 defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32">;
563 defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">;
564 defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">;
565 defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">;
567 let hasSideEffects = 1, Defs = [EXEC] in {
569 defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32">;
570 defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32">;
571 defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32">;
572 defm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32">;
573 defm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32">;
574 defm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32">;
575 defm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32">;
576 defm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32">;
577 defm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32">;
578 defm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32">;
579 defm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32">;
580 defm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32">;
581 defm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32">;
582 defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32">;
583 defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32">;
584 defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32">;
586 } // End hasSideEffects = 1, Defs = [EXEC]
588 defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">;
589 defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">;
590 defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">;
591 defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64">;
592 defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64">;
593 defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64">;
594 defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64">;
595 defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64">;
596 defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64">;
597 defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64">;
598 defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64">;
599 defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64">;
600 defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64">;
601 defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">;
602 defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">;
603 defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">;
605 let hasSideEffects = 1, Defs = [EXEC] in {
607 defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">;
608 defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">;
609 defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">;
610 defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64">;
611 defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64">;
612 defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64">;
613 defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64">;
614 defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64">;
615 defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64">;
616 defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64">;
617 defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64">;
618 defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64">;
619 defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64">;
620 defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">;
621 defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">;
622 defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">;
624 } // End hasSideEffects = 1, Defs = [EXEC]
626 defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">;
627 defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_SLT>;
628 defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>;
629 defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", i32, COND_SLE>;
630 defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", i32, COND_SGT>;
631 defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", i32, COND_NE>;
632 defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_SGE>;
633 defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">;
635 let hasSideEffects = 1, Defs = [EXEC] in {
637 defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32">;
638 defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32">;
639 defm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32">;
640 defm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32">;
641 defm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32">;
642 defm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32">;
643 defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32">;
644 defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32">;
646 } // End hasSideEffects = 1, Defs = [EXEC]
648 defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">;
649 defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64", i64, COND_SLT>;
650 defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64", i64, COND_EQ>;
651 defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64", i64, COND_SLE>;
652 defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64", i64, COND_SGT>;
653 defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64", i64, COND_NE>;
654 defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64", i64, COND_SGE>;
655 defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">;
657 let hasSideEffects = 1, Defs = [EXEC] in {
659 defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64">;
660 defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64">;
661 defm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64">;
662 defm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64">;
663 defm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64">;
664 defm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64">;
665 defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64">;
666 defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64">;
668 } // End hasSideEffects = 1, Defs = [EXEC]
670 defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">;
671 defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32", i32, COND_ULT>;
672 defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32", i32, COND_EQ>;
673 defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32", i32, COND_ULE>;
674 defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32", i32, COND_UGT>;
675 defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32", i32, COND_NE>;
676 defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32", i32, COND_UGE>;
677 defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">;
679 let hasSideEffects = 1, Defs = [EXEC] in {
681 defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32">;
682 defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32">;
683 defm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32">;
684 defm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32">;
685 defm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32">;
686 defm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32">;
687 defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32">;
688 defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32">;
690 } // End hasSideEffects = 1, Defs = [EXEC]
692 defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">;
693 defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64", i64, COND_ULT>;
694 defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64", i64, COND_EQ>;
695 defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64", i64, COND_ULE>;
696 defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64", i64, COND_UGT>;
697 defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64", i64, COND_NE>;
698 defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64", i64, COND_UGE>;
699 defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">;
701 let hasSideEffects = 1, Defs = [EXEC] in {
703 defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64">;
704 defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64">;
705 defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64">;
706 defm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64">;
707 defm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64">;
708 defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64">;
709 defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64">;
710 defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64">;
712 } // End hasSideEffects = 1, Defs = [EXEC]
714 defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">;
716 let hasSideEffects = 1, Defs = [EXEC] in {
717 defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">;
718 } // End hasSideEffects = 1, Defs = [EXEC]
720 defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">;
722 let hasSideEffects = 1, Defs = [EXEC] in {
723 defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">;
724 } // End hasSideEffects = 1, Defs = [EXEC]
726 } // End isCompare = 1
728 //===----------------------------------------------------------------------===//
730 //===----------------------------------------------------------------------===//
732 def DS_ADD_U32_RTN : DS_1A1D_RET <0x20, "DS_ADD_U32_RTN", VReg_32>;
733 def DS_SUB_U32_RTN : DS_1A1D_RET <0x21, "DS_SUB_U32_RTN", VReg_32>;
734 def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>;
735 def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "DS_WRITE_B8", VReg_32>;
736 def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "DS_WRITE_B16", VReg_32>;
737 def DS_WRITE_B64 : DS_Store_Helper <0x00000004d, "DS_WRITE_B64", VReg_64>;
739 def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>;
740 def DS_READ_I8 : DS_Load_Helper <0x00000039, "DS_READ_I8", VReg_32>;
741 def DS_READ_U8 : DS_Load_Helper <0x0000003a, "DS_READ_U8", VReg_32>;
742 def DS_READ_I16 : DS_Load_Helper <0x0000003b, "DS_READ_I16", VReg_32>;
743 def DS_READ_U16 : DS_Load_Helper <0x0000003c, "DS_READ_U16", VReg_32>;
744 def DS_READ_B64 : DS_Load_Helper <0x00000076, "DS_READ_B64", VReg_64>;
747 def DS_WRITE2_B32 : DS_Load2_Helper <0x0000000E, "DS_WRITE2_B32", VReg_64>;
748 def DS_WRITE2_B64 : DS_Load2_Helper <0x0000004E, "DS_WRITE2_B64", VReg_128>;
750 def DS_READ2_B32 : DS_Load2_Helper <0x00000037, "DS_READ2_B32", VReg_64>;
751 def DS_READ2_B64 : DS_Load2_Helper <0x00000075, "DS_READ2_B64", VReg_128>;
753 // TODO: DS_READ2ST64_B32, DS_READ2ST64_B64,
754 // DS_WRITE2ST64_B32, DS_WRITE2ST64_B64
756 //===----------------------------------------------------------------------===//
757 // MUBUF Instructions
758 //===----------------------------------------------------------------------===//
760 //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>;
761 //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>;
762 //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>;
763 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>;
764 //def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>;
765 //def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>;
766 //def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>;
767 //def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>;
768 defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <0x00000008, "BUFFER_LOAD_UBYTE", VReg_32>;
769 defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <0x00000009, "BUFFER_LOAD_SBYTE", VReg_32>;
770 defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <0x0000000a, "BUFFER_LOAD_USHORT", VReg_32>;
771 defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32>;
772 defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <0x0000000c, "BUFFER_LOAD_DWORD", VReg_32>;
773 defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64>;
774 defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128>;
776 def BUFFER_STORE_BYTE : MUBUF_Store_Helper <
777 0x00000018, "BUFFER_STORE_BYTE", VReg_32
780 def BUFFER_STORE_SHORT : MUBUF_Store_Helper <
781 0x0000001a, "BUFFER_STORE_SHORT", VReg_32
784 def BUFFER_STORE_DWORD : MUBUF_Store_Helper <
785 0x0000001c, "BUFFER_STORE_DWORD", VReg_32
788 def BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper <
789 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64
792 def BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper <
793 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128
795 //def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>;
796 //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>;
797 //def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>;
798 //def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>;
799 //def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>;
800 //def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>;
801 //def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>;
802 //def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>;
803 //def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>;
804 //def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>;
805 //def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>;
806 //def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>;
807 //def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>;
808 //def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>;
809 //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>;
810 //def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>;
811 //def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>;
812 //def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>;
813 //def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>;
814 //def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>;
815 //def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>;
816 //def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>;
817 //def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>;
818 //def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>;
819 //def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>;
820 //def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>;
821 //def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>;
822 //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>;
823 //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>;
824 //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>;
825 //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>;
826 //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>;
827 //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>;
828 //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>;
829 //def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>;
830 //def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>;
832 //===----------------------------------------------------------------------===//
833 // MTBUF Instructions
834 //===----------------------------------------------------------------------===//
836 //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>;
837 //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>;
838 //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>;
839 def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>;
840 def TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "TBUFFER_STORE_FORMAT_X", VReg_32>;
841 def TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FORMAT_XY", VReg_64>;
842 def TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>;
843 def TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>;
845 //===----------------------------------------------------------------------===//
847 //===----------------------------------------------------------------------===//
849 defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "IMAGE_LOAD">;
850 defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "IMAGE_LOAD_MIP">;
851 //def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>;
852 //def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>;
853 //def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>;
854 //def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>;
855 //def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>;
856 //def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>;
857 //def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>;
858 //def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>;
859 defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "IMAGE_GET_RESINFO">;
860 //def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>;
861 //def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>;
862 //def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>;
863 //def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>;
864 //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>;
865 //def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>;
866 //def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>;
867 //def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>;
868 //def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>;
869 //def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>;
870 //def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>;
871 //def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>;
872 //def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>;
873 //def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>;
874 //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>;
875 //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>;
876 //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>;
877 defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">;
878 //def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>;
879 defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">;
880 //def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>;
881 defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">;
882 defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">;
883 //def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>;
884 //def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>;
885 defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">;
886 //def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>;
887 defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">;
888 //def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>;
889 defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">;
890 defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">;
891 //def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>;
892 //def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>;
893 //def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>;
894 //def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>;
895 //def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>;
896 //def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>;
897 //def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>;
898 //def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>;
899 //def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>;
900 //def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>;
901 //def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>;
902 //def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>;
903 //def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>;
904 //def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>;
905 //def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>;
906 //def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>;
907 //def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>;
908 //def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>;
909 //def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>;
910 //def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>;
911 //def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>;
912 //def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>;
913 //def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>;
914 //def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>;
915 //def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>;
916 //def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>;
917 //def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>;
918 //def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>;
919 //def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>;
920 //def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>;
921 //def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>;
922 //def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>;
923 //def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>;
924 //def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>;
925 //def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>;
926 //def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>;
927 //def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>;
928 //def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>;
929 //def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>;
930 //def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>;
931 //def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>;
932 //def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>;
933 //def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>;
934 //def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>;
935 //def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>;
936 //def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>;
937 //def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>;
938 //def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>;
939 //def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>;
940 //def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>;
941 //def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>;
942 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>;
943 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>;
945 //===----------------------------------------------------------------------===//
947 //===----------------------------------------------------------------------===//
949 //def V_NOP : VOP1_ <0x00000000, "V_NOP", []>;
951 let neverHasSideEffects = 1, isMoveImm = 1 in {
952 defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>;
953 } // End neverHasSideEffects = 1, isMoveImm = 1
955 let Uses = [EXEC] in {
957 def V_READFIRSTLANE_B32 : VOP1 <
959 (outs SReg_32:$vdst),
961 "V_READFIRSTLANE_B32 $vdst, $src0",
967 defm V_CVT_I32_F64 : VOP1_32_64 <0x00000003, "V_CVT_I32_F64",
968 [(set i32:$dst, (fp_to_sint f64:$src0))]
970 defm V_CVT_F64_I32 : VOP1_64_32 <0x00000004, "V_CVT_F64_I32",
971 [(set f64:$dst, (sint_to_fp i32:$src0))]
973 defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32",
974 [(set f32:$dst, (sint_to_fp i32:$src0))]
976 defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32",
977 [(set f32:$dst, (uint_to_fp i32:$src0))]
979 defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32",
980 [(set i32:$dst, (fp_to_uint f32:$src0))]
982 defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32",
983 [(set i32:$dst, (fp_to_sint f32:$src0))]
985 defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>;
986 ////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>;
987 //defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>;
988 //defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>;
989 //defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>;
990 //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>;
991 defm V_CVT_F32_F64 : VOP1_32_64 <0x0000000f, "V_CVT_F32_F64",
992 [(set f32:$dst, (fround f64:$src0))]
994 defm V_CVT_F64_F32 : VOP1_64_32 <0x00000010, "V_CVT_F64_F32",
995 [(set f64:$dst, (fextend f32:$src0))]
997 //defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0", []>;
998 //defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1", []>;
999 //defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2", []>;
1000 //defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", []>;
1001 //defm V_CVT_U32_F64 : VOP1_32 <0x00000015, "V_CVT_U32_F64", []>;
1002 //defm V_CVT_F64_U32 : VOP1_64 <0x00000016, "V_CVT_F64_U32", []>;
1003 defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32",
1004 [(set f32:$dst, (AMDGPUfract f32:$src0))]
1006 defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32",
1007 [(set f32:$dst, (int_AMDGPU_trunc f32:$src0))]
1009 defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32",
1010 [(set f32:$dst, (fceil f32:$src0))]
1012 defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32",
1013 [(set f32:$dst, (frint f32:$src0))]
1015 defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32",
1016 [(set f32:$dst, (ffloor f32:$src0))]
1018 defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32",
1019 [(set f32:$dst, (fexp2 f32:$src0))]
1021 defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>;
1022 defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32",
1023 [(set f32:$dst, (flog2 f32:$src0))]
1025 defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>;
1026 defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>;
1027 defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32",
1028 [(set f32:$dst, (fdiv FP_ONE, f32:$src0))]
1030 defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>;
1031 defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>;
1032 defm V_RSQ_LEGACY_F32 : VOP1_32 <
1033 0x0000002d, "V_RSQ_LEGACY_F32",
1034 [(set f32:$dst, (int_AMDGPU_rsq f32:$src0))]
1036 defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32", []>;
1037 defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64",
1038 [(set f64:$dst, (fdiv FP_ONE, f64:$src0))]
1040 defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>;
1041 defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64", []>;
1042 defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>;
1043 defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32",
1044 [(set f32:$dst, (fsqrt f32:$src0))]
1046 defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64",
1047 [(set f64:$dst, (fsqrt f64:$src0))]
1049 defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>;
1050 defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>;
1051 defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>;
1052 defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>;
1053 defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>;
1054 defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>;
1055 defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>;
1056 //defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>;
1057 defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>;
1058 defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>;
1059 //defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>;
1060 defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>;
1061 //def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>;
1062 defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>;
1063 defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>;
1064 defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>;
1067 //===----------------------------------------------------------------------===//
1068 // VINTRP Instructions
1069 //===----------------------------------------------------------------------===//
1071 def V_INTERP_P1_F32 : VINTRP <
1073 (outs VReg_32:$dst),
1074 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1075 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]",
1077 let DisableEncoding = "$m0";
1080 def V_INTERP_P2_F32 : VINTRP <
1082 (outs VReg_32:$dst),
1083 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1084 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]",
1087 let Constraints = "$src0 = $dst";
1088 let DisableEncoding = "$src0,$m0";
1092 def V_INTERP_MOV_F32 : VINTRP <
1094 (outs VReg_32:$dst),
1095 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1096 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]",
1098 let DisableEncoding = "$m0";
1101 //===----------------------------------------------------------------------===//
1102 // VOP2 Instructions
1103 //===----------------------------------------------------------------------===//
1105 def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
1106 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc),
1107 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]",
1110 let DisableEncoding = "$vcc";
1113 def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst),
1114 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2,
1115 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
1116 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg",
1117 [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))]
1120 //f32 pattern for V_CNDMASK_B32_e64
1122 (f32 (select i1:$src2, f32:$src1, f32:$src0)),
1123 (V_CNDMASK_B32_e64 $src0, $src1, $src2)
1127 (i32 (trunc i64:$val)),
1128 (EXTRACT_SUBREG $val, sub0)
1131 def V_READLANE_B32 : VOP2 <
1133 (outs SReg_32:$vdst),
1134 (ins VReg_32:$src0, SSrc_32:$vsrc1),
1135 "V_READLANE_B32 $vdst, $src0, $vsrc1",
1139 def V_WRITELANE_B32 : VOP2 <
1141 (outs VReg_32:$vdst),
1142 (ins SReg_32:$src0, SSrc_32:$vsrc1),
1143 "V_WRITELANE_B32 $vdst, $src0, $vsrc1",
1147 let isCommutable = 1 in {
1148 defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32",
1149 [(set f32:$dst, (fadd f32:$src0, f32:$src1))]
1152 defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32",
1153 [(set f32:$dst, (fsub f32:$src0, f32:$src1))]
1155 defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", [], "V_SUB_F32">;
1156 } // End isCommutable = 1
1158 defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>;
1160 let isCommutable = 1 in {
1162 defm V_MUL_LEGACY_F32 : VOP2_32 <
1163 0x00000007, "V_MUL_LEGACY_F32",
1164 [(set f32:$dst, (int_AMDGPU_mul f32:$src0, f32:$src1))]
1167 defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32",
1168 [(set f32:$dst, (fmul f32:$src0, f32:$src1))]
1172 defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24",
1173 [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))]
1175 //defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>;
1176 defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24",
1177 [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))]
1179 //defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>;
1182 defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32",
1183 [(set f32:$dst, (AMDGPUfmin f32:$src0, f32:$src1))]
1186 defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32",
1187 [(set f32:$dst, (AMDGPUfmax f32:$src0, f32:$src1))]
1190 defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>;
1191 defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>;
1192 defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32",
1193 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]>;
1194 defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32",
1195 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]>;
1196 defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32",
1197 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]>;
1198 defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32",
1199 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]>;
1201 defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32",
1202 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
1205 defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">;
1207 defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32",
1208 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
1210 defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">;
1212 let hasPostISelHook = 1 in {
1214 defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32",
1215 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
1219 defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">;
1221 defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32",
1222 [(set i32:$dst, (and i32:$src0, i32:$src1))]>;
1223 defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32",
1224 [(set i32:$dst, (or i32:$src0, i32:$src1))]
1226 defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32",
1227 [(set i32:$dst, (xor i32:$src0, i32:$src1))]
1230 } // End isCommutable = 1
1232 defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32",
1233 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))]>;
1234 defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>;
1235 defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>;
1236 defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>;
1237 //defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>;
1238 defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>;
1239 defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>;
1241 let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC
1242 // No patterns so that the scalar instructions are always selected.
1243 // The scalar versions will be replaced with vector when needed later.
1244 defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32",
1245 [(set i32:$dst, (add i32:$src0, i32:$src1))], VSrc_32>;
1246 defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32",
1247 [(set i32:$dst, (sub i32:$src0, i32:$src1))], VSrc_32>;
1248 defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], VSrc_32,
1251 let Uses = [VCC] in { // Carry-in comes from VCC
1252 defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32",
1253 [(set i32:$dst, (adde i32:$src0, i32:$src1))], VReg_32>;
1254 defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32",
1255 [(set i32:$dst, (sube i32:$src0, i32:$src1))], VReg_32>;
1256 defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], VReg_32,
1258 } // End Uses = [VCC]
1259 } // End isCommutable = 1, Defs = [VCC]
1261 defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>;
1262 ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>;
1263 ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>;
1264 ////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>;
1265 defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32",
1266 [(set i32:$dst, (int_SI_packf16 f32:$src0, f32:$src1))]
1268 ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>;
1269 ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>;
1271 //===----------------------------------------------------------------------===//
1272 // VOP3 Instructions
1273 //===----------------------------------------------------------------------===//
1275 let neverHasSideEffects = 1 in {
1277 def V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>;
1278 def V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", []>;
1279 def V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24",
1280 [(set i32:$dst, (add (AMDGPUmul_i24 i32:$src0, i32:$src1), i32:$src2))]
1282 def V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24",
1283 [(set i32:$dst, (add (AMDGPUmul_u24 i32:$src0, i32:$src1), i32:$src2))]
1286 } // End neverHasSideEffects
1287 def V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>;
1288 def V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>;
1289 def V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>;
1290 def V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>;
1292 let neverHasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
1293 def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32",
1294 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))]>;
1295 def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32",
1296 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))]>;
1299 def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32",
1300 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))]>;
1301 defm : BFIPatterns <V_BFI_B32>;
1302 def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32",
1303 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))]
1305 def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64",
1306 [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
1308 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>;
1309 def V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>;
1310 def : ROTRPattern <V_ALIGNBIT_B32>;
1312 def V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>;
1313 def V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>;
1314 ////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>;
1315 ////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>;
1316 ////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>;
1317 ////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>;
1318 ////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>;
1319 ////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>;
1320 ////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>;
1321 ////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>;
1322 ////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>;
1323 //def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>;
1324 //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>;
1325 //def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>;
1326 def V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>;
1327 ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>;
1328 def V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>;
1329 def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>;
1331 def V_LSHL_B64 : VOP3_64_Shift <0x00000161, "V_LSHL_B64",
1332 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
1334 def V_LSHR_B64 : VOP3_64_Shift <0x00000162, "V_LSHR_B64",
1335 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
1337 def V_ASHR_I64 : VOP3_64_Shift <0x00000163, "V_ASHR_I64",
1338 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
1341 let isCommutable = 1 in {
1343 def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>;
1344 def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>;
1345 def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>;
1346 def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>;
1348 } // isCommutable = 1
1351 (fadd f64:$src0, f64:$src1),
1352 (V_ADD_F64 $src0, $src1, (i64 0))
1356 (fmul f64:$src0, f64:$src1),
1357 (V_MUL_F64 $src0, $src1, (i64 0))
1360 def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>;
1362 let isCommutable = 1 in {
1364 def V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>;
1365 def V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>;
1366 def V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>;
1367 def V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>;
1369 } // isCommutable = 1
1372 (mul i32:$src0, i32:$src1),
1373 (V_MUL_LO_I32 $src0, $src1, (i32 0))
1377 (mulhu i32:$src0, i32:$src1),
1378 (V_MUL_HI_U32 $src0, $src1, (i32 0))
1382 (mulhs i32:$src0, i32:$src1),
1383 (V_MUL_HI_I32 $src0, $src1, (i32 0))
1386 def V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>;
1387 def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>;
1388 def V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>;
1389 def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>;
1390 //def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>;
1391 //def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>;
1392 //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>;
1393 def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>;
1395 //===----------------------------------------------------------------------===//
1396 // Pseudo Instructions
1397 //===----------------------------------------------------------------------===//
1399 let isCodeGenOnly = 1, isPseudo = 1 in {
1401 def V_MOV_I1 : InstSI <
1404 "", [(set i1:$dst, (imm:$src))]
1407 def LOAD_CONST : AMDGPUShaderInst <
1410 "LOAD_CONST $dst, $src",
1411 [(set GPRF32:$dst, (int_AMDGPU_load_const imm:$src))]
1414 // SI pseudo instructions. These are used by the CFG structurizer pass
1415 // and should be lowered to ISA instructions prior to codegen.
1417 let mayLoad = 1, mayStore = 1, hasSideEffects = 1,
1418 Uses = [EXEC], Defs = [EXEC] in {
1420 let usesCustomInserter = 1 in {
1422 def SI_IF_NON_TERM : InstSI <
1423 (outs SReg_64:$dst),
1424 (ins SReg_64:$vcc, brtarget:$target), "",
1425 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))]
1428 def SI_ELSE_NON_TERM : InstSI <
1429 (outs SReg_64:$dst),
1430 (ins SReg_64:$src, brtarget:$target),
1432 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]
1434 let Constraints = "$src = $dst";
1437 } // usesCustomInserter = 1
1439 let isBranch = 1, isTerminator = 1 in {
1442 (outs SReg_64:$dst),
1443 (ins SReg_64:$vcc, brtarget:$target),
1447 def SI_ELSE : InstSI <
1448 (outs SReg_64:$dst),
1449 (ins SReg_64:$src, brtarget:$target),
1452 let Constraints = "$src = $dst";
1455 def SI_LOOP : InstSI <
1457 (ins SReg_64:$saved, brtarget:$target),
1458 "SI_LOOP $saved, $target",
1459 [(int_SI_loop i64:$saved, bb:$target)]
1462 } // end isBranch = 1, isTerminator = 1
1464 def SI_BREAK : InstSI <
1465 (outs SReg_64:$dst),
1467 "SI_ELSE $dst, $src",
1468 [(set i64:$dst, (int_SI_break i64:$src))]
1471 def SI_IF_BREAK : InstSI <
1472 (outs SReg_64:$dst),
1473 (ins SReg_64:$vcc, SReg_64:$src),
1474 "SI_IF_BREAK $dst, $vcc, $src",
1475 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))]
1478 def SI_ELSE_BREAK : InstSI <
1479 (outs SReg_64:$dst),
1480 (ins SReg_64:$src0, SReg_64:$src1),
1481 "SI_ELSE_BREAK $dst, $src0, $src1",
1482 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))]
1485 def SI_END_CF : InstSI <
1487 (ins SReg_64:$saved),
1489 [(int_SI_end_cf i64:$saved)]
1492 def SI_KILL : InstSI <
1496 [(int_AMDGPU_kill f32:$src)]
1499 } // end mayLoad = 1, mayStore = 1, hasSideEffects = 1
1500 // Uses = [EXEC], Defs = [EXEC]
1502 let Uses = [EXEC], Defs = [EXEC,VCC,M0] in {
1504 //defm SI_ : RegisterLoadStore <VReg_32, FRAMEri, ADDRIndirect>;
1506 let UseNamedOperandTable = 1 in {
1508 def SI_RegisterLoad : AMDGPUShaderInst <
1509 (outs VReg_32:$dst, SReg_64:$temp),
1510 (ins FRAMEri32:$addr, i32imm:$chan),
1513 let isRegisterLoad = 1;
1517 class SIRegStore<dag outs> : AMDGPUShaderInst <
1519 (ins VReg_32:$val, FRAMEri32:$addr, i32imm:$chan),
1522 let isRegisterStore = 1;
1526 let usesCustomInserter = 1 in {
1527 def SI_RegisterStorePseudo : SIRegStore<(outs)>;
1528 } // End usesCustomInserter = 1
1529 def SI_RegisterStore : SIRegStore<(outs SReg_64:$temp)>;
1532 } // End UseNamedOperandTable = 1
1534 def SI_INDIRECT_SRC : InstSI <
1535 (outs VReg_32:$dst, SReg_64:$temp),
1536 (ins unknown:$src, VSrc_32:$idx, i32imm:$off),
1537 "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off",
1541 class SI_INDIRECT_DST<RegisterClass rc> : InstSI <
1542 (outs rc:$dst, SReg_64:$temp),
1543 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val),
1544 "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val",
1547 let Constraints = "$src = $dst";
1550 def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VReg_32>;
1551 def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
1552 def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
1553 def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
1554 def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
1556 } // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0]
1558 let usesCustomInserter = 1 in {
1560 // This pseudo instruction takes a pointer as input and outputs a resource
1561 // constant that can be used with the ADDR64 MUBUF instructions.
1562 def SI_ADDR64_RSRC : InstSI <
1563 (outs SReg_128:$srsrc),
1568 def V_SUB_F64 : InstSI <
1569 (outs VReg_64:$dst),
1570 (ins VReg_64:$src0, VReg_64:$src1),
1571 "V_SUB_F64 $dst, $src0, $src1",
1575 } // end usesCustomInserter
1577 } // end IsCodeGenOnly, isPseudo
1580 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2),
1581 (V_CNDMASK_B32_e64 $src2, $src1, (V_CMP_GT_F32_e64 0, $src0))
1586 (SI_KILL 0xbf800000)
1589 /* int_SI_vs_load_input */
1591 (SIload_input v4i32:$tlst, IMM12bit:$attr_offset, i32:$buf_idx_vgpr),
1592 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0)
1597 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
1598 f32:$src0, f32:$src1, f32:$src2, f32:$src3),
1599 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
1600 $src0, $src1, $src2, $src3)
1604 (f64 (fsub f64:$src0, f64:$src1)),
1605 (V_SUB_F64 $src0, $src1)
1608 //===----------------------------------------------------------------------===//
1610 //===----------------------------------------------------------------------===//
1612 multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
1614 // 1. Offset as 8bit DWORD immediate
1616 (constant_load (add i64:$sbase, (i64 IMM8bitDWORD:$offset))),
1617 (vt (Instr_IMM $sbase, (as_dword_i32imm $offset)))
1620 // 2. Offset loaded in an 32bit SGPR
1622 (constant_load (SIadd64bit32bit i64:$sbase, imm:$offset)),
1623 (vt (Instr_SGPR $sbase, (S_MOV_B32 imm:$offset)))
1626 // 3. No offset at all
1628 (constant_load i64:$sbase),
1629 (vt (Instr_IMM $sbase, 0))
1633 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>;
1634 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
1635 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, i64>;
1636 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>;
1637 defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>;
1638 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
1639 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>;
1640 defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
1642 // 1. Offset as 8bit DWORD immediate
1644 (SIload_constant v4i32:$sbase, IMM8bitDWORD:$offset),
1645 (S_BUFFER_LOAD_DWORD_IMM $sbase, (as_dword_i32imm $offset))
1648 // 2. Offset loaded in an 32bit SGPR
1650 (SIload_constant v4i32:$sbase, imm:$offset),
1651 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset))
1654 //===----------------------------------------------------------------------===//
1656 //===----------------------------------------------------------------------===//
1659 (i1 (and i1:$src0, i1:$src1)),
1660 (S_AND_B64 $src0, $src1)
1664 (i1 (or i1:$src0, i1:$src1)),
1665 (S_OR_B64 $src0, $src1)
1669 (i1 (xor i1:$src0, i1:$src1)),
1670 (S_XOR_B64 $src0, $src1)
1673 //===----------------------------------------------------------------------===//
1675 //===----------------------------------------------------------------------===//
1678 (or i64:$src0, i64:$src1),
1679 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1680 (V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub0),
1681 (EXTRACT_SUBREG i64:$src1, sub0)), sub0),
1682 (V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub1),
1683 (EXTRACT_SUBREG i64:$src1, sub1)), sub1)
1686 class SextInReg <ValueType vt, int ShiftAmt> : Pat <
1687 (sext_inreg i32:$src0, vt),
1688 (V_ASHRREV_I32_e32 ShiftAmt, (V_LSHLREV_B32_e32 ShiftAmt, $src0))
1691 def : SextInReg <i8, 24>;
1692 def : SextInReg <i16, 16>;
1694 /********** ======================= **********/
1695 /********** Image sampling patterns **********/
1696 /********** ======================= **********/
1698 /* SIsample for simple 1D texture lookup */
1700 (SIsample i32:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
1701 (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1704 class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1705 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
1706 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1709 class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1710 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_RECT),
1711 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1714 class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1715 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_ARRAY),
1716 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1719 class SampleShadowPattern<SDNode name, MIMG opcode,
1720 ValueType vt> : Pat <
1721 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW),
1722 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1725 class SampleShadowArrayPattern<SDNode name, MIMG opcode,
1726 ValueType vt> : Pat <
1727 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
1728 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1731 /* SIsample* for texture lookups consuming more address parameters */
1732 multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l,
1733 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b,
1734 MIMG sample_d, MIMG sample_c_d, ValueType addr_type> {
1735 def : SamplePattern <SIsample, sample, addr_type>;
1736 def : SampleRectPattern <SIsample, sample, addr_type>;
1737 def : SampleArrayPattern <SIsample, sample, addr_type>;
1738 def : SampleShadowPattern <SIsample, sample_c, addr_type>;
1739 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>;
1741 def : SamplePattern <SIsamplel, sample_l, addr_type>;
1742 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>;
1743 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>;
1744 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>;
1746 def : SamplePattern <SIsampleb, sample_b, addr_type>;
1747 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>;
1748 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>;
1749 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>;
1751 def : SamplePattern <SIsampled, sample_d, addr_type>;
1752 def : SampleArrayPattern <SIsampled, sample_d, addr_type>;
1753 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>;
1754 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>;
1757 defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2,
1758 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2,
1759 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2,
1760 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2,
1762 defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4,
1763 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4,
1764 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4,
1765 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4,
1767 defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8,
1768 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8,
1769 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8,
1770 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8,
1772 defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16,
1773 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16,
1774 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16,
1775 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16,
1778 /* int_SI_imageload for texture fetches consuming varying address parameters */
1779 class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1780 (name addr_type:$addr, v32i8:$rsrc, imm),
1781 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
1784 class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1785 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY),
1786 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
1789 class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1790 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA),
1791 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
1794 class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1795 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA),
1796 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
1799 multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> {
1800 def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>;
1801 def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>;
1804 multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> {
1805 def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>;
1806 def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>;
1809 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V2, v2i32>;
1810 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V4, v4i32>;
1812 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V2, v2i32>;
1813 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V4, v4i32>;
1815 /* Image resource information */
1817 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm),
1818 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1822 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY),
1823 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1827 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA),
1828 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1831 /********** ============================================ **********/
1832 /********** Extraction, Insertion, Building and Casting **********/
1833 /********** ============================================ **********/
1835 foreach Index = 0-2 in {
1836 def Extract_Element_v2i32_#Index : Extract_Element <
1837 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
1839 def Insert_Element_v2i32_#Index : Insert_Element <
1840 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
1843 def Extract_Element_v2f32_#Index : Extract_Element <
1844 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
1846 def Insert_Element_v2f32_#Index : Insert_Element <
1847 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
1851 foreach Index = 0-3 in {
1852 def Extract_Element_v4i32_#Index : Extract_Element <
1853 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
1855 def Insert_Element_v4i32_#Index : Insert_Element <
1856 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
1859 def Extract_Element_v4f32_#Index : Extract_Element <
1860 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
1862 def Insert_Element_v4f32_#Index : Insert_Element <
1863 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
1867 foreach Index = 0-7 in {
1868 def Extract_Element_v8i32_#Index : Extract_Element <
1869 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
1871 def Insert_Element_v8i32_#Index : Insert_Element <
1872 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
1875 def Extract_Element_v8f32_#Index : Extract_Element <
1876 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
1878 def Insert_Element_v8f32_#Index : Insert_Element <
1879 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
1883 foreach Index = 0-15 in {
1884 def Extract_Element_v16i32_#Index : Extract_Element <
1885 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
1887 def Insert_Element_v16i32_#Index : Insert_Element <
1888 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
1891 def Extract_Element_v16f32_#Index : Extract_Element <
1892 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
1894 def Insert_Element_v16f32_#Index : Insert_Element <
1895 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
1899 def : BitConvert <i32, f32, SReg_32>;
1900 def : BitConvert <i32, f32, VReg_32>;
1902 def : BitConvert <f32, i32, SReg_32>;
1903 def : BitConvert <f32, i32, VReg_32>;
1905 def : BitConvert <i64, f64, VReg_64>;
1907 def : BitConvert <f64, i64, VReg_64>;
1909 def : BitConvert <v2f32, v2i32, VReg_64>;
1910 def : BitConvert <v2i32, v2f32, VReg_64>;
1911 def : BitConvert <v2i32, i64, VReg_64>;
1912 def : BitConvert <i64, v2i32, VReg_64>;
1914 def : BitConvert <v4f32, v4i32, VReg_128>;
1915 def : BitConvert <v4i32, v4f32, VReg_128>;
1917 def : BitConvert <v8f32, v8i32, SReg_256>;
1918 def : BitConvert <v8i32, v8f32, SReg_256>;
1919 def : BitConvert <v8i32, v32i8, SReg_256>;
1920 def : BitConvert <v32i8, v8i32, SReg_256>;
1921 def : BitConvert <v8i32, v32i8, VReg_256>;
1922 def : BitConvert <v8i32, v8f32, VReg_256>;
1923 def : BitConvert <v8f32, v8i32, VReg_256>;
1924 def : BitConvert <v32i8, v8i32, VReg_256>;
1926 def : BitConvert <v16i32, v16f32, VReg_512>;
1927 def : BitConvert <v16f32, v16i32, VReg_512>;
1929 /********** =================== **********/
1930 /********** Src & Dst modifiers **********/
1931 /********** =================== **********/
1934 (int_AMDIL_clamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)),
1935 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
1936 0 /* ABS */, 1 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */)
1939 /********** ================================ **********/
1940 /********** Floating point absolute/negative **********/
1941 /********** ================================ **********/
1943 // Manipulate the sign bit directly, as e.g. using the source negation modifier
1944 // in V_ADD_F32_e64 $src, 0, [...] does not result in -0.0 for $src == +0.0,
1945 // breaking the piglit *s-floatBitsToInt-neg* tests
1947 // TODO: Look into not implementing isFNegFree/isFAbsFree for SI, and possibly
1948 // removing these patterns
1951 (fneg (fabs f32:$src)),
1952 (V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
1957 (V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff)) /* Clear sign bit */
1962 (V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Toggle sign bit */
1965 /********** ================== **********/
1966 /********** Immediate Patterns **********/
1967 /********** ================== **********/
1970 (SGPRImm<(i32 imm)>:$imm),
1971 (S_MOV_B32 imm:$imm)
1975 (SGPRImm<(f32 fpimm)>:$imm),
1976 (S_MOV_B32 fpimm:$imm)
1981 (V_MOV_B32_e32 imm:$imm)
1986 (V_MOV_B32_e32 fpimm:$imm)
1990 (i64 InlineImm<i64>:$imm),
1991 (S_MOV_B64 InlineImm<i64>:$imm)
1994 /********** ===================== **********/
1995 /********** Interpolation Paterns **********/
1996 /********** ===================== **********/
1999 (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params),
2000 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, $params)
2004 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, v2i32:$ij),
2005 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0),
2006 imm:$attr_chan, imm:$attr, i32:$params),
2007 (EXTRACT_SUBREG $ij, sub1),
2008 imm:$attr_chan, imm:$attr, $params)
2011 /********** ================== **********/
2012 /********** Intrinsic Patterns **********/
2013 /********** ================== **********/
2015 /* llvm.AMDGPU.pow */
2016 def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>;
2019 (int_AMDGPU_div f32:$src0, f32:$src1),
2020 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1))
2024 (fdiv f32:$src0, f32:$src1),
2025 (V_MUL_F32_e32 $src0, (V_RCP_F32_e32 $src1))
2029 (fdiv f64:$src0, f64:$src1),
2030 (V_MUL_F64 $src0, (V_RCP_F64_e32 $src1), (i64 0))
2035 (V_COS_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
2040 (V_SIN_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
2044 (int_AMDGPU_cube v4f32:$src),
2045 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2046 (V_CUBETC_F32 (EXTRACT_SUBREG $src, sub0),
2047 (EXTRACT_SUBREG $src, sub1),
2048 (EXTRACT_SUBREG $src, sub2)),
2050 (V_CUBESC_F32 (EXTRACT_SUBREG $src, sub0),
2051 (EXTRACT_SUBREG $src, sub1),
2052 (EXTRACT_SUBREG $src, sub2)),
2054 (V_CUBEMA_F32 (EXTRACT_SUBREG $src, sub0),
2055 (EXTRACT_SUBREG $src, sub1),
2056 (EXTRACT_SUBREG $src, sub2)),
2058 (V_CUBEID_F32 (EXTRACT_SUBREG $src, sub0),
2059 (EXTRACT_SUBREG $src, sub1),
2060 (EXTRACT_SUBREG $src, sub2)),
2065 (i32 (sext i1:$src0)),
2066 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
2069 class Ext32Pat <SDNode ext> : Pat <
2070 (i32 (ext i1:$src0)),
2071 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0)
2074 def : Ext32Pat <zext>;
2075 def : Ext32Pat <anyext>;
2077 // Offset in an 32Bit VGPR
2079 (SIload_constant v4i32:$sbase, i32:$voff),
2080 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0)
2083 // The multiplication scales from [0,1] to the unsigned integer range
2085 (AMDGPUurecip i32:$src0),
2087 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1,
2088 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
2093 (V_MBCNT_HI_U32_B32_e32 0xffffffff,
2094 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0, 0, 0, 0, 0))
2097 /********** ================== **********/
2098 /********** VOP3 Patterns **********/
2099 /********** ================== **********/
2102 (f32 (fadd (fmul f32:$src0, f32:$src1), f32:$src2)),
2103 (V_MAD_F32 $src0, $src1, $src2)
2106 /********** ======================= **********/
2107 /********** Load/Store Patterns **********/
2108 /********** ======================= **********/
2110 multiclass DSReadPat <DS inst, ValueType vt, PatFrag frag> {
2112 (vt (frag (add i32:$ptr, (i32 IMM16bit:$offset)))),
2113 (inst (i1 0), $ptr, (as_i16imm $offset))
2118 (vt (inst 0, $src0, 0))
2122 defm : DSReadPat <DS_READ_I8, i32, sextloadi8_local>;
2123 defm : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>;
2124 defm : DSReadPat <DS_READ_I16, i32, sextloadi16_local>;
2125 defm : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>;
2126 defm : DSReadPat <DS_READ_B32, i32, local_load>;
2127 defm : DSReadPat <DS_READ_B64, i64, local_load>;
2129 multiclass DSWritePat <DS inst, ValueType vt, PatFrag frag> {
2131 (frag vt:$value, (add i32:$ptr, (i32 IMM16bit:$offset))),
2132 (inst (i1 0), $ptr, $value, (as_i16imm $offset))
2136 (frag vt:$src1, i32:$src0),
2137 (inst 0, $src0, $src1, 0)
2141 defm : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>;
2142 defm : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>;
2143 defm : DSWritePat <DS_WRITE_B32, i32, local_store>;
2144 defm : DSWritePat <DS_WRITE_B64, i64, local_store>;
2146 def : Pat <(atomic_load_add_local i32:$ptr, i32:$val),
2147 (DS_ADD_U32_RTN 0, $ptr, $val, 0)>;
2149 def : Pat <(atomic_load_sub_local i32:$ptr, i32:$val),
2150 (DS_SUB_U32_RTN 0, $ptr, $val, 0)>;
2152 //===----------------------------------------------------------------------===//
2154 //===----------------------------------------------------------------------===//
2156 multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
2157 PatFrag global_ld, PatFrag constant_ld> {
2159 (vt (global_ld (mubuf_vaddr_offset i64:$ptr, i64:$offset, IMM12bit:$imm_offset))),
2160 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, (as_i16imm $imm_offset))
2164 (vt (global_ld (add i64:$ptr, (i64 IMM12bit:$offset)))),
2165 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset))
2169 (vt (global_ld i64:$ptr)),
2170 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, 0)
2174 (vt (global_ld (add i64:$ptr, i64:$offset))),
2175 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0)
2179 (vt (constant_ld (add i64:$ptr, i64:$offset))),
2180 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0)
2184 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32,
2185 sextloadi8_global, sextloadi8_constant>;
2186 defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32,
2187 az_extloadi8_global, az_extloadi8_constant>;
2188 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32,
2189 sextloadi16_global, sextloadi16_constant>;
2190 defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32,
2191 az_extloadi16_global, az_extloadi16_constant>;
2192 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32,
2193 global_load, constant_load>;
2194 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64,
2195 global_load, constant_load>;
2196 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64,
2197 az_extloadi32_global, az_extloadi32_constant>;
2198 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32,
2199 global_load, constant_load>;
2200 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32,
2201 global_load, constant_load>;
2203 multiclass MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> {
2206 (st vt:$value, (mubuf_vaddr_offset i64:$ptr, i64:$offset, IMM12bit:$imm_offset)),
2207 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, (as_i16imm $imm_offset))
2211 (st vt:$value, (add i64:$ptr, IMM12bit:$offset)),
2212 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset))
2216 (st vt:$value, i64:$ptr),
2217 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, 0)
2221 (st vt:$value, (add i64:$ptr, i64:$offset)),
2222 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, 0)
2226 defm : MUBUFStore_Pattern <BUFFER_STORE_BYTE, i32, truncstorei8_global>;
2227 defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT, i32, truncstorei16_global>;
2228 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORD, i32, global_store>;
2229 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, i64, global_store>;
2230 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, v2i32, global_store>;
2231 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4, v4i32, global_store>;
2233 // BUFFER_LOAD_DWORD*, addr64=0
2234 multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen,
2238 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2239 imm:$offset, 0, 0, imm:$glc, imm:$slc,
2241 (offset $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2242 (as_i1imm $slc), (as_i1imm $tfe))
2246 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2247 imm, 1, 0, imm:$glc, imm:$slc,
2249 (offen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
2254 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2255 imm:$offset, 0, 1, imm:$glc, imm:$slc,
2257 (idxen $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2258 (as_i1imm $slc), (as_i1imm $tfe))
2262 (vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset,
2263 imm, 1, 1, imm:$glc, imm:$slc,
2265 (bothen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
2270 defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN,
2271 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
2272 defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN,
2273 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>;
2274 defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN,
2275 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
2277 //===----------------------------------------------------------------------===//
2279 //===----------------------------------------------------------------------===//
2281 // TBUFFER_STORE_FORMAT_*, addr64=0
2282 class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat<
2283 (SItbuffer_store v4i32:$rsrc, vt:$vdata, num_channels, i32:$vaddr,
2284 i32:$soffset, imm:$inst_offset, imm:$dfmt,
2285 imm:$nfmt, imm:$offen, imm:$idxen,
2286 imm:$glc, imm:$slc, imm:$tfe),
2288 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen),
2289 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc,
2290 (as_i1imm $slc), (as_i1imm $tfe), $soffset)
2293 def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>;
2294 def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>;
2295 def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>;
2296 def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>;
2298 let Predicates = [isCI] in {
2300 // Sea island new arithmetic instructinos
2301 let neverHasSideEffects = 1 in {
2302 defm V_TRUNC_F64 : VOP1_64 <0x00000017, "V_TRUNC_F64",
2303 [(set f64:$dst, (ftrunc f64:$src0))]
2305 defm V_CEIL_F64 : VOP1_64 <0x00000018, "V_CEIL_F64",
2306 [(set f64:$dst, (fceil f64:$src0))]
2308 defm V_FLOOR_F64 : VOP1_64 <0x0000001A, "V_FLOOR_F64",
2309 [(set f64:$dst, (ffloor f64:$src0))]
2311 defm V_RNDNE_F64 : VOP1_64 <0x00000019, "V_RNDNE_F64",
2312 [(set f64:$dst, (frint f64:$src0))]
2315 def V_QSAD_PK_U16_U8 : VOP3_32 <0x00000173, "V_QSAD_PK_U16_U8", []>;
2316 def V_MQSAD_U16_U8 : VOP3_32 <0x000000172, "V_MQSAD_U16_U8", []>;
2317 def V_MQSAD_U32_U8 : VOP3_32 <0x00000175, "V_MQSAD_U32_U8", []>;
2318 def V_MAD_U64_U32 : VOP3_64 <0x00000176, "V_MAD_U64_U32", []>;
2320 // XXX - Does this set VCC?
2321 def V_MAD_I64_I32 : VOP3_64 <0x00000177, "V_MAD_I64_I32", []>;
2322 } // End neverHasSideEffects = 1
2324 // Remaining instructions:
2326 // S_CBRANCH_CDBGUSER
2327 // S_CBRANCH_CDBGSYS
2328 // S_CBRANCH_CDBGSYS_OR_USER
2329 // S_CBRANCH_CDBGSYS_AND_USER
2334 // DS_GWS_SEMA_RELEASE_ALL
2336 // DS_CNDXCHG32_RTN_B64
2339 // DS_CONDXCHG32_RTN_B128
2342 // BUFFER_LOAD_DWORDX3
2343 // BUFFER_STORE_DWORDX3
2345 } // End Predicates = [isCI]
2348 /********** ====================== **********/
2349 /********** Indirect adressing **********/
2350 /********** ====================== **********/
2352 multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, SI_INDIRECT_DST IndDst> {
2354 // 1. Extract with offset
2356 (vector_extract vt:$vec, (add i32:$idx, imm:$off)),
2357 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off))
2360 // 2. Extract without offset
2362 (vector_extract vt:$vec, i32:$idx),
2363 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0))
2366 // 3. Insert with offset
2368 (vector_insert vt:$vec, eltvt:$val, (add i32:$idx, imm:$off)),
2369 (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val)
2372 // 4. Insert without offset
2374 (vector_insert vt:$vec, eltvt:$val, i32:$idx),
2375 (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val)
2379 defm : SI_INDIRECT_Pattern <v2f32, f32, SI_INDIRECT_DST_V2>;
2380 defm : SI_INDIRECT_Pattern <v4f32, f32, SI_INDIRECT_DST_V4>;
2381 defm : SI_INDIRECT_Pattern <v8f32, f32, SI_INDIRECT_DST_V8>;
2382 defm : SI_INDIRECT_Pattern <v16f32, f32, SI_INDIRECT_DST_V16>;
2384 defm : SI_INDIRECT_Pattern <v2i32, i32, SI_INDIRECT_DST_V2>;
2385 defm : SI_INDIRECT_Pattern <v4i32, i32, SI_INDIRECT_DST_V4>;
2386 defm : SI_INDIRECT_Pattern <v8i32, i32, SI_INDIRECT_DST_V8>;
2387 defm : SI_INDIRECT_Pattern <v16i32, i32, SI_INDIRECT_DST_V16>;
2389 /********** =============== **********/
2390 /********** Conditions **********/
2391 /********** =============== **********/
2394 (i1 (setcc f32:$src0, f32:$src1, SETO)),
2395 (V_CMP_O_F32_e64 $src0, $src1)
2399 (i1 (setcc f32:$src0, f32:$src1, SETUO)),
2400 (V_CMP_U_F32_e64 $src0, $src1)
2403 //===----------------------------------------------------------------------===//
2404 // Conversion Patterns
2405 //===----------------------------------------------------------------------===//
2407 def : Pat<(i32 (sext_inreg i32:$src, i1)),
2408 (S_BFE_I32 i32:$src, 65536)>; // 0 | 1 << 16
2410 // TODO: Match 64-bit BFE. SI has a 64-bit BFE, but it's scalar only so it
2411 // might not be worth the effort, and will need to expand to shifts when
2412 // fixing SGPR copies.
2414 // Handle sext_inreg in i64
2416 (i64 (sext_inreg i64:$src, i1)),
2417 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2418 (S_BFE_I32 (EXTRACT_SUBREG i64:$src, sub0), 65536), sub0), // 0 | 1 << 16
2419 (S_MOV_B32 -1), sub1)
2423 (i64 (sext_inreg i64:$src, i8)),
2424 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2425 (S_SEXT_I32_I8 (EXTRACT_SUBREG i64:$src, sub0)), sub0),
2426 (S_MOV_B32 -1), sub1)
2430 (i64 (sext_inreg i64:$src, i16)),
2431 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2432 (S_SEXT_I32_I16 (EXTRACT_SUBREG i64:$src, sub0)), sub0),
2433 (S_MOV_B32 -1), sub1)
2436 //===----------------------------------------------------------------------===//
2437 // Miscellaneous Patterns
2438 //===----------------------------------------------------------------------===//
2441 (i32 (trunc i64:$a)),
2442 (EXTRACT_SUBREG $a, sub0)
2446 (i1 (trunc i32:$a)),
2447 (V_CMP_EQ_I32_e64 (V_AND_B32_e32 (i32 1), $a), 1)
2450 // V_ADD_I32_e32/S_ADD_I32 produces carry in VCC/SCC. For the vector
2451 // case, the sgpr-copies pass will fix this to use the vector version.
2453 (i32 (addc i32:$src0, i32:$src1)),
2454 (S_ADD_I32 $src0, $src1)
2457 //============================================================================//
2458 // Miscellaneous Optimization Patterns
2459 //============================================================================//
2461 def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e32>;
2463 } // End isSI predicate