1 //===-- SIInstructions.td - SI Instruction Defintions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This file was originally auto-generated from a GPU register header file and
10 // all the instruction definitions were originally commented out. Instructions
11 // that are not yet supported remain commented out.
12 //===----------------------------------------------------------------------===//
19 def INTERP : InterpSlots;
21 def InterpSlot : Operand<i32> {
22 let PrintMethod = "printInterpSlot";
25 def isSI : Predicate<"Subtarget.device()"
26 "->getGeneration() == AMDGPUDeviceInfo::HD7XXX">;
28 let Predicates = [isSI] in {
30 let neverHasSideEffects = 1 in {
32 let isMoveImm = 1 in {
33 def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>;
34 def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>;
35 def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>;
36 def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>;
37 } // End isMoveImm = 1
39 def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32", []>;
40 def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", []>;
41 def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>;
42 def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>;
43 def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>;
44 def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>;
45 } // End neverHasSideEffects = 1
47 ////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>;
48 ////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>;
49 ////def S_BCNT1_I32_B32 : SOP1_BCNT1 <0x0000000f, "S_BCNT1_I32_B32", []>;
50 ////def S_BCNT1_I32_B64 : SOP1_BCNT1 <0x00000010, "S_BCNT1_I32_B64", []>;
51 ////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>;
52 ////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>;
53 ////def S_FF1_I32_B32 : SOP1_FF1 <0x00000013, "S_FF1_I32_B32", []>;
54 ////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>;
55 //def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", []>;
56 //def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>;
57 def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>;
58 //def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>;
59 //def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8", []>;
60 //def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16", []>;
61 ////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>;
62 ////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>;
63 ////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>;
64 ////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>;
65 def S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>;
66 def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>;
67 def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>;
68 def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>;
70 let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in {
72 def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>;
73 def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>;
74 def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>;
75 def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>;
76 def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>;
77 def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>;
78 def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>;
79 def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>;
81 } // End hasSideEffects = 1
83 def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>;
84 def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>;
85 def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>;
86 def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>;
87 def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>;
88 def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>;
89 //def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>;
90 def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>;
91 def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>;
92 def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>;
93 def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>;
94 def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>;
97 This instruction is disabled for now until we can figure out how to teach
98 the instruction selector to correctly use the S_CMP* vs V_CMP*
101 When this instruction is enabled the code generator sometimes produces this
104 SCC = S_CMPK_EQ_I32 SGPR0, imm
106 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
108 def S_CMPK_EQ_I32 : SOPK <
109 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1),
111 [(set SCCReg:$dst, (setcc SReg_32:$src0, imm:$src1, SETEQ))]
115 let isCompare = 1 in {
116 def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>;
117 def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>;
118 def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>;
119 def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>;
120 def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>;
121 def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>;
122 def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>;
123 def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>;
124 def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>;
125 def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>;
126 def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>;
127 } // End isCompare = 1
129 def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>;
130 def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>;
131 //def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>;
132 def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>;
133 def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>;
134 def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>;
135 //def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>;
136 //def EXP : EXP_ <0x00000000, "EXP", []>;
138 let isCompare = 1 in {
140 defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">;
141 defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_LT>;
142 defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", f32, COND_EQ>;
143 defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", f32, COND_LE>;
144 defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", f32, COND_GT>;
145 defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32", f32, COND_NE>;
146 defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", f32, COND_GE>;
147 defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32">;
148 defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32">;
149 defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32">;
150 defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32">;
151 defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32">;
152 defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32">;
153 defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", f32, COND_NE>;
154 defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">;
155 defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">;
157 let hasSideEffects = 1, Defs = [EXEC] in {
159 defm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32">;
160 defm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32">;
161 defm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32">;
162 defm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32">;
163 defm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32">;
164 defm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32">;
165 defm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32">;
166 defm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32">;
167 defm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32">;
168 defm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32">;
169 defm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32">;
170 defm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32">;
171 defm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32">;
172 defm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32">;
173 defm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32">;
174 defm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32">;
176 } // End hasSideEffects = 1, Defs = [EXEC]
178 defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">;
179 defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64">;
180 defm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64">;
181 defm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64">;
182 defm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64">;
183 defm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64">;
184 defm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64">;
185 defm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64">;
186 defm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64">;
187 defm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64">;
188 defm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64">;
189 defm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64">;
190 defm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64">;
191 defm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64">;
192 defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">;
193 defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">;
195 let hasSideEffects = 1, Defs = [EXEC] in {
197 defm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64">;
198 defm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64">;
199 defm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64">;
200 defm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64">;
201 defm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64">;
202 defm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64">;
203 defm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64">;
204 defm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64">;
205 defm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64">;
206 defm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64">;
207 defm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64">;
208 defm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64">;
209 defm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64">;
210 defm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64">;
211 defm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64">;
212 defm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64">;
214 } // End hasSideEffects = 1, Defs = [EXEC]
216 defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">;
217 defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">;
218 defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32">;
219 defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32">;
220 defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32">;
221 defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32">;
222 defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32">;
223 defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32">;
224 defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32">;
225 defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32">;
226 defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32">;
227 defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32">;
228 defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32">;
229 defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">;
230 defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">;
231 defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">;
233 let hasSideEffects = 1, Defs = [EXEC] in {
235 defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32">;
236 defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32">;
237 defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32">;
238 defm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32">;
239 defm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32">;
240 defm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32">;
241 defm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32">;
242 defm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32">;
243 defm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32">;
244 defm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32">;
245 defm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32">;
246 defm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32">;
247 defm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32">;
248 defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32">;
249 defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32">;
250 defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32">;
252 } // End hasSideEffects = 1, Defs = [EXEC]
254 defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">;
255 defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">;
256 defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">;
257 defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64">;
258 defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64">;
259 defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64">;
260 defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64">;
261 defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64">;
262 defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64">;
263 defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64">;
264 defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64">;
265 defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64">;
266 defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64">;
267 defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">;
268 defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">;
269 defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">;
271 let hasSideEffects = 1, Defs = [EXEC] in {
273 defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">;
274 defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">;
275 defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">;
276 defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64">;
277 defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64">;
278 defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64">;
279 defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64">;
280 defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64">;
281 defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64">;
282 defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64">;
283 defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64">;
284 defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64">;
285 defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64">;
286 defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">;
287 defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">;
288 defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">;
290 } // End hasSideEffects = 1, Defs = [EXEC]
292 defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">;
293 defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_LT>;
294 defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>;
295 defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", i32, COND_LE>;
296 defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", i32, COND_GT>;
297 defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", i32, COND_NE>;
298 defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_GE>;
299 defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">;
301 let hasSideEffects = 1, Defs = [EXEC] in {
303 defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32">;
304 defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32">;
305 defm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32">;
306 defm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32">;
307 defm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32">;
308 defm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32">;
309 defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32">;
310 defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32">;
312 } // End hasSideEffects = 1, Defs = [EXEC]
314 defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">;
315 defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64">;
316 defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64">;
317 defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64">;
318 defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64">;
319 defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64">;
320 defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64">;
321 defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">;
323 let hasSideEffects = 1, Defs = [EXEC] in {
325 defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64">;
326 defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64">;
327 defm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64">;
328 defm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64">;
329 defm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64">;
330 defm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64">;
331 defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64">;
332 defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64">;
334 } // End hasSideEffects = 1, Defs = [EXEC]
336 defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">;
337 defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32">;
338 defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32">;
339 defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32">;
340 defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32">;
341 defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32">;
342 defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32">;
343 defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">;
345 let hasSideEffects = 1, Defs = [EXEC] in {
347 defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32">;
348 defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32">;
349 defm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32">;
350 defm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32">;
351 defm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32">;
352 defm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32">;
353 defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32">;
354 defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32">;
356 } // End hasSideEffects = 1, Defs = [EXEC]
358 defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">;
359 defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64">;
360 defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64">;
361 defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64">;
362 defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64">;
363 defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64">;
364 defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64">;
365 defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">;
367 let hasSideEffects = 1, Defs = [EXEC] in {
369 defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64">;
370 defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64">;
371 defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64">;
372 defm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64">;
373 defm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64">;
374 defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64">;
375 defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64">;
376 defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64">;
378 } // End hasSideEffects = 1, Defs = [EXEC]
380 defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">;
382 let hasSideEffects = 1, Defs = [EXEC] in {
383 defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">;
384 } // End hasSideEffects = 1, Defs = [EXEC]
386 defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">;
388 let hasSideEffects = 1, Defs = [EXEC] in {
389 defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">;
390 } // End hasSideEffects = 1, Defs = [EXEC]
392 } // End isCompare = 1
394 //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>;
395 //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>;
396 //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>;
397 def BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>;
398 //def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>;
399 //def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>;
400 //def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>;
401 //def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>;
402 //def BUFFER_LOAD_UBYTE : MUBUF_ <0x00000008, "BUFFER_LOAD_UBYTE", []>;
403 //def BUFFER_LOAD_SBYTE : MUBUF_ <0x00000009, "BUFFER_LOAD_SBYTE", []>;
404 //def BUFFER_LOAD_USHORT : MUBUF_ <0x0000000a, "BUFFER_LOAD_USHORT", []>;
405 //def BUFFER_LOAD_SSHORT : MUBUF_ <0x0000000b, "BUFFER_LOAD_SSHORT", []>;
406 //def BUFFER_LOAD_DWORD : MUBUF_ <0x0000000c, "BUFFER_LOAD_DWORD", []>;
407 //def BUFFER_LOAD_DWORDX2 : MUBUF_DWORDX2 <0x0000000d, "BUFFER_LOAD_DWORDX2", []>;
408 //def BUFFER_LOAD_DWORDX4 : MUBUF_DWORDX4 <0x0000000e, "BUFFER_LOAD_DWORDX4", []>;
409 //def BUFFER_STORE_BYTE : MUBUF_ <0x00000018, "BUFFER_STORE_BYTE", []>;
410 //def BUFFER_STORE_SHORT : MUBUF_ <0x0000001a, "BUFFER_STORE_SHORT", []>;
411 //def BUFFER_STORE_DWORD : MUBUF_ <0x0000001c, "BUFFER_STORE_DWORD", []>;
412 //def BUFFER_STORE_DWORDX2 : MUBUF_DWORDX2 <0x0000001d, "BUFFER_STORE_DWORDX2", []>;
413 //def BUFFER_STORE_DWORDX4 : MUBUF_DWORDX4 <0x0000001e, "BUFFER_STORE_DWORDX4", []>;
414 //def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>;
415 //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>;
416 //def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>;
417 //def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>;
418 //def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>;
419 //def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>;
420 //def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>;
421 //def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>;
422 //def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>;
423 //def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>;
424 //def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>;
425 //def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>;
426 //def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>;
427 //def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>;
428 //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>;
429 //def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>;
430 //def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>;
431 //def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>;
432 //def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>;
433 //def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>;
434 //def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>;
435 //def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>;
436 //def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>;
437 //def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>;
438 //def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>;
439 //def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>;
440 //def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>;
441 //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>;
442 //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>;
443 //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>;
444 //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>;
445 //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>;
446 //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>;
447 //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>;
448 //def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>;
449 //def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>;
450 //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>;
451 //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>;
452 //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>;
453 def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>;
454 //def TBUFFER_STORE_FORMAT_X : MTBUF_ <0x00000004, "TBUFFER_STORE_FORMAT_X", []>;
455 //def TBUFFER_STORE_FORMAT_XY : MTBUF_ <0x00000005, "TBUFFER_STORE_FORMAT_XY", []>;
456 //def TBUFFER_STORE_FORMAT_XYZ : MTBUF_ <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", []>;
457 //def TBUFFER_STORE_FORMAT_XYZW : MTBUF_ <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", []>;
461 defm S_LOAD_DWORD : SMRD_Helper <0x00000000, "S_LOAD_DWORD", SReg_32>;
463 //def S_LOAD_DWORDX2 : SMRD_DWORDX2 <0x00000001, "S_LOAD_DWORDX2", []>;
464 defm S_LOAD_DWORDX4 : SMRD_Helper <0x00000002, "S_LOAD_DWORDX4", SReg_128>;
465 defm S_LOAD_DWORDX8 : SMRD_Helper <0x00000003, "S_LOAD_DWORDX8", SReg_256>;
466 //def S_LOAD_DWORDX16 : SMRD_DWORDX16 <0x00000004, "S_LOAD_DWORDX16", []>;
467 //def S_BUFFER_LOAD_DWORD : SMRD_ <0x00000008, "S_BUFFER_LOAD_DWORD", []>;
468 //def S_BUFFER_LOAD_DWORDX2 : SMRD_DWORDX2 <0x00000009, "S_BUFFER_LOAD_DWORDX2", []>;
469 //def S_BUFFER_LOAD_DWORDX4 : SMRD_DWORDX4 <0x0000000a, "S_BUFFER_LOAD_DWORDX4", []>;
470 //def S_BUFFER_LOAD_DWORDX8 : SMRD_DWORDX8 <0x0000000b, "S_BUFFER_LOAD_DWORDX8", []>;
471 //def S_BUFFER_LOAD_DWORDX16 : SMRD_DWORDX16 <0x0000000c, "S_BUFFER_LOAD_DWORDX16", []>;
475 //def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>;
476 //def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>;
477 //def IMAGE_LOAD : MIMG_NoPattern_ <"IMAGE_LOAD", 0x00000000>;
478 //def IMAGE_LOAD_MIP : MIMG_NoPattern_ <"IMAGE_LOAD_MIP", 0x00000001>;
479 //def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>;
480 //def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>;
481 //def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>;
482 //def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>;
483 //def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>;
484 //def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>;
485 //def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>;
486 //def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>;
487 //def IMAGE_GET_RESINFO : MIMG_NoPattern_ <"IMAGE_GET_RESINFO", 0x0000000e>;
488 //def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>;
489 //def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>;
490 //def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>;
491 //def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>;
492 //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>;
493 //def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>;
494 //def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>;
495 //def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>;
496 //def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>;
497 //def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>;
498 //def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>;
499 //def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>;
500 //def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>;
501 //def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>;
502 //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>;
503 //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>;
504 //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>;
505 def IMAGE_SAMPLE : MIMG_Load_Helper <0x00000020, "IMAGE_SAMPLE">;
506 //def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>;
507 def IMAGE_SAMPLE_D : MIMG_Load_Helper <0x00000022, "IMAGE_SAMPLE_D">;
508 //def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>;
509 def IMAGE_SAMPLE_L : MIMG_Load_Helper <0x00000024, "IMAGE_SAMPLE_L">;
510 def IMAGE_SAMPLE_B : MIMG_Load_Helper <0x00000025, "IMAGE_SAMPLE_B">;
511 //def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>;
512 //def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>;
513 def IMAGE_SAMPLE_C : MIMG_Load_Helper <0x00000028, "IMAGE_SAMPLE_C">;
514 //def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>;
515 //def IMAGE_SAMPLE_C_D : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D", 0x0000002a>;
516 //def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>;
517 def IMAGE_SAMPLE_C_L : MIMG_Load_Helper <0x0000002c, "IMAGE_SAMPLE_C_L">;
518 def IMAGE_SAMPLE_C_B : MIMG_Load_Helper <0x0000002d, "IMAGE_SAMPLE_C_B">;
519 //def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>;
520 //def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>;
521 //def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>;
522 //def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>;
523 //def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>;
524 //def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>;
525 //def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>;
526 //def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>;
527 //def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>;
528 //def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>;
529 //def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>;
530 //def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>;
531 //def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>;
532 //def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>;
533 //def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>;
534 //def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>;
535 //def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>;
536 //def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>;
537 //def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>;
538 //def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>;
539 //def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>;
540 //def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>;
541 //def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>;
542 //def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>;
543 //def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>;
544 //def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>;
545 //def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>;
546 //def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>;
547 //def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>;
548 //def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>;
549 //def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>;
550 //def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>;
551 //def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>;
552 //def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>;
553 //def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>;
554 //def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>;
555 //def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>;
556 //def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>;
557 //def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>;
558 //def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>;
559 //def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>;
560 //def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>;
561 //def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>;
562 //def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>;
563 //def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>;
564 //def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>;
565 //def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>;
566 //def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>;
567 //def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>;
568 //def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>;
569 //def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>;
570 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>;
571 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>;
572 //def V_NOP : VOP1_ <0x00000000, "V_NOP", []>;
575 let neverHasSideEffects = 1, isMoveImm = 1 in {
576 defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>;
577 } // End neverHasSideEffects = 1, isMoveImm = 1
579 defm V_READFIRSTLANE_B32 : VOP1_32 <0x00000002, "V_READFIRSTLANE_B32", []>;
580 //defm V_CVT_I32_F64 : VOP1_32 <0x00000003, "V_CVT_I32_F64", []>;
581 //defm V_CVT_F64_I32 : VOP1_64 <0x00000004, "V_CVT_F64_I32", []>;
582 defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32",
583 [(set VReg_32:$dst, (sint_to_fp VSrc_32:$src0))]
585 //defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32", []>;
586 //defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32", []>;
587 defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32",
588 [(set (i32 VReg_32:$dst), (fp_to_sint VSrc_32:$src0))]
590 defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>;
591 ////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>;
592 //defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>;
593 //defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>;
594 //defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>;
595 //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>;
596 //defm V_CVT_F32_F64 : VOP1_32 <0x0000000f, "V_CVT_F32_F64", []>;
597 //defm V_CVT_F64_F32 : VOP1_64 <0x00000010, "V_CVT_F64_F32", []>;
598 //defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0", []>;
599 //defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1", []>;
600 //defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2", []>;
601 //defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", []>;
602 //defm V_CVT_U32_F64 : VOP1_32 <0x00000015, "V_CVT_U32_F64", []>;
603 //defm V_CVT_F64_U32 : VOP1_64 <0x00000016, "V_CVT_F64_U32", []>;
604 defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32",
605 [(set VReg_32:$dst, (AMDGPUfract VSrc_32:$src0))]
607 defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32", []>;
608 defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32",
609 [(set VReg_32:$dst, (fceil VSrc_32:$src0))]
611 defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32",
612 [(set VReg_32:$dst, (frint VSrc_32:$src0))]
614 defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32",
615 [(set VReg_32:$dst, (ffloor VSrc_32:$src0))]
617 defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32",
618 [(set VReg_32:$dst, (fexp2 VSrc_32:$src0))]
620 defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>;
621 defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32",
622 [(set VReg_32:$dst, (flog2 VSrc_32:$src0))]
624 defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>;
625 defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>;
626 defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32",
627 [(set VReg_32:$dst, (fdiv FP_ONE, VSrc_32:$src0))]
629 defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>;
630 defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>;
631 defm V_RSQ_LEGACY_F32 : VOP1_32 <
632 0x0000002d, "V_RSQ_LEGACY_F32",
633 [(set VReg_32:$dst, (int_AMDGPU_rsq VSrc_32:$src0))]
635 defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32", []>;
636 defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64", []>;
637 defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>;
638 defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64", []>;
639 defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>;
640 defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32", []>;
641 defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64", []>;
642 defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>;
643 defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>;
644 defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>;
645 defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>;
646 defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>;
647 defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>;
648 defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>;
649 //defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>;
650 defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>;
651 defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>;
652 //defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>;
653 defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>;
654 //def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>;
655 defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>;
656 defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>;
657 defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>;
659 def V_INTERP_P1_F32 : VINTRP <
662 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
663 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]",
665 let DisableEncoding = "$m0";
668 def V_INTERP_P2_F32 : VINTRP <
671 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
672 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]",
675 let Constraints = "$src0 = $dst";
676 let DisableEncoding = "$src0,$m0";
680 def V_INTERP_MOV_F32 : VINTRP <
683 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
684 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]",
686 let DisableEncoding = "$m0";
689 //def S_NOP : SOPP_ <0x00000000, "S_NOP", []>;
691 let isTerminator = 1 in {
693 def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM",
700 let isBranch = 1 in {
701 def S_BRANCH : SOPP <
702 0x00000002, (ins brtarget:$target), "S_BRANCH $target",
707 let DisableEncoding = "$scc" in {
708 def S_CBRANCH_SCC0 : SOPP <
709 0x00000004, (ins brtarget:$target, SCCReg:$scc),
710 "S_CBRANCH_SCC0 $target", []
712 def S_CBRANCH_SCC1 : SOPP <
713 0x00000005, (ins brtarget:$target, SCCReg:$scc),
714 "S_CBRANCH_SCC1 $target",
717 } // End DisableEncoding = "$scc"
719 def S_CBRANCH_VCCZ : SOPP <
720 0x00000006, (ins brtarget:$target, VCCReg:$vcc),
721 "S_CBRANCH_VCCZ $target",
724 def S_CBRANCH_VCCNZ : SOPP <
725 0x00000007, (ins brtarget:$target, VCCReg:$vcc),
726 "S_CBRANCH_VCCNZ $target",
730 let DisableEncoding = "$exec" in {
731 def S_CBRANCH_EXECZ : SOPP <
732 0x00000008, (ins brtarget:$target, EXECReg:$exec),
733 "S_CBRANCH_EXECZ $target",
736 def S_CBRANCH_EXECNZ : SOPP <
737 0x00000009, (ins brtarget:$target, EXECReg:$exec),
738 "S_CBRANCH_EXECNZ $target",
741 } // End DisableEncoding = "$exec"
744 } // End isBranch = 1
745 } // End isTerminator = 1
747 //def S_BARRIER : SOPP_ <0x0000000a, "S_BARRIER", []>;
748 let hasSideEffects = 1 in {
749 def S_WAITCNT : SOPP <0x0000000c, (ins i32imm:$simm16), "S_WAITCNT $simm16",
752 } // End hasSideEffects
753 //def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>;
754 //def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>;
755 //def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>;
756 //def S_SENDMSG : SOPP_ <0x00000010, "S_SENDMSG", []>;
757 //def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>;
758 //def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>;
759 //def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>;
760 //def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>;
761 //def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>;
762 //def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
764 def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
765 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc),
766 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]",
769 let DisableEncoding = "$vcc";
772 def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst),
773 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2,
774 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
775 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg",
776 [(set (i32 VReg_32:$dst), (select (i1 SSrc_64:$src2),
777 VSrc_32:$src1, VSrc_32:$src0))]
780 //f32 pattern for V_CNDMASK_B32_e64
782 (f32 (select (i1 SSrc_64:$src2), VSrc_32:$src1, VSrc_32:$src0)),
783 (V_CNDMASK_B32_e64 VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2)
786 defm V_READLANE_B32 : VOP2_32 <0x00000001, "V_READLANE_B32", []>;
787 defm V_WRITELANE_B32 : VOP2_32 <0x00000002, "V_WRITELANE_B32", []>;
789 let isCommutable = 1 in {
790 defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32",
791 [(set VReg_32:$dst, (fadd VSrc_32:$src0, VReg_32:$src1))]
793 } // End isCommutable = 1
795 defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32",
796 [(set VReg_32:$dst, (fsub VSrc_32:$src0, VReg_32:$src1))]
799 defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", []>;
800 defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>;
802 let isCommutable = 1 in {
804 defm V_MUL_LEGACY_F32 : VOP2_32 <
805 0x00000007, "V_MUL_LEGACY_F32",
806 [(set VReg_32:$dst, (int_AMDGPU_mul VSrc_32:$src0, VReg_32:$src1))]
809 defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32",
810 [(set VReg_32:$dst, (fmul VSrc_32:$src0, VReg_32:$src1))]
813 } // End isCommutable = 1
815 //defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24", []>;
816 //defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>;
817 //defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24", []>;
818 //defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>;
820 let isCommutable = 1 in {
822 defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32",
823 [(set VReg_32:$dst, (AMDGPUfmin VSrc_32:$src0, VReg_32:$src1))]
826 defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32",
827 [(set VReg_32:$dst, (AMDGPUfmax VSrc_32:$src0, VReg_32:$src1))]
830 defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>;
831 defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>;
832 defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32", []>;
833 defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32", []>;
834 defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32", []>;
835 defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32", []>;
837 } // End isCommutable = 1
839 defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32", []>;
840 defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", []>;
841 defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32", []>;
842 defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", []>;
843 defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32", []>;
844 defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", []>;
846 let isCommutable = 1 in {
848 defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32",
849 [(set VReg_32:$dst, (and VSrc_32:$src0, VReg_32:$src1))]
851 defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32",
852 [(set VReg_32:$dst, (or VSrc_32:$src0, VReg_32:$src1))]
854 defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32",
855 [(set VReg_32:$dst, (xor VSrc_32:$src0, VReg_32:$src1))]
858 } // End isCommutable = 1
860 defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32", []>;
861 defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>;
862 defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>;
863 defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>;
864 //defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>;
865 //defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>;
866 //defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>;
867 let Defs = [VCC] in { // Carry-out goes to VCC
869 let isCommutable = 1 in {
870 defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32",
871 [(set VReg_32:$dst, (add (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))]
873 } // End isCommutable = 1
875 defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32",
876 [(set VReg_32:$dst, (sub (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))]
879 defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", []>;
880 let Uses = [VCC] in { // Carry-out comes from VCC
881 defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", []>;
882 defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", []>;
883 defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", []>;
884 } // End Uses = [VCC]
885 } // End Defs = [VCC]
886 defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>;
887 ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>;
888 ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>;
889 ////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>;
890 defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32",
891 [(set VReg_32:$dst, (int_SI_packf16 VSrc_32:$src0, VReg_32:$src1))]
893 ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>;
894 ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>;
895 def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32", []>;
896 def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32", []>;
897 def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32", []>;
898 def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32", []>;
899 def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32", []>;
900 def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32", []>;
901 def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32", []>;
902 def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32", []>;
903 def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32", []>;
904 def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32", []>;
905 def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32", []>;
906 def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32", []>;
907 ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>;
908 ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>;
909 ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>;
910 ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>;
911 //def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>;
913 let neverHasSideEffects = 1 in {
915 def V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>;
916 def V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", []>;
917 //def V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24", []>;
918 //def V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24", []>;
920 } // End neverHasSideEffects
921 def V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>;
922 def V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>;
923 def V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>;
924 def V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>;
925 def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", []>;
926 def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", []>;
927 def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", []>;
928 def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", []>;
929 def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64", []>;
930 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>;
931 def V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>;
932 def V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>;
933 def V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>;
934 ////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>;
935 ////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>;
936 ////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>;
937 ////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>;
938 ////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>;
939 ////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>;
940 ////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>;
941 ////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>;
942 ////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>;
943 //def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>;
944 //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>;
945 //def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>;
946 def V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>;
947 ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>;
948 def V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>;
949 def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>;
950 def V_LSHL_B64 : VOP3_64 <0x00000161, "V_LSHL_B64", []>;
951 def V_LSHR_B64 : VOP3_64 <0x00000162, "V_LSHR_B64", []>;
952 def V_ASHR_I64 : VOP3_64 <0x00000163, "V_ASHR_I64", []>;
953 def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>;
954 def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>;
955 def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>;
956 def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>;
957 def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>;
958 def V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>;
959 def V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>;
960 def V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>;
962 (mul VSrc_32:$src0, VReg_32:$src1),
963 (V_MUL_LO_I32 VSrc_32:$src0, VReg_32:$src1, (i32 0), 0, 0, 0, 0)
965 def V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>;
966 def V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>;
967 def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>;
968 def V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>;
969 def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>;
970 //def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>;
971 //def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>;
972 //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>;
973 def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>;
974 def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>;
975 def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>;
976 def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32", []>;
977 def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32", []>;
978 def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32", []>;
979 def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32", []>;
980 def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32", []>;
981 def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32", []>;
982 def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32", []>;
983 def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32", []>;
985 def S_CSELECT_B32 : SOP2 <
986 0x0000000a, (outs SReg_32:$dst),
987 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32",
988 [(set (i32 SReg_32:$dst), (select (i1 SCCReg:$scc),
989 SReg_32:$src0, SReg_32:$src1))]
992 def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>;
994 // f32 pattern for S_CSELECT_B32
996 (f32 (select (i1 SCCReg:$scc), SReg_32:$src0, SReg_32:$src1)),
997 (S_CSELECT_B32 SReg_32:$src0, SReg_32:$src1, SCCReg:$scc)
1000 def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32", []>;
1002 def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64",
1003 [(set SReg_64:$dst, (i64 (and SSrc_64:$src0, SSrc_64:$src1)))]
1007 (i1 (and SSrc_64:$src0, SSrc_64:$src1)),
1008 (S_AND_B64 SSrc_64:$src0, SSrc_64:$src1)
1011 def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32", []>;
1012 def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64", []>;
1014 (i1 (or SSrc_64:$src0, SSrc_64:$src1)),
1015 (S_OR_B64 SSrc_64:$src0, SSrc_64:$src1)
1017 def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32", []>;
1018 def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64", []>;
1019 def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>;
1020 def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>;
1021 def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>;
1022 def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>;
1023 def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>;
1024 def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>;
1025 def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>;
1026 def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>;
1027 def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>;
1028 def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>;
1029 def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32", []>;
1030 def S_LSHL_B64 : SOP2_64 <0x0000001f, "S_LSHL_B64", []>;
1031 def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32", []>;
1032 def S_LSHR_B64 : SOP2_64 <0x00000021, "S_LSHR_B64", []>;
1033 def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32", []>;
1034 def S_ASHR_I64 : SOP2_64 <0x00000023, "S_ASHR_I64", []>;
1035 def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>;
1036 def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>;
1037 def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>;
1038 def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>;
1039 def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>;
1040 def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>;
1041 def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>;
1042 //def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>;
1043 def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>;
1045 let isCodeGenOnly = 1, isPseudo = 1 in {
1047 def SET_M0 : InstSI <
1048 (outs SReg_32:$dst),
1050 "SET_M0 $dst, $src0",
1051 [(set SReg_32:$dst, (int_SI_set_M0 imm:$src0))]
1054 def LOAD_CONST : AMDGPUShaderInst <
1057 "LOAD_CONST $dst, $src",
1058 [(set GPRF32:$dst, (int_AMDGPU_load_const imm:$src))]
1061 let usesCustomInserter = 1 in {
1063 def SI_INTERP : InstSI <
1064 (outs VReg_32:$dst),
1065 (ins VReg_32:$i, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, SReg_32:$params),
1066 "SI_INTERP $dst, $i, $j, $attr_chan, $attr, $params",
1070 def SI_WQM : InstSI <
1077 } // end usesCustomInserter
1079 // SI Psuedo instructions. These are used by the CFG structurizer pass
1080 // and should be lowered to ISA instructions prior to codegen.
1082 let mayLoad = 1, mayStore = 1, hasSideEffects = 1,
1083 Uses = [EXEC], Defs = [EXEC] in {
1085 let isBranch = 1, isTerminator = 1 in {
1087 def SI_IF : InstSI <
1088 (outs SReg_64:$dst),
1089 (ins SReg_64:$vcc, brtarget:$target),
1090 "SI_IF $dst, $vcc, $target",
1091 [(set SReg_64:$dst, (int_SI_if SReg_64:$vcc, bb:$target))]
1094 def SI_ELSE : InstSI <
1095 (outs SReg_64:$dst),
1096 (ins SReg_64:$src, brtarget:$target),
1097 "SI_ELSE $dst, $src, $target",
1098 [(set SReg_64:$dst, (int_SI_else SReg_64:$src, bb:$target))]> {
1100 let Constraints = "$src = $dst";
1103 def SI_LOOP : InstSI <
1105 (ins SReg_64:$saved, brtarget:$target),
1106 "SI_LOOP $saved, $target",
1107 [(int_SI_loop SReg_64:$saved, bb:$target)]
1110 } // end isBranch = 1, isTerminator = 1
1112 def SI_BREAK : InstSI <
1113 (outs SReg_64:$dst),
1115 "SI_ELSE $dst, $src",
1116 [(set SReg_64:$dst, (int_SI_break SReg_64:$src))]
1119 def SI_IF_BREAK : InstSI <
1120 (outs SReg_64:$dst),
1121 (ins SReg_64:$vcc, SReg_64:$src),
1122 "SI_IF_BREAK $dst, $vcc, $src",
1123 [(set SReg_64:$dst, (int_SI_if_break SReg_64:$vcc, SReg_64:$src))]
1126 def SI_ELSE_BREAK : InstSI <
1127 (outs SReg_64:$dst),
1128 (ins SReg_64:$src0, SReg_64:$src1),
1129 "SI_ELSE_BREAK $dst, $src0, $src1",
1130 [(set SReg_64:$dst, (int_SI_else_break SReg_64:$src0, SReg_64:$src1))]
1133 def SI_END_CF : InstSI <
1135 (ins SReg_64:$saved),
1137 [(int_SI_end_cf SReg_64:$saved)]
1140 def SI_KILL : InstSI <
1144 [(int_AMDGPU_kill VReg_32:$src)]
1147 } // end mayLoad = 1, mayStore = 1, hasSideEffects = 1
1148 // Uses = [EXEC], Defs = [EXEC]
1150 } // end IsCodeGenOnly, isPseudo
1153 (int_AMDGPU_cndlt VReg_32:$src0, VReg_32:$src1, VReg_32:$src2),
1154 (V_CNDMASK_B32_e64 VReg_32:$src2, VReg_32:$src1, (V_CMP_GT_F32_e64 0, VReg_32:$src0))
1159 (SI_KILL (V_MOV_B32_e32 0xbf800000))
1162 /* int_SI_vs_load_input */
1164 (int_SI_vs_load_input SReg_128:$tlst, IMM12bit:$attr_offset,
1165 VReg_32:$buf_idx_vgpr),
1166 (BUFFER_LOAD_FORMAT_XYZW imm:$attr_offset, 0, 1, 0, 0, 0,
1167 VReg_32:$buf_idx_vgpr, SReg_128:$tlst,
1173 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
1174 VReg_32:$src0,VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
1175 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
1176 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3)
1180 /* int_SI_sample for simple 1D texture lookup */
1182 (int_SI_sample imm:$writemask, (v1i32 VReg_32:$addr),
1183 SReg_256:$rsrc, SReg_128:$sampler, imm),
1184 (IMAGE_SAMPLE imm:$writemask, 0, 0, 0, 0, 0, 0, 0,
1185 (i32 (COPY_TO_REGCLASS VReg_32:$addr, VReg_32)),
1186 SReg_256:$rsrc, SReg_128:$sampler)
1189 class SamplePattern<Intrinsic name, MIMG opcode, RegisterClass addr_class,
1190 ValueType addr_type> : Pat <
1191 (name imm:$writemask, (addr_type addr_class:$addr),
1192 SReg_256:$rsrc, SReg_128:$sampler, imm),
1193 (opcode imm:$writemask, 0, 0, 0, 0, 0, 0, 0,
1194 (EXTRACT_SUBREG addr_class:$addr, sub0),
1195 SReg_256:$rsrc, SReg_128:$sampler)
1198 class SampleRectPattern<Intrinsic name, MIMG opcode, RegisterClass addr_class,
1199 ValueType addr_type> : Pat <
1200 (name imm:$writemask, (addr_type addr_class:$addr),
1201 SReg_256:$rsrc, SReg_128:$sampler, TEX_RECT),
1202 (opcode imm:$writemask, 1, 0, 0, 0, 0, 0, 0,
1203 (EXTRACT_SUBREG addr_class:$addr, sub0),
1204 SReg_256:$rsrc, SReg_128:$sampler)
1207 class SampleArrayPattern<Intrinsic name, MIMG opcode, RegisterClass addr_class,
1208 ValueType addr_type> : Pat <
1209 (name imm:$writemask, (addr_type addr_class:$addr),
1210 SReg_256:$rsrc, SReg_128:$sampler, TEX_ARRAY),
1211 (opcode imm:$writemask, 0, 0, 1, 0, 0, 0, 0,
1212 (EXTRACT_SUBREG addr_class:$addr, sub0),
1213 SReg_256:$rsrc, SReg_128:$sampler)
1216 class SampleShadowPattern<Intrinsic name, MIMG opcode,
1217 RegisterClass addr_class, ValueType addr_type> : Pat <
1218 (name imm:$writemask, (addr_type addr_class:$addr),
1219 SReg_256:$rsrc, SReg_128:$sampler, TEX_SHADOW),
1220 (opcode imm:$writemask, 0, 0, 0, 0, 0, 0, 0,
1221 (EXTRACT_SUBREG addr_class:$addr, sub0),
1222 SReg_256:$rsrc, SReg_128:$sampler)
1225 class SampleShadowArrayPattern<Intrinsic name, MIMG opcode,
1226 RegisterClass addr_class, ValueType addr_type> : Pat <
1227 (name imm:$writemask, (addr_type addr_class:$addr),
1228 SReg_256:$rsrc, SReg_128:$sampler, TEX_SHADOW_ARRAY),
1229 (opcode imm:$writemask, 0, 0, 1, 0, 0, 0, 0,
1230 (EXTRACT_SUBREG addr_class:$addr, sub0),
1231 SReg_256:$rsrc, SReg_128:$sampler)
1234 /* int_SI_sample* for texture lookups consuming more address parameters */
1235 multiclass SamplePatterns<RegisterClass addr_class, ValueType addr_type> {
1236 def : SamplePattern <int_SI_sample, IMAGE_SAMPLE, addr_class, addr_type>;
1237 def : SampleRectPattern <int_SI_sample, IMAGE_SAMPLE, addr_class, addr_type>;
1238 def : SampleArrayPattern <int_SI_sample, IMAGE_SAMPLE, addr_class, addr_type>;
1239 def : SampleShadowPattern <int_SI_sample, IMAGE_SAMPLE_C, addr_class, addr_type>;
1240 def : SampleShadowArrayPattern <int_SI_sample, IMAGE_SAMPLE_C, addr_class, addr_type>;
1242 def : SamplePattern <int_SI_samplel, IMAGE_SAMPLE_L, addr_class, addr_type>;
1243 def : SampleArrayPattern <int_SI_samplel, IMAGE_SAMPLE_L, addr_class, addr_type>;
1244 def : SampleShadowPattern <int_SI_samplel, IMAGE_SAMPLE_C_L, addr_class, addr_type>;
1245 def : SampleShadowArrayPattern <int_SI_samplel, IMAGE_SAMPLE_C_L, addr_class, addr_type>;
1247 def : SamplePattern <int_SI_sampleb, IMAGE_SAMPLE_B, addr_class, addr_type>;
1248 def : SampleArrayPattern <int_SI_sampleb, IMAGE_SAMPLE_B, addr_class, addr_type>;
1249 def : SampleShadowPattern <int_SI_sampleb, IMAGE_SAMPLE_C_B, addr_class, addr_type>;
1250 def : SampleShadowArrayPattern <int_SI_sampleb, IMAGE_SAMPLE_C_B, addr_class, addr_type>;
1253 defm : SamplePatterns<VReg_64, v2i32>;
1254 defm : SamplePatterns<VReg_128, v4i32>;
1255 defm : SamplePatterns<VReg_256, v8i32>;
1256 defm : SamplePatterns<VReg_512, v16i32>;
1258 def : Extract_Element <f32, v4f32, VReg_128, 0, sub0>;
1259 def : Extract_Element <f32, v4f32, VReg_128, 1, sub1>;
1260 def : Extract_Element <f32, v4f32, VReg_128, 2, sub2>;
1261 def : Extract_Element <f32, v4f32, VReg_128, 3, sub3>;
1263 def : Insert_Element <f32, v4f32, VReg_32, VReg_128, 4, sub0>;
1264 def : Insert_Element <f32, v4f32, VReg_32, VReg_128, 5, sub1>;
1265 def : Insert_Element <f32, v4f32, VReg_32, VReg_128, 6, sub2>;
1266 def : Insert_Element <f32, v4f32, VReg_32, VReg_128, 7, sub3>;
1268 def : Vector1_Build <v1i32, VReg_32, i32, VReg_32>;
1269 def : Vector2_Build <v2i32, VReg_64, i32, VReg_32>;
1270 def : Vector_Build <v4f32, VReg_128, f32, VReg_32>;
1271 def : Vector_Build <v4i32, VReg_128, i32, VReg_32>;
1272 def : Vector8_Build <v8i32, VReg_256, i32, VReg_32>;
1273 def : Vector16_Build <v16i32, VReg_512, i32, VReg_32>;
1275 def : BitConvert <i32, f32, SReg_32>;
1276 def : BitConvert <i32, f32, VReg_32>;
1278 def : BitConvert <f32, i32, SReg_32>;
1279 def : BitConvert <f32, i32, VReg_32>;
1281 /********** =================== **********/
1282 /********** Src & Dst modifiers **********/
1283 /********** =================== **********/
1286 (int_AMDIL_clamp VReg_32:$src, (f32 FP_ZERO), (f32 FP_ONE)),
1287 (V_ADD_F32_e64 VReg_32:$src, (i32 0 /* SRC1 */),
1288 0 /* ABS */, 1 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */)
1292 (fabs VReg_32:$src),
1293 (V_ADD_F32_e64 VReg_32:$src, (i32 0 /* SRC1 */),
1294 1 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */)
1298 (fneg VReg_32:$src),
1299 (V_ADD_F32_e64 VReg_32:$src, (i32 0 /* SRC1 */),
1300 0 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 1 /* NEG */)
1303 /********** ================== **********/
1304 /********** Immediate Patterns **********/
1305 /********** ================== **********/
1309 (V_MOV_B32_e32 imm:$imm)
1314 (V_MOV_B32_e32 fpimm:$imm)
1319 (S_MOV_B64 imm:$imm)
1323 (i64 InlineImm<i64>:$imm),
1324 (S_MOV_B64 InlineImm<i64>:$imm)
1327 // i64 immediates aren't supported in hardware, split it into two 32bit values
1330 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1331 (S_MOV_B32 (i32 (LO32 imm:$imm))), sub0),
1332 (S_MOV_B32 (i32 (HI32 imm:$imm))), sub1)
1335 /********** ===================== **********/
1336 /********** Interpolation Paterns **********/
1337 /********** ===================== **********/
1340 (int_SI_fs_interp_constant imm:$attr_chan, imm:$attr, M0Reg:$params),
1341 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, M0Reg:$params)
1345 (int_SI_fs_interp_linear_center imm:$attr_chan, imm:$attr, SReg_32:$params),
1346 (SI_INTERP (f32 LINEAR_CENTER_I), (f32 LINEAR_CENTER_J), imm:$attr_chan,
1347 imm:$attr, SReg_32:$params)
1351 (int_SI_fs_interp_linear_centroid imm:$attr_chan, imm:$attr, SReg_32:$params),
1352 (SI_INTERP (f32 LINEAR_CENTROID_I), (f32 LINEAR_CENTROID_J), imm:$attr_chan,
1353 imm:$attr, SReg_32:$params)
1357 (int_SI_fs_interp_persp_center imm:$attr_chan, imm:$attr, SReg_32:$params),
1358 (SI_INTERP (f32 PERSP_CENTER_I), (f32 PERSP_CENTER_J), imm:$attr_chan,
1359 imm:$attr, SReg_32:$params)
1363 (int_SI_fs_interp_persp_centroid imm:$attr_chan, imm:$attr, SReg_32:$params),
1364 (SI_INTERP (f32 PERSP_CENTROID_I), (f32 PERSP_CENTROID_J), imm:$attr_chan,
1365 imm:$attr, SReg_32:$params)
1369 (int_SI_fs_read_face),
1374 (int_SI_fs_read_pos 0),
1379 (int_SI_fs_read_pos 1),
1384 (int_SI_fs_read_pos 2),
1389 (int_SI_fs_read_pos 3),
1393 /********** ================== **********/
1394 /********** Intrinsic Patterns **********/
1395 /********** ================== **********/
1397 /* llvm.AMDGPU.pow */
1398 /* XXX: We are using IEEE MUL, not the 0 * anything = 0 MUL, is this correct? */
1399 def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_F32_e32, VReg_32>;
1402 (int_AMDGPU_div VSrc_32:$src0, VSrc_32:$src1),
1403 (V_MUL_LEGACY_F32_e32 VSrc_32:$src0, (V_RCP_LEGACY_F32_e32 VSrc_32:$src1))
1407 (fdiv VSrc_32:$src0, VSrc_32:$src1),
1408 (V_MUL_F32_e32 VSrc_32:$src0, (V_RCP_F32_e32 VSrc_32:$src1))
1412 (fcos VSrc_32:$src0),
1413 (V_COS_F32_e32 (V_MUL_F32_e32 VSrc_32:$src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
1417 (fsin VSrc_32:$src0),
1418 (V_SIN_F32_e32 (V_MUL_F32_e32 VSrc_32:$src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
1422 (int_AMDGPU_cube VReg_128:$src),
1423 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
1424 (V_CUBETC_F32 (EXTRACT_SUBREG VReg_128:$src, sub0),
1425 (EXTRACT_SUBREG VReg_128:$src, sub1),
1426 (EXTRACT_SUBREG VReg_128:$src, sub2),
1428 (V_CUBESC_F32 (EXTRACT_SUBREG VReg_128:$src, sub0),
1429 (EXTRACT_SUBREG VReg_128:$src, sub1),
1430 (EXTRACT_SUBREG VReg_128:$src, sub2),
1432 (V_CUBEMA_F32 (EXTRACT_SUBREG VReg_128:$src, sub0),
1433 (EXTRACT_SUBREG VReg_128:$src, sub1),
1434 (EXTRACT_SUBREG VReg_128:$src, sub2),
1436 (V_CUBEID_F32 (EXTRACT_SUBREG VReg_128:$src, sub0),
1437 (EXTRACT_SUBREG VReg_128:$src, sub1),
1438 (EXTRACT_SUBREG VReg_128:$src, sub2),
1443 (i32 (sext (i1 SReg_64:$src0))),
1444 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), SReg_64:$src0)
1447 /********** ================== **********/
1448 /********** VOP3 Patterns **********/
1449 /********** ================== **********/
1451 def : Pat <(f32 (fadd (fmul VSrc_32:$src0, VSrc_32:$src1), VSrc_32:$src2)),
1452 (V_MAD_F32 VSrc_32:$src0, VSrc_32:$src1, VSrc_32:$src2,
1455 /********** ================== **********/
1456 /********** SMRD Patterns **********/
1457 /********** ================== **********/
1459 multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
1460 // 1. Offset as 8bit DWORD immediate
1462 (constant_load (SIadd64bit32bit SReg_64:$sbase, IMM8bitDWORD:$offset)),
1463 (vt (Instr_IMM SReg_64:$sbase, IMM8bitDWORD:$offset))
1466 // 2. Offset loaded in an 32bit SGPR
1468 (constant_load (SIadd64bit32bit SReg_64:$sbase, imm:$offset)),
1469 (vt (Instr_SGPR SReg_64:$sbase, (S_MOV_B32 imm:$offset)))
1472 // 3. No offset at all
1474 (constant_load SReg_64:$sbase),
1475 (vt (Instr_IMM SReg_64:$sbase, 0))
1479 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>;
1480 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
1481 defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v16i8>;
1482 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
1484 } // End isSI predicate