1 //===-- SILoadStoreOptimizer.cpp ------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass tries to fuse DS instructions with close by immediate offsets.
11 // This will fuse operations such as
12 // ds_read_b32 v0, v2 offset:16
13 // ds_read_b32 v1, v2 offset:32
15 // ds_read2_b32 v[0:1], v2, offset0:4 offset1:8
18 // Future improvements:
20 // - This currently relies on the scheduler to place loads and stores next to
21 // each other, and then only merges adjacent pairs of instructions. It would
22 // be good to be more flexible with interleaved instructions, and possibly run
23 // before scheduling. It currently missing stores of constants because loading
24 // the constant into the data register is placed between the stores, although
25 // this is arguably a scheduling problem.
27 // - Live interval recomputing seems inefficient. This currently only matches
28 // one pair, and recomputes live intervals and moves on to the next pair. It
29 // would be better to compute a list of all merges that need to occur
31 // - With a list of instructions to process, we can also merge more. If a
32 // cluster of loads have offsets that are too large to fit in the 8-bit
33 // offsets, but are close enough to fit in the 8 bits, we can add to the base
34 // pointer and use the new reduced offsets.
36 //===----------------------------------------------------------------------===//
39 #include "SIInstrInfo.h"
40 #include "SIRegisterInfo.h"
41 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
42 #include "llvm/CodeGen/LiveVariables.h"
43 #include "llvm/CodeGen/MachineFunction.h"
44 #include "llvm/CodeGen/MachineFunctionPass.h"
45 #include "llvm/CodeGen/MachineInstrBuilder.h"
46 #include "llvm/CodeGen/MachineRegisterInfo.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Target/TargetMachine.h"
52 #define DEBUG_TYPE "si-load-store-opt"
56 class SILoadStoreOptimizer : public MachineFunctionPass {
58 const TargetMachine *TM;
59 const SIInstrInfo *TII;
60 const SIRegisterInfo *TRI;
61 MachineRegisterInfo *MRI;
65 static bool offsetsCanBeCombined(unsigned Offset0,
69 MachineBasicBlock::iterator findMatchingDSInst(MachineBasicBlock::iterator I,
72 void updateRegDefsUses(unsigned SrcReg,
76 MachineBasicBlock::iterator mergeRead2Pair(
77 MachineBasicBlock::iterator I,
78 MachineBasicBlock::iterator Paired,
81 MachineBasicBlock::iterator mergeWrite2Pair(
82 MachineBasicBlock::iterator I,
83 MachineBasicBlock::iterator Paired,
89 SILoadStoreOptimizer() :
90 MachineFunctionPass(ID),
99 SILoadStoreOptimizer(const TargetMachine &TM_) :
100 MachineFunctionPass(ID),
102 TII(static_cast<const SIInstrInfo*>(TM->getSubtargetImpl()->getInstrInfo())) {
103 initializeSILoadStoreOptimizerPass(*PassRegistry::getPassRegistry());
106 bool optimizeBlock(MachineBasicBlock &MBB);
108 bool runOnMachineFunction(MachineFunction &MF) override;
110 const char *getPassName() const override {
111 return "SI Load / Store Optimizer";
114 void getAnalysisUsage(AnalysisUsage &AU) const override {
115 AU.setPreservesCFG();
116 AU.addPreserved<SlotIndexes>();
117 AU.addPreserved<LiveIntervals>();
118 AU.addPreserved<LiveVariables>();
119 AU.addRequired<LiveIntervals>();
121 MachineFunctionPass::getAnalysisUsage(AU);
125 } // End anonymous namespace.
127 INITIALIZE_PASS_BEGIN(SILoadStoreOptimizer, DEBUG_TYPE,
128 "SI Load / Store Optimizer", false, false)
129 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
130 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
131 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
132 INITIALIZE_PASS_END(SILoadStoreOptimizer, DEBUG_TYPE,
133 "SI Load / Store Optimizer", false, false)
135 char SILoadStoreOptimizer::ID = 0;
137 char &llvm::SILoadStoreOptimizerID = SILoadStoreOptimizer::ID;
139 FunctionPass *llvm::createSILoadStoreOptimizerPass(TargetMachine &TM) {
140 return new SILoadStoreOptimizer(TM);
143 bool SILoadStoreOptimizer::offsetsCanBeCombined(unsigned Offset0,
146 // XXX - Would the same offset be OK? Is there any reason this would happen or
148 if (Offset0 == Offset1)
151 // This won't be valid if the offset isn't aligned.
152 if ((Offset0 % Size != 0) || (Offset1 % Size != 0))
155 unsigned EltOffset0 = Offset0 / Size;
156 unsigned EltOffset1 = Offset1 / Size;
158 // Check if the new offsets fit in the reduced 8-bit range.
159 if (isUInt<8>(EltOffset0) && isUInt<8>(EltOffset1))
162 // If the offset in elements doesn't fit in 8-bits, we might be able to use
163 // the stride 64 versions.
164 if ((EltOffset0 % 64 != 0) || (EltOffset1 % 64) != 0)
167 return isUInt<8>(EltOffset0 / 64) && isUInt<8>(EltOffset1 / 64);
170 MachineBasicBlock::iterator
171 SILoadStoreOptimizer::findMatchingDSInst(MachineBasicBlock::iterator I,
173 MachineBasicBlock::iterator E = I->getParent()->end();
174 MachineBasicBlock::iterator MBBI = I;
177 if (MBBI->getOpcode() != I->getOpcode())
180 // Don't merge volatiles.
181 if (MBBI->hasOrderedMemoryRef())
184 int AddrIdx = AMDGPU::getNamedOperandIdx(I->getOpcode(), AMDGPU::OpName::addr);
185 const MachineOperand &AddrReg0 = I->getOperand(AddrIdx);
186 const MachineOperand &AddrReg1 = MBBI->getOperand(AddrIdx);
188 // Check same base pointer. Be careful of subregisters, which can occur with
189 // vectors of pointers.
190 if (AddrReg0.getReg() == AddrReg1.getReg() &&
191 AddrReg0.getSubReg() == AddrReg1.getSubReg()) {
192 int OffsetIdx = AMDGPU::getNamedOperandIdx(I->getOpcode(),
193 AMDGPU::OpName::offset);
194 unsigned Offset0 = I->getOperand(OffsetIdx).getImm() & 0xffff;
195 unsigned Offset1 = MBBI->getOperand(OffsetIdx).getImm() & 0xffff;
197 // Check both offsets fit in the reduced range.
198 if (offsetsCanBeCombined(Offset0, Offset1, EltSize))
205 void SILoadStoreOptimizer::updateRegDefsUses(unsigned SrcReg,
208 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg),
209 E = MRI->reg_end(); I != E; ) {
210 MachineOperand &O = *I;
212 O.substVirtReg(DstReg, SubIdx, *TRI);
216 MachineBasicBlock::iterator SILoadStoreOptimizer::mergeRead2Pair(
217 MachineBasicBlock::iterator I,
218 MachineBasicBlock::iterator Paired,
220 MachineBasicBlock *MBB = I->getParent();
222 // Be careful, since the addresses could be subregisters themselves in weird
223 // cases, like vectors of pointers.
224 const MachineOperand *AddrReg = TII->getNamedOperand(*I, AMDGPU::OpName::addr);
225 const MachineOperand *M0Reg = TII->getNamedOperand(*I, AMDGPU::OpName::m0);
227 unsigned DestReg0 = TII->getNamedOperand(*I, AMDGPU::OpName::vdst)->getReg();
229 = TII->getNamedOperand(*Paired, AMDGPU::OpName::vdst)->getReg();
232 = TII->getNamedOperand(*I, AMDGPU::OpName::offset)->getImm() & 0xffff;
234 = TII->getNamedOperand(*Paired, AMDGPU::OpName::offset)->getImm() & 0xffff;
236 unsigned NewOffset0 = Offset0 / EltSize;
237 unsigned NewOffset1 = Offset1 / EltSize;
238 unsigned Opc = (EltSize == 4) ? AMDGPU::DS_READ2_B32 : AMDGPU::DS_READ2_B64;
240 // Prefer the st64 form if we can use it, even if we can fit the offset in the
241 // non st64 version. I'm not sure if there's any real reason to do this.
242 bool UseST64 = (NewOffset0 % 64 == 0) && (NewOffset1 % 64 == 0);
246 Opc = (EltSize == 4) ? AMDGPU::DS_READ2ST64_B32 : AMDGPU::DS_READ2ST64_B64;
249 assert((isUInt<8>(NewOffset0) && isUInt<8>(NewOffset1)) &&
250 (NewOffset0 != NewOffset1) &&
251 "Computed offset doesn't fit");
253 const MCInstrDesc &Read2Desc = TII->get(Opc);
255 const TargetRegisterClass *SuperRC
256 = (EltSize == 4) ? &AMDGPU::VReg_64RegClass : &AMDGPU::VReg_128RegClass;
257 unsigned DestReg = MRI->createVirtualRegister(SuperRC);
259 DebugLoc DL = I->getDebugLoc();
260 MachineInstrBuilder Read2
261 = BuildMI(*MBB, I, DL, Read2Desc, DestReg)
263 .addOperand(*AddrReg) // addr
264 .addImm(NewOffset0) // offset0
265 .addImm(NewOffset1) // offset1
266 .addOperand(*M0Reg) // M0
267 .addMemOperand(*I->memoperands_begin())
268 .addMemOperand(*Paired->memoperands_begin());
270 LIS->InsertMachineInstrInMaps(Read2);
272 unsigned SubRegIdx0 = (EltSize == 4) ? AMDGPU::sub0 : AMDGPU::sub0_sub1;
273 unsigned SubRegIdx1 = (EltSize == 4) ? AMDGPU::sub1 : AMDGPU::sub2_sub3;
274 updateRegDefsUses(DestReg0, DestReg, SubRegIdx0);
275 updateRegDefsUses(DestReg1, DestReg, SubRegIdx1);
277 LIS->RemoveMachineInstrFromMaps(I);
278 LIS->RemoveMachineInstrFromMaps(Paired);
279 I->eraseFromParent();
280 Paired->eraseFromParent();
282 LiveInterval &AddrRegLI = LIS->getInterval(AddrReg->getReg());
283 LIS->shrinkToUses(&AddrRegLI);
285 LiveInterval &M0RegLI = LIS->getInterval(M0Reg->getReg());
286 LIS->shrinkToUses(&M0RegLI);
288 // Currently m0 is treated as a register class with one member instead of an
289 // implicit physical register. We are using the virtual register for the first
290 // one, but we still need to update the live range of the now unused second m0
291 // virtual register to avoid verifier errors.
292 const MachineOperand *PairedM0Reg
293 = TII->getNamedOperand(*Paired, AMDGPU::OpName::m0);
294 LiveInterval &PairedM0RegLI = LIS->getInterval(PairedM0Reg->getReg());
295 LIS->shrinkToUses(&PairedM0RegLI);
297 LIS->getInterval(DestReg); // Create new LI
299 DEBUG(dbgs() << "Inserted read2: " << *Read2 << '\n');
300 return Read2.getInstr();
303 MachineBasicBlock::iterator SILoadStoreOptimizer::mergeWrite2Pair(
304 MachineBasicBlock::iterator I,
305 MachineBasicBlock::iterator Paired,
307 MachineBasicBlock *MBB = I->getParent();
309 // Be sure to use .addOperand(), and not .addReg() with these. We want to be
310 // sure we preserve the subregister index and any register flags set on them.
311 const MachineOperand *Addr = TII->getNamedOperand(*I, AMDGPU::OpName::addr);
312 const MachineOperand *M0Reg = TII->getNamedOperand(*I, AMDGPU::OpName::m0);
313 const MachineOperand *Data0 = TII->getNamedOperand(*I, AMDGPU::OpName::data0);
314 const MachineOperand *Data1
315 = TII->getNamedOperand(*Paired, AMDGPU::OpName::data0);
319 = TII->getNamedOperand(*I, AMDGPU::OpName::offset)->getImm() & 0xffff;
321 = TII->getNamedOperand(*Paired, AMDGPU::OpName::offset)->getImm() & 0xffff;
323 unsigned NewOffset0 = Offset0 / EltSize;
324 unsigned NewOffset1 = Offset1 / EltSize;
325 unsigned Opc = (EltSize == 4) ? AMDGPU::DS_WRITE2_B32 : AMDGPU::DS_WRITE2_B64;
327 // Prefer the st64 form if we can use it, even if we can fit the offset in the
328 // non st64 version. I'm not sure if there's any real reason to do this.
329 bool UseST64 = (NewOffset0 % 64 == 0) && (NewOffset1 % 64 == 0);
333 Opc = (EltSize == 4) ? AMDGPU::DS_WRITE2ST64_B32 : AMDGPU::DS_WRITE2ST64_B64;
336 assert((isUInt<8>(NewOffset0) && isUInt<8>(NewOffset1)) &&
337 (NewOffset0 != NewOffset1) &&
338 "Computed offset doesn't fit");
340 const MCInstrDesc &Write2Desc = TII->get(Opc);
341 DebugLoc DL = I->getDebugLoc();
343 MachineInstrBuilder Write2
344 = BuildMI(*MBB, I, DL, Write2Desc)
346 .addOperand(*Addr) // addr
347 .addOperand(*Data0) // data0
348 .addOperand(*Data1) // data1
349 .addImm(NewOffset0) // offset0
350 .addImm(NewOffset1) // offset1
351 .addOperand(*M0Reg) // m0
352 .addMemOperand(*I->memoperands_begin())
353 .addMemOperand(*Paired->memoperands_begin());
355 // XXX - How do we express subregisters here?
356 unsigned OrigRegs[] = { Data0->getReg(), Data1->getReg(), Addr->getReg(),
359 LIS->RemoveMachineInstrFromMaps(I);
360 LIS->RemoveMachineInstrFromMaps(Paired);
361 I->eraseFromParent();
362 Paired->eraseFromParent();
364 LIS->repairIntervalsInRange(MBB, Write2, Write2, OrigRegs);
366 DEBUG(dbgs() << "Inserted write2 inst: " << *Write2 << '\n');
367 return Write2.getInstr();
370 // Scan through looking for adjacent LDS operations with constant offsets from
371 // the same base register. We rely on the scheduler to do the hard work of
372 // clustering nearby loads, and assume these are all adjacent.
373 bool SILoadStoreOptimizer::optimizeBlock(MachineBasicBlock &MBB) {
374 bool Modified = false;
376 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;) {
377 MachineInstr &MI = *I;
379 // Don't combine if volatile.
380 if (MI.hasOrderedMemoryRef()) {
385 unsigned Opc = MI.getOpcode();
386 if (Opc == AMDGPU::DS_READ_B32 || Opc == AMDGPU::DS_READ_B64) {
387 unsigned Size = (Opc == AMDGPU::DS_READ_B64) ? 8 : 4;
388 MachineBasicBlock::iterator Match = findMatchingDSInst(I, Size);
391 I = mergeRead2Pair(I, Match, Size);
397 } else if (Opc == AMDGPU::DS_WRITE_B32 || Opc == AMDGPU::DS_WRITE_B64) {
398 unsigned Size = (Opc == AMDGPU::DS_WRITE_B64) ? 8 : 4;
399 MachineBasicBlock::iterator Match = findMatchingDSInst(I, Size);
402 I = mergeWrite2Pair(I, Match, Size);
416 bool SILoadStoreOptimizer::runOnMachineFunction(MachineFunction &MF) {
417 const TargetSubtargetInfo *STM = MF.getTarget().getSubtargetImpl();
418 TRI = static_cast<const SIRegisterInfo*>(STM->getRegisterInfo());
419 TII = static_cast<const SIInstrInfo*>(STM->getInstrInfo());
420 MRI = &MF.getRegInfo();
422 LIS = &getAnalysis<LiveIntervals>();
424 DEBUG(dbgs() << "Running SILoadStoreOptimizer\n");
426 assert(!MRI->isSSA());
428 bool Modified = false;
430 for (MachineBasicBlock &MBB : MF)
431 Modified |= optimizeBlock(MBB);