1 //===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This pass lowers the pseudo control flow instructions to real
12 /// machine instructions.
14 /// All control flow is handled using predicated instructions and
15 /// a predicate stack. Each Scalar ALU controls the operations of 64 Vector
16 /// ALUs. The Scalar ALU can update the predicate for any of the Vector ALUs
17 /// by writting to the 64-bit EXEC register (each bit corresponds to a
18 /// single vector ALU). Typically, for predicates, a vector ALU will write
19 /// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
20 /// Vector ALU) and then the ScalarALU will AND the VCC register with the
21 /// EXEC to update the predicates.
24 /// %VCC = V_CMP_GT_F32 %VGPR1, %VGPR2
25 /// %SGPR0 = SI_IF %VCC
26 /// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0
27 /// %SGPR0 = SI_ELSE %SGPR0
28 /// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR0
33 /// %SGPR0 = S_AND_SAVEEXEC_B64 %VCC // Save and update the exec mask
34 /// %SGPR0 = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
35 /// S_CBRANCH_EXECZ label0 // This instruction is an optional
36 /// // optimization which allows us to
37 /// // branch if all the bits of
39 /// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0 // Do the IF block of the branch
42 /// %SGPR0 = S_OR_SAVEEXEC_B64 %EXEC // Restore the exec mask for the Then block
43 /// %EXEC = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
44 /// S_BRANCH_EXECZ label1 // Use our branch optimization
45 /// // instruction again.
46 /// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR // Do the THEN block
48 /// %EXEC = S_OR_B64 %EXEC, %SGPR0 // Re-enable saved exec mask bits
49 //===----------------------------------------------------------------------===//
52 #include "SIInstrInfo.h"
53 #include "SIMachineFunctionInfo.h"
54 #include "llvm/CodeGen/MachineFunction.h"
55 #include "llvm/CodeGen/MachineFunctionPass.h"
56 #include "llvm/CodeGen/MachineInstrBuilder.h"
57 #include "llvm/CodeGen/MachineRegisterInfo.h"
63 class SILowerControlFlowPass : public MachineFunctionPass {
66 static const unsigned SkipThreshold = 12;
69 const TargetInstrInfo *TII;
71 void Skip(MachineInstr &MI, MachineOperand &To);
73 void If(MachineInstr &MI);
74 void Else(MachineInstr &MI);
75 void Break(MachineInstr &MI);
76 void IfBreak(MachineInstr &MI);
77 void ElseBreak(MachineInstr &MI);
78 void Loop(MachineInstr &MI);
79 void EndCf(MachineInstr &MI);
81 void Branch(MachineInstr &MI);
84 SILowerControlFlowPass(TargetMachine &tm) :
85 MachineFunctionPass(ID), TII(tm.getInstrInfo()) { }
87 virtual bool runOnMachineFunction(MachineFunction &MF);
89 const char *getPassName() const {
90 return "SI Lower control flow instructions";
95 } // End anonymous namespace
97 char SILowerControlFlowPass::ID = 0;
99 FunctionPass *llvm::createSILowerControlFlowPass(TargetMachine &tm) {
100 return new SILowerControlFlowPass(tm);
103 void SILowerControlFlowPass::Skip(MachineInstr &From, MachineOperand &To) {
104 unsigned NumInstr = 0;
106 for (MachineBasicBlock *MBB = *From.getParent()->succ_begin();
107 NumInstr < SkipThreshold && MBB != To.getMBB() && !MBB->succ_empty();
108 MBB = *MBB->succ_begin()) {
110 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
111 NumInstr < SkipThreshold && I != E; ++I) {
113 if (I->isBundle() || !I->isBundled())
118 if (NumInstr < SkipThreshold)
121 DebugLoc DL = From.getDebugLoc();
122 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
124 .addReg(AMDGPU::EXEC);
127 void SILowerControlFlowPass::If(MachineInstr &MI) {
128 MachineBasicBlock &MBB = *MI.getParent();
129 DebugLoc DL = MI.getDebugLoc();
130 unsigned Reg = MI.getOperand(0).getReg();
131 unsigned Vcc = MI.getOperand(1).getReg();
133 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
136 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
137 .addReg(AMDGPU::EXEC)
140 Skip(MI, MI.getOperand(2));
142 MI.eraseFromParent();
145 void SILowerControlFlowPass::Else(MachineInstr &MI) {
146 MachineBasicBlock &MBB = *MI.getParent();
147 DebugLoc DL = MI.getDebugLoc();
148 unsigned Dst = MI.getOperand(0).getReg();
149 unsigned Src = MI.getOperand(1).getReg();
151 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
152 .addReg(Src); // Saved EXEC
154 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
155 .addReg(AMDGPU::EXEC)
158 Skip(MI, MI.getOperand(2));
160 MI.eraseFromParent();
163 void SILowerControlFlowPass::Break(MachineInstr &MI) {
164 MachineBasicBlock &MBB = *MI.getParent();
165 DebugLoc DL = MI.getDebugLoc();
167 unsigned Dst = MI.getOperand(0).getReg();
168 unsigned Src = MI.getOperand(1).getReg();
170 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
171 .addReg(AMDGPU::EXEC)
174 MI.eraseFromParent();
177 void SILowerControlFlowPass::IfBreak(MachineInstr &MI) {
178 MachineBasicBlock &MBB = *MI.getParent();
179 DebugLoc DL = MI.getDebugLoc();
181 unsigned Dst = MI.getOperand(0).getReg();
182 unsigned Vcc = MI.getOperand(1).getReg();
183 unsigned Src = MI.getOperand(2).getReg();
185 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
189 MI.eraseFromParent();
192 void SILowerControlFlowPass::ElseBreak(MachineInstr &MI) {
193 MachineBasicBlock &MBB = *MI.getParent();
194 DebugLoc DL = MI.getDebugLoc();
196 unsigned Dst = MI.getOperand(0).getReg();
197 unsigned Saved = MI.getOperand(1).getReg();
198 unsigned Src = MI.getOperand(2).getReg();
200 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
204 MI.eraseFromParent();
207 void SILowerControlFlowPass::Loop(MachineInstr &MI) {
208 MachineBasicBlock &MBB = *MI.getParent();
209 DebugLoc DL = MI.getDebugLoc();
210 unsigned Src = MI.getOperand(0).getReg();
212 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ANDN2_B64), AMDGPU::EXEC)
213 .addReg(AMDGPU::EXEC)
216 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
217 .addOperand(MI.getOperand(1))
218 .addReg(AMDGPU::EXEC);
220 MI.eraseFromParent();
223 void SILowerControlFlowPass::EndCf(MachineInstr &MI) {
224 MachineBasicBlock &MBB = *MI.getParent();
225 DebugLoc DL = MI.getDebugLoc();
226 unsigned Reg = MI.getOperand(0).getReg();
228 BuildMI(MBB, MBB.getFirstNonPHI(), DL,
229 TII->get(AMDGPU::S_OR_B64), AMDGPU::EXEC)
230 .addReg(AMDGPU::EXEC)
233 MI.eraseFromParent();
236 void SILowerControlFlowPass::Branch(MachineInstr &MI) {
237 MachineBasicBlock *Next = MI.getParent()->getNextNode();
238 MachineBasicBlock *Target = MI.getOperand(0).getMBB();
240 MI.eraseFromParent();
245 bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
248 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
251 MachineBasicBlock &MBB = *BI;
252 for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
253 I != MBB.end(); I = Next) {
255 Next = llvm::next(I);
256 MachineInstr &MI = *I;
257 switch (MI.getOpcode()) {
263 case AMDGPU::SI_ELSE:
267 case AMDGPU::SI_BREAK:
271 case AMDGPU::SI_IF_BREAK:
275 case AMDGPU::SI_ELSE_BREAK:
279 case AMDGPU::SI_LOOP:
283 case AMDGPU::SI_END_CF:
288 case AMDGPU::S_BRANCH:
295 // TODO: What is this good for?
296 unsigned ShaderType = MF.getInfo<SIMachineFunctionInfo>()->ShaderType;
297 if (HaveCf && ShaderType == ShaderType::PIXEL) {
298 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
301 MachineBasicBlock &MBB = *BI;
302 if (MBB.succ_empty()) {
304 MachineInstr &MI = *MBB.getFirstNonPHI();
305 DebugLoc DL = MI.getDebugLoc();
307 // If the exec mask is non-zero, skip the next two instructions
308 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
310 .addReg(AMDGPU::EXEC);
312 // Exec mask is zero: Export to NULL target...
313 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::EXP))
315 .addImm(0x09) // V_008DFC_SQ_EXP_NULL
319 .addReg(AMDGPU::SREG_LIT_0)
320 .addReg(AMDGPU::SREG_LIT_0)
321 .addReg(AMDGPU::SREG_LIT_0)
322 .addReg(AMDGPU::SREG_LIT_0);
324 // ... and terminate wavefront
325 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ENDPGM));