1 //===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This pass lowers the pseudo control flow instructions to real
12 /// machine instructions.
14 /// All control flow is handled using predicated instructions and
15 /// a predicate stack. Each Scalar ALU controls the operations of 64 Vector
16 /// ALUs. The Scalar ALU can update the predicate for any of the Vector ALUs
17 /// by writting to the 64-bit EXEC register (each bit corresponds to a
18 /// single vector ALU). Typically, for predicates, a vector ALU will write
19 /// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
20 /// Vector ALU) and then the ScalarALU will AND the VCC register with the
21 /// EXEC to update the predicates.
24 /// %VCC = V_CMP_GT_F32 %VGPR1, %VGPR2
25 /// %SGPR0 = SI_IF %VCC
26 /// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0
27 /// %SGPR0 = SI_ELSE %SGPR0
28 /// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR0
33 /// %SGPR0 = S_AND_SAVEEXEC_B64 %VCC // Save and update the exec mask
34 /// %SGPR0 = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
35 /// S_CBRANCH_EXECZ label0 // This instruction is an optional
36 /// // optimization which allows us to
37 /// // branch if all the bits of
39 /// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0 // Do the IF block of the branch
42 /// %SGPR0 = S_OR_SAVEEXEC_B64 %EXEC // Restore the exec mask for the Then block
43 /// %EXEC = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
44 /// S_BRANCH_EXECZ label1 // Use our branch optimization
45 /// // instruction again.
46 /// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR // Do the THEN block
48 /// %EXEC = S_OR_B64 %EXEC, %SGPR0 // Re-enable saved exec mask bits
49 //===----------------------------------------------------------------------===//
52 #include "SIInstrInfo.h"
53 #include "SIMachineFunctionInfo.h"
54 #include "llvm/CodeGen/MachineFunction.h"
55 #include "llvm/CodeGen/MachineFunctionPass.h"
56 #include "llvm/CodeGen/MachineInstrBuilder.h"
57 #include "llvm/CodeGen/MachineRegisterInfo.h"
63 class SILowerControlFlowPass : public MachineFunctionPass {
66 static const unsigned SkipThreshold = 12;
69 const TargetInstrInfo *TII;
71 void Skip(MachineInstr &MI, MachineOperand &To);
73 void If(MachineInstr &MI);
74 void Else(MachineInstr &MI);
75 void Break(MachineInstr &MI);
76 void IfBreak(MachineInstr &MI);
77 void ElseBreak(MachineInstr &MI);
78 void Loop(MachineInstr &MI);
79 void EndCf(MachineInstr &MI);
81 void Branch(MachineInstr &MI);
84 SILowerControlFlowPass(TargetMachine &tm) :
85 MachineFunctionPass(ID), TII(tm.getInstrInfo()) { }
87 virtual bool runOnMachineFunction(MachineFunction &MF);
89 const char *getPassName() const {
90 return "SI Lower control flow instructions";
95 } // End anonymous namespace
97 char SILowerControlFlowPass::ID = 0;
99 FunctionPass *llvm::createSILowerControlFlowPass(TargetMachine &tm) {
100 return new SILowerControlFlowPass(tm);
103 void SILowerControlFlowPass::Skip(MachineInstr &From, MachineOperand &To) {
105 unsigned NumInstr = 0;
107 for (MachineBasicBlock *MBB = *From.getParent()->succ_begin();
108 NumInstr < SkipThreshold && MBB != To.getMBB() && !MBB->succ_empty();
109 MBB = *MBB->succ_begin()) {
111 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
112 NumInstr < SkipThreshold && I != E; ++I) {
114 if (I->isBundle() || !I->isBundled())
119 if (NumInstr < SkipThreshold)
122 DebugLoc DL = From.getDebugLoc();
123 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
125 .addReg(AMDGPU::EXEC);
128 void SILowerControlFlowPass::If(MachineInstr &MI) {
130 MachineBasicBlock &MBB = *MI.getParent();
131 DebugLoc DL = MI.getDebugLoc();
132 unsigned Reg = MI.getOperand(0).getReg();
133 unsigned Vcc = MI.getOperand(1).getReg();
135 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
138 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
139 .addReg(AMDGPU::EXEC)
142 Skip(MI, MI.getOperand(2));
144 MI.eraseFromParent();
147 void SILowerControlFlowPass::Else(MachineInstr &MI) {
149 MachineBasicBlock &MBB = *MI.getParent();
150 DebugLoc DL = MI.getDebugLoc();
151 unsigned Dst = MI.getOperand(0).getReg();
152 unsigned Src = MI.getOperand(1).getReg();
154 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
155 .addReg(Src); // Saved EXEC
157 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
158 .addReg(AMDGPU::EXEC)
161 Skip(MI, MI.getOperand(2));
163 MI.eraseFromParent();
166 void SILowerControlFlowPass::Break(MachineInstr &MI) {
168 MachineBasicBlock &MBB = *MI.getParent();
169 DebugLoc DL = MI.getDebugLoc();
171 unsigned Dst = MI.getOperand(0).getReg();
172 unsigned Src = MI.getOperand(1).getReg();
174 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
175 .addReg(AMDGPU::EXEC)
178 MI.eraseFromParent();
181 void SILowerControlFlowPass::IfBreak(MachineInstr &MI) {
183 MachineBasicBlock &MBB = *MI.getParent();
184 DebugLoc DL = MI.getDebugLoc();
186 unsigned Dst = MI.getOperand(0).getReg();
187 unsigned Vcc = MI.getOperand(1).getReg();
188 unsigned Src = MI.getOperand(2).getReg();
190 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
194 MI.eraseFromParent();
197 void SILowerControlFlowPass::ElseBreak(MachineInstr &MI) {
199 MachineBasicBlock &MBB = *MI.getParent();
200 DebugLoc DL = MI.getDebugLoc();
202 unsigned Dst = MI.getOperand(0).getReg();
203 unsigned Saved = MI.getOperand(1).getReg();
204 unsigned Src = MI.getOperand(2).getReg();
206 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
210 MI.eraseFromParent();
213 void SILowerControlFlowPass::Loop(MachineInstr &MI) {
215 MachineBasicBlock &MBB = *MI.getParent();
216 DebugLoc DL = MI.getDebugLoc();
217 unsigned Src = MI.getOperand(0).getReg();
219 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ANDN2_B64), AMDGPU::EXEC)
220 .addReg(AMDGPU::EXEC)
223 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
224 .addOperand(MI.getOperand(1))
225 .addReg(AMDGPU::EXEC);
227 MI.eraseFromParent();
230 void SILowerControlFlowPass::EndCf(MachineInstr &MI) {
232 MachineBasicBlock &MBB = *MI.getParent();
233 DebugLoc DL = MI.getDebugLoc();
234 unsigned Reg = MI.getOperand(0).getReg();
236 BuildMI(MBB, MBB.getFirstNonPHI(), DL,
237 TII->get(AMDGPU::S_OR_B64), AMDGPU::EXEC)
238 .addReg(AMDGPU::EXEC)
241 MI.eraseFromParent();
244 void SILowerControlFlowPass::Branch(MachineInstr &MI) {
246 MachineBasicBlock *Next = MI.getParent()->getNextNode();
247 MachineBasicBlock *Target = MI.getOperand(0).getMBB();
249 MI.eraseFromParent();
254 bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
258 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
261 MachineBasicBlock &MBB = *BI;
262 for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
263 I != MBB.end(); I = Next) {
265 Next = llvm::next(I);
266 MachineInstr &MI = *I;
267 switch (MI.getOpcode()) {
273 case AMDGPU::SI_ELSE:
277 case AMDGPU::SI_BREAK:
281 case AMDGPU::SI_IF_BREAK:
285 case AMDGPU::SI_ELSE_BREAK:
289 case AMDGPU::SI_LOOP:
293 case AMDGPU::SI_END_CF:
298 case AMDGPU::S_BRANCH:
305 // TODO: What is this good for?
306 unsigned ShaderType = MF.getInfo<SIMachineFunctionInfo>()->ShaderType;
307 if (HaveCf && ShaderType == ShaderType::PIXEL) {
308 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
311 MachineBasicBlock &MBB = *BI;
312 if (MBB.succ_empty()) {
314 MachineInstr &MI = *MBB.getFirstNonPHI();
315 DebugLoc DL = MI.getDebugLoc();
317 // If the exec mask is non-zero, skip the next two instructions
318 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
320 .addReg(AMDGPU::EXEC);
322 // Exec mask is zero: Export to NULL target...
323 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::EXP))
325 .addImm(0x09) // V_008DFC_SQ_EXP_NULL
329 .addReg(AMDGPU::SREG_LIT_0)
330 .addReg(AMDGPU::SREG_LIT_0)
331 .addReg(AMDGPU::SREG_LIT_0)
332 .addReg(AMDGPU::SREG_LIT_0);
334 // ... and terminate wavefront
335 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ENDPGM));