1 //===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This pass lowers the pseudo control flow instructions to real
12 /// machine instructions.
14 /// All control flow is handled using predicated instructions and
15 /// a predicate stack. Each Scalar ALU controls the operations of 64 Vector
16 /// ALUs. The Scalar ALU can update the predicate for any of the Vector ALUs
17 /// by writting to the 64-bit EXEC register (each bit corresponds to a
18 /// single vector ALU). Typically, for predicates, a vector ALU will write
19 /// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
20 /// Vector ALU) and then the ScalarALU will AND the VCC register with the
21 /// EXEC to update the predicates.
24 /// %VCC = V_CMP_GT_F32 %VGPR1, %VGPR2
25 /// %SGPR0 = SI_IF %VCC
26 /// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0
27 /// %SGPR0 = SI_ELSE %SGPR0
28 /// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR0
33 /// %SGPR0 = S_AND_SAVEEXEC_B64 %VCC // Save and update the exec mask
34 /// %SGPR0 = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
35 /// S_CBRANCH_EXECZ label0 // This instruction is an optional
36 /// // optimization which allows us to
37 /// // branch if all the bits of
39 /// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0 // Do the IF block of the branch
42 /// %SGPR0 = S_OR_SAVEEXEC_B64 %EXEC // Restore the exec mask for the Then block
43 /// %EXEC = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
44 /// S_BRANCH_EXECZ label1 // Use our branch optimization
45 /// // instruction again.
46 /// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR // Do the THEN block
48 /// %EXEC = S_OR_B64 %EXEC, %SGPR0 // Re-enable saved exec mask bits
49 //===----------------------------------------------------------------------===//
52 #include "SIInstrInfo.h"
53 #include "SIMachineFunctionInfo.h"
54 #include "llvm/CodeGen/MachineFunction.h"
55 #include "llvm/CodeGen/MachineFunctionPass.h"
56 #include "llvm/CodeGen/MachineInstrBuilder.h"
57 #include "llvm/CodeGen/MachineRegisterInfo.h"
58 #include "llvm/IR/Constants.h"
64 class SILowerControlFlowPass : public MachineFunctionPass {
67 static const unsigned SkipThreshold = 12;
70 const SIRegisterInfo *TRI;
71 const SIInstrInfo *TII;
73 bool shouldSkip(MachineBasicBlock *From, MachineBasicBlock *To);
75 void Skip(MachineInstr &From, MachineOperand &To);
76 void SkipIfDead(MachineInstr &MI);
78 void If(MachineInstr &MI);
79 void Else(MachineInstr &MI);
80 void Break(MachineInstr &MI);
81 void IfBreak(MachineInstr &MI);
82 void ElseBreak(MachineInstr &MI);
83 void Loop(MachineInstr &MI);
84 void EndCf(MachineInstr &MI);
86 void Kill(MachineInstr &MI);
87 void Branch(MachineInstr &MI);
89 void LoadM0(MachineInstr &MI, MachineInstr *MovRel);
90 void IndirectSrc(MachineInstr &MI);
91 void IndirectDst(MachineInstr &MI);
94 SILowerControlFlowPass(TargetMachine &tm) :
95 MachineFunctionPass(ID), TRI(nullptr), TII(nullptr) { }
97 bool runOnMachineFunction(MachineFunction &MF) override;
99 const char *getPassName() const override {
100 return "SI Lower control flow instructions";
105 } // End anonymous namespace
107 char SILowerControlFlowPass::ID = 0;
109 FunctionPass *llvm::createSILowerControlFlowPass(TargetMachine &tm) {
110 return new SILowerControlFlowPass(tm);
113 bool SILowerControlFlowPass::shouldSkip(MachineBasicBlock *From,
114 MachineBasicBlock *To) {
116 unsigned NumInstr = 0;
118 for (MachineBasicBlock *MBB = From; MBB != To && !MBB->succ_empty();
119 MBB = *MBB->succ_begin()) {
121 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
122 NumInstr < SkipThreshold && I != E; ++I) {
124 if (I->isBundle() || !I->isBundled())
125 if (++NumInstr >= SkipThreshold)
133 void SILowerControlFlowPass::Skip(MachineInstr &From, MachineOperand &To) {
135 if (!shouldSkip(*From.getParent()->succ_begin(), To.getMBB()))
138 DebugLoc DL = From.getDebugLoc();
139 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
141 .addReg(AMDGPU::EXEC);
144 void SILowerControlFlowPass::SkipIfDead(MachineInstr &MI) {
146 MachineBasicBlock &MBB = *MI.getParent();
147 DebugLoc DL = MI.getDebugLoc();
149 if (MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType !=
151 !shouldSkip(&MBB, &MBB.getParent()->back()))
154 MachineBasicBlock::iterator Insert = &MI;
157 // If the exec mask is non-zero, skip the next two instructions
158 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
160 .addReg(AMDGPU::EXEC);
162 // Exec mask is zero: Export to NULL target...
163 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP))
165 .addImm(0x09) // V_008DFC_SQ_EXP_NULL
169 .addReg(AMDGPU::VGPR0)
170 .addReg(AMDGPU::VGPR0)
171 .addReg(AMDGPU::VGPR0)
172 .addReg(AMDGPU::VGPR0);
174 // ... and terminate wavefront
175 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
178 void SILowerControlFlowPass::If(MachineInstr &MI) {
179 MachineBasicBlock &MBB = *MI.getParent();
180 DebugLoc DL = MI.getDebugLoc();
181 unsigned Reg = MI.getOperand(0).getReg();
182 unsigned Vcc = MI.getOperand(1).getReg();
184 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
187 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
188 .addReg(AMDGPU::EXEC)
191 Skip(MI, MI.getOperand(2));
193 MI.eraseFromParent();
196 void SILowerControlFlowPass::Else(MachineInstr &MI) {
197 MachineBasicBlock &MBB = *MI.getParent();
198 DebugLoc DL = MI.getDebugLoc();
199 unsigned Dst = MI.getOperand(0).getReg();
200 unsigned Src = MI.getOperand(1).getReg();
202 BuildMI(MBB, MBB.getFirstNonPHI(), DL,
203 TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
204 .addReg(Src); // Saved EXEC
206 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
207 .addReg(AMDGPU::EXEC)
210 Skip(MI, MI.getOperand(2));
212 MI.eraseFromParent();
215 void SILowerControlFlowPass::Break(MachineInstr &MI) {
216 MachineBasicBlock &MBB = *MI.getParent();
217 DebugLoc DL = MI.getDebugLoc();
219 unsigned Dst = MI.getOperand(0).getReg();
220 unsigned Src = MI.getOperand(1).getReg();
222 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
223 .addReg(AMDGPU::EXEC)
226 MI.eraseFromParent();
229 void SILowerControlFlowPass::IfBreak(MachineInstr &MI) {
230 MachineBasicBlock &MBB = *MI.getParent();
231 DebugLoc DL = MI.getDebugLoc();
233 unsigned Dst = MI.getOperand(0).getReg();
234 unsigned Vcc = MI.getOperand(1).getReg();
235 unsigned Src = MI.getOperand(2).getReg();
237 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
241 MI.eraseFromParent();
244 void SILowerControlFlowPass::ElseBreak(MachineInstr &MI) {
245 MachineBasicBlock &MBB = *MI.getParent();
246 DebugLoc DL = MI.getDebugLoc();
248 unsigned Dst = MI.getOperand(0).getReg();
249 unsigned Saved = MI.getOperand(1).getReg();
250 unsigned Src = MI.getOperand(2).getReg();
252 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
256 MI.eraseFromParent();
259 void SILowerControlFlowPass::Loop(MachineInstr &MI) {
260 MachineBasicBlock &MBB = *MI.getParent();
261 DebugLoc DL = MI.getDebugLoc();
262 unsigned Src = MI.getOperand(0).getReg();
264 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ANDN2_B64), AMDGPU::EXEC)
265 .addReg(AMDGPU::EXEC)
268 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
269 .addOperand(MI.getOperand(1))
270 .addReg(AMDGPU::EXEC);
272 MI.eraseFromParent();
275 void SILowerControlFlowPass::EndCf(MachineInstr &MI) {
276 MachineBasicBlock &MBB = *MI.getParent();
277 DebugLoc DL = MI.getDebugLoc();
278 unsigned Reg = MI.getOperand(0).getReg();
280 BuildMI(MBB, MBB.getFirstNonPHI(), DL,
281 TII->get(AMDGPU::S_OR_B64), AMDGPU::EXEC)
282 .addReg(AMDGPU::EXEC)
285 MI.eraseFromParent();
288 void SILowerControlFlowPass::Branch(MachineInstr &MI) {
289 if (MI.getOperand(0).getMBB() == MI.getParent()->getNextNode())
290 MI.eraseFromParent();
292 // If these aren't equal, this is probably an infinite loop.
295 void SILowerControlFlowPass::Kill(MachineInstr &MI) {
296 MachineBasicBlock &MBB = *MI.getParent();
297 DebugLoc DL = MI.getDebugLoc();
298 const MachineOperand &Op = MI.getOperand(0);
300 // Kill is only allowed in pixel / geometry shaders
301 assert(MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType ==
303 MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType ==
304 ShaderType::GEOMETRY);
306 // Clear this thread from the exec mask if the operand is negative
307 if ((Op.isImm() || Op.isFPImm())) {
308 // Constant operand: Set exec mask to 0 or do nothing
309 if (Op.isImm() ? (Op.getImm() & 0x80000000) :
310 Op.getFPImm()->isNegative()) {
311 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
315 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC)
320 MI.eraseFromParent();
323 void SILowerControlFlowPass::LoadM0(MachineInstr &MI, MachineInstr *MovRel) {
325 MachineBasicBlock &MBB = *MI.getParent();
326 DebugLoc DL = MI.getDebugLoc();
327 MachineBasicBlock::iterator I = MI;
329 unsigned Save = MI.getOperand(1).getReg();
330 unsigned Idx = MI.getOperand(3).getReg();
332 if (AMDGPU::SReg_32RegClass.contains(Idx)) {
333 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
335 MBB.insert(I, MovRel);
336 MI.eraseFromParent();
340 assert(AMDGPU::SReg_64RegClass.contains(Save));
341 assert(AMDGPU::VReg_32RegClass.contains(Idx));
343 // Save the EXEC mask
344 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), Save)
345 .addReg(AMDGPU::EXEC);
347 // Read the next variant into VCC (lower 32 bits) <- also loop target
348 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
352 // Move index from VCC into M0
353 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
354 .addReg(AMDGPU::VCC_LO);
356 // Compare the just read M0 value to all possible Idx values
357 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e32), AMDGPU::VCC)
361 // Update EXEC, save the original EXEC value to VCC
362 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), AMDGPU::VCC)
363 .addReg(AMDGPU::VCC);
365 // Do the actual move
366 MBB.insert(I, MovRel);
368 // Update EXEC, switch all done bits to 0 and all todo bits to 1
369 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
370 .addReg(AMDGPU::EXEC)
371 .addReg(AMDGPU::VCC);
373 // Loop back to V_READFIRSTLANE_B32 if there are still variants to cover
374 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
376 .addReg(AMDGPU::EXEC);
379 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
382 MI.eraseFromParent();
385 void SILowerControlFlowPass::IndirectSrc(MachineInstr &MI) {
387 MachineBasicBlock &MBB = *MI.getParent();
388 DebugLoc DL = MI.getDebugLoc();
390 unsigned Dst = MI.getOperand(0).getReg();
391 unsigned Vec = MI.getOperand(2).getReg();
392 unsigned Off = MI.getOperand(4).getImm();
393 unsigned SubReg = TRI->getSubReg(Vec, AMDGPU::sub0);
397 MachineInstr *MovRel =
398 BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
399 .addReg(SubReg + Off)
400 .addReg(AMDGPU::M0, RegState::Implicit)
401 .addReg(Vec, RegState::Implicit);
406 void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) {
408 MachineBasicBlock &MBB = *MI.getParent();
409 DebugLoc DL = MI.getDebugLoc();
411 unsigned Dst = MI.getOperand(0).getReg();
412 unsigned Off = MI.getOperand(4).getImm();
413 unsigned Val = MI.getOperand(5).getReg();
414 unsigned SubReg = TRI->getSubReg(Dst, AMDGPU::sub0);
418 MachineInstr *MovRel =
419 BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELD_B32_e32))
420 .addReg(SubReg + Off, RegState::Define)
422 .addReg(AMDGPU::M0, RegState::Implicit)
423 .addReg(Dst, RegState::Implicit);
428 bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
429 TII = static_cast<const SIInstrInfo*>(MF.getTarget().getInstrInfo());
430 TRI = static_cast<const SIRegisterInfo*>(MF.getTarget().getRegisterInfo());
431 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
433 bool HaveKill = false;
435 bool NeedWQM = false;
438 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
441 MachineBasicBlock &MBB = *BI;
442 MachineBasicBlock::iterator I, Next;
443 for (I = MBB.begin(); I != MBB.end(); I = Next) {
446 MachineInstr &MI = *I;
447 if (TII->isDS(MI.getOpcode())) {
452 switch (MI.getOpcode()) {
459 case AMDGPU::SI_ELSE:
463 case AMDGPU::SI_BREAK:
467 case AMDGPU::SI_IF_BREAK:
471 case AMDGPU::SI_ELSE_BREAK:
475 case AMDGPU::SI_LOOP:
480 case AMDGPU::SI_END_CF:
481 if (--Depth == 0 && HaveKill) {
488 case AMDGPU::SI_KILL:
496 case AMDGPU::S_BRANCH:
500 case AMDGPU::SI_INDIRECT_SRC:
504 case AMDGPU::SI_INDIRECT_DST_V1:
505 case AMDGPU::SI_INDIRECT_DST_V2:
506 case AMDGPU::SI_INDIRECT_DST_V4:
507 case AMDGPU::SI_INDIRECT_DST_V8:
508 case AMDGPU::SI_INDIRECT_DST_V16:
512 case AMDGPU::V_INTERP_P1_F32:
513 case AMDGPU::V_INTERP_P2_F32:
514 case AMDGPU::V_INTERP_MOV_F32:
523 MachineBasicBlock &MBB = MF.front();
524 // Initialize M0 to a value that won't cause LDS access to be discarded
525 // due to offset clamping
526 BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_MOV_B32),
527 AMDGPU::M0).addImm(0xffffffff);
530 if (NeedWQM && MFI->ShaderType == ShaderType::PIXEL) {
531 MachineBasicBlock &MBB = MF.front();
532 BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_WQM_B64),
533 AMDGPU::EXEC).addReg(AMDGPU::EXEC);