1 //===-- SILowerI1Copies.cpp - Lower I1 Copies -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 /// i1 values are usually inserted by the CFG Structurize pass and they are
9 /// unique in that they can be copied from VALU to SALU registers.
10 /// This is not possible for any other value type. Since there are no
11 /// MOV instructions for i1, we to use V_CMP_* and V_CNDMASK to move the i1.
13 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "si-i1-copies"
18 #include "SIInstrInfo.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/MachineDominators.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/IR/LLVMContext.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Target/TargetMachine.h"
33 class SILowerI1Copies : public MachineFunctionPass {
38 SILowerI1Copies() : MachineFunctionPass(ID) {
39 initializeSILowerI1CopiesPass(*PassRegistry::getPassRegistry());
42 virtual bool runOnMachineFunction(MachineFunction &MF) override;
44 virtual const char *getPassName() const override {
45 return "SI Lower il Copies";
48 virtual void getAnalysisUsage(AnalysisUsage &AU) const override {
49 AU.addRequired<MachineDominatorTree>();
51 MachineFunctionPass::getAnalysisUsage(AU);
55 } // End anonymous namespace.
57 INITIALIZE_PASS_BEGIN(SILowerI1Copies, DEBUG_TYPE,
58 "SI Lower il Copies", false, false)
59 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
60 INITIALIZE_PASS_END(SILowerI1Copies, DEBUG_TYPE,
61 "SI Lower il Copies", false, false)
63 char SILowerI1Copies::ID = 0;
65 char &llvm::SILowerI1CopiesID = SILowerI1Copies::ID;
67 FunctionPass *llvm::createSILowerI1CopiesPass() {
68 return new SILowerI1Copies();
71 bool SILowerI1Copies::runOnMachineFunction(MachineFunction &MF) {
72 MachineRegisterInfo &MRI = MF.getRegInfo();
73 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
74 MF.getTarget().getInstrInfo());
75 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
76 std::vector<unsigned> I1Defs;
78 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
81 MachineBasicBlock &MBB = *BI;
82 MachineBasicBlock::iterator I, Next;
83 for (I = MBB.begin(); I != MBB.end(); I = Next) {
85 MachineInstr &MI = *I;
87 if (MI.getOpcode() == AMDGPU::V_MOV_I1) {
88 I1Defs.push_back(MI.getOperand(0).getReg());
89 MI.setDesc(TII->get(AMDGPU::V_MOV_B32_e32));
93 if (MI.getOpcode() == AMDGPU::V_AND_I1) {
94 I1Defs.push_back(MI.getOperand(0).getReg());
95 MI.setDesc(TII->get(AMDGPU::V_AND_B32_e32));
99 if (MI.getOpcode() == AMDGPU::V_OR_I1) {
100 I1Defs.push_back(MI.getOperand(0).getReg());
101 MI.setDesc(TII->get(AMDGPU::V_OR_B32_e32));
105 if (MI.getOpcode() == AMDGPU::V_XOR_I1) {
106 I1Defs.push_back(MI.getOperand(0).getReg());
107 MI.setDesc(TII->get(AMDGPU::V_XOR_B32_e32));
111 if (MI.getOpcode() != AMDGPU::COPY ||
112 !TargetRegisterInfo::isVirtualRegister(MI.getOperand(0).getReg()) ||
113 !TargetRegisterInfo::isVirtualRegister(MI.getOperand(1).getReg()))
117 const TargetRegisterClass *DstRC =
118 MRI.getRegClass(MI.getOperand(0).getReg());
119 const TargetRegisterClass *SrcRC =
120 MRI.getRegClass(MI.getOperand(1).getReg());
122 if (DstRC == &AMDGPU::VReg_1RegClass &&
123 TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) {
124 I1Defs.push_back(MI.getOperand(0).getReg());
125 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(AMDGPU::V_CNDMASK_B32_e64))
126 .addOperand(MI.getOperand(0))
129 .addOperand(MI.getOperand(1))
134 MI.eraseFromParent();
135 } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) &&
136 SrcRC == &AMDGPU::VReg_1RegClass) {
137 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(AMDGPU::V_CMP_NE_I32_e64))
138 .addOperand(MI.getOperand(0))
139 .addOperand(MI.getOperand(1))
141 MI.eraseFromParent();
146 for (unsigned Reg : I1Defs)
147 MRI.setRegClass(Reg, &AMDGPU::VReg_32RegClass);