1 //===- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface -*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_R600_SIMACHINEFUNCTIONINFO_H
16 #define LLVM_LIB_TARGET_R600_SIMACHINEFUNCTIONINFO_H
18 #include "AMDGPUMachineFunction.h"
23 class MachineRegisterInfo;
25 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
26 /// tells the hardware which interpolation parameters to load.
27 class SIMachineFunctionInfo : public AMDGPUMachineFunction {
28 void anchor() override;
34 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { }
35 SpilledReg() : VGPR(0), Lane(-1) { }
36 bool hasLane() { return Lane != -1;}
39 struct RegSpillTracker {
42 std::map<unsigned, SpilledReg> SpilledRegisters;
45 RegSpillTracker() : CurrentLane(0), SpilledRegisters(), LaneVGPR(0) { }
46 /// \p NumRegs The number of consecutive registers what need to be spilled.
47 /// This function will ensure that all registers are stored in
49 /// \returns The lane to be used for storing the first register.
50 unsigned reserveLanes(MachineRegisterInfo &MRI, MachineFunction *MF,
51 unsigned NumRegs = 1);
52 void addSpilledReg(unsigned FrameIndex, unsigned Reg, int Lane = -1);
53 const SpilledReg& getSpilledReg(unsigned FrameIndex);
54 bool programSpillsRegisters() { return !SpilledRegisters.empty(); }
57 // SIMachineFunctionInfo definition
59 SIMachineFunctionInfo(const MachineFunction &MF);
61 struct RegSpillTracker SpillTracker;
62 unsigned NumUserSGPRs;
65 } // End namespace llvm