1 //===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI implementation of the TargetRegisterInfo class.
13 //===----------------------------------------------------------------------===//
16 #include "SIRegisterInfo.h"
17 #include "AMDGPUSubtarget.h"
18 #include "SIInstrInfo.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/RegisterScavenging.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/IR/LLVMContext.h"
28 SIRegisterInfo::SIRegisterInfo(const AMDGPUSubtarget &st)
29 : AMDGPURegisterInfo(st)
32 BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
33 BitVector Reserved(getNumRegs());
34 Reserved.set(AMDGPU::EXEC);
36 // EXEC_LO and EXEC_HI could be allocated and used as regular register,
37 // but this seems likely to result in bugs, so I'm marking them as reserved.
38 Reserved.set(AMDGPU::EXEC_LO);
39 Reserved.set(AMDGPU::EXEC_HI);
41 Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
42 Reserved.set(AMDGPU::FLAT_SCR);
43 Reserved.set(AMDGPU::FLAT_SCR_LO);
44 Reserved.set(AMDGPU::FLAT_SCR_HI);
46 // Reserve some VGPRs to use as temp registers in case we have to spill VGPRs
47 Reserved.set(AMDGPU::VGPR255);
48 Reserved.set(AMDGPU::VGPR254);
53 unsigned SIRegisterInfo::getRegPressureSetLimit(unsigned Idx) const {
55 // FIXME: We should adjust the max number of waves based on LDS size.
56 unsigned SGPRLimit = getNumSGPRsAllowed(ST.getMaxWavesPerCU());
57 unsigned VGPRLimit = getNumVGPRsAllowed(ST.getMaxWavesPerCU());
59 for (regclass_iterator I = regclass_begin(), E = regclass_end();
62 unsigned NumSubRegs = std::max((int)(*I)->getSize() / 4, 1);
65 if (isSGPRClass(*I)) {
66 Limit = SGPRLimit / NumSubRegs;
68 Limit = VGPRLimit / NumSubRegs;
71 const int *Sets = getRegClassPressureSets(*I);
73 for (unsigned i = 0; Sets[i] != -1; ++i) {
74 if (Sets[i] == (int)Idx)
81 bool SIRegisterInfo::requiresRegisterScavenging(const MachineFunction &Fn) const {
82 return Fn.getFrameInfo()->hasStackObjects();
85 static unsigned getNumSubRegsForSpillOp(unsigned Op) {
88 case AMDGPU::SI_SPILL_S512_SAVE:
89 case AMDGPU::SI_SPILL_S512_RESTORE:
90 case AMDGPU::SI_SPILL_V512_SAVE:
91 case AMDGPU::SI_SPILL_V512_RESTORE:
93 case AMDGPU::SI_SPILL_S256_SAVE:
94 case AMDGPU::SI_SPILL_S256_RESTORE:
95 case AMDGPU::SI_SPILL_V256_SAVE:
96 case AMDGPU::SI_SPILL_V256_RESTORE:
98 case AMDGPU::SI_SPILL_S128_SAVE:
99 case AMDGPU::SI_SPILL_S128_RESTORE:
100 case AMDGPU::SI_SPILL_V128_SAVE:
101 case AMDGPU::SI_SPILL_V128_RESTORE:
103 case AMDGPU::SI_SPILL_V96_SAVE:
104 case AMDGPU::SI_SPILL_V96_RESTORE:
106 case AMDGPU::SI_SPILL_S64_SAVE:
107 case AMDGPU::SI_SPILL_S64_RESTORE:
108 case AMDGPU::SI_SPILL_V64_SAVE:
109 case AMDGPU::SI_SPILL_V64_RESTORE:
111 case AMDGPU::SI_SPILL_S32_SAVE:
112 case AMDGPU::SI_SPILL_S32_RESTORE:
113 case AMDGPU::SI_SPILL_V32_SAVE:
114 case AMDGPU::SI_SPILL_V32_RESTORE:
116 default: llvm_unreachable("Invalid spill opcode");
120 void SIRegisterInfo::buildScratchLoadStore(MachineBasicBlock::iterator MI,
121 unsigned LoadStoreOp,
123 unsigned ScratchRsrcReg,
124 unsigned ScratchOffset,
126 RegScavenger *RS) const {
128 const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
129 MachineBasicBlock *MBB = MI->getParent();
130 const MachineFunction *MF = MI->getParent()->getParent();
131 LLVMContext &Ctx = MF->getFunction()->getContext();
132 DebugLoc DL = MI->getDebugLoc();
133 bool IsLoad = TII->get(LoadStoreOp).mayLoad();
135 bool RanOutOfSGPRs = false;
136 unsigned SOffset = ScratchOffset;
138 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
139 unsigned Size = NumSubRegs * 4;
141 if (!isUInt<12>(Offset + Size)) {
142 SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0);
143 if (SOffset == AMDGPU::NoRegister) {
144 RanOutOfSGPRs = true;
145 SOffset = AMDGPU::SGPR0;
147 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), SOffset)
148 .addReg(ScratchOffset)
154 Ctx.emitError("Ran out of SGPRs for spilling VGPRS");
156 for (unsigned i = 0, e = NumSubRegs; i != e; ++i, Offset += 4) {
157 unsigned SubReg = NumSubRegs > 1 ?
158 getPhysRegSubReg(Value, &AMDGPU::VGPR_32RegClass, i) :
160 bool IsKill = (i == e - 1);
162 BuildMI(*MBB, MI, DL, TII->get(LoadStoreOp))
163 .addReg(SubReg, getDefRegState(IsLoad))
164 .addReg(ScratchRsrcReg, getKillRegState(IsKill))
170 .addReg(Value, RegState::Implicit | getDefRegState(IsLoad));
174 void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
175 int SPAdj, unsigned FIOperandNum,
176 RegScavenger *RS) const {
177 MachineFunction *MF = MI->getParent()->getParent();
178 MachineBasicBlock *MBB = MI->getParent();
179 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
180 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
181 const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
182 DebugLoc DL = MI->getDebugLoc();
184 MachineOperand &FIOp = MI->getOperand(FIOperandNum);
185 int Index = MI->getOperand(FIOperandNum).getIndex();
187 switch (MI->getOpcode()) {
188 // SGPR register spill
189 case AMDGPU::SI_SPILL_S512_SAVE:
190 case AMDGPU::SI_SPILL_S256_SAVE:
191 case AMDGPU::SI_SPILL_S128_SAVE:
192 case AMDGPU::SI_SPILL_S64_SAVE:
193 case AMDGPU::SI_SPILL_S32_SAVE: {
194 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
196 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
197 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
198 &AMDGPU::SGPR_32RegClass, i);
199 struct SIMachineFunctionInfo::SpilledReg Spill =
200 MFI->getSpilledReg(MF, Index, i);
202 if (Spill.VGPR == AMDGPU::NoRegister) {
203 LLVMContext &Ctx = MF->getFunction()->getContext();
204 Ctx.emitError("Ran out of VGPRs for spilling SGPR");
207 BuildMI(*MBB, MI, DL,
208 TII->getMCOpcodeFromPseudo(AMDGPU::V_WRITELANE_B32),
214 MI->eraseFromParent();
218 // SGPR register restore
219 case AMDGPU::SI_SPILL_S512_RESTORE:
220 case AMDGPU::SI_SPILL_S256_RESTORE:
221 case AMDGPU::SI_SPILL_S128_RESTORE:
222 case AMDGPU::SI_SPILL_S64_RESTORE:
223 case AMDGPU::SI_SPILL_S32_RESTORE: {
224 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
226 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
227 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
228 &AMDGPU::SGPR_32RegClass, i);
229 bool isM0 = SubReg == AMDGPU::M0;
230 struct SIMachineFunctionInfo::SpilledReg Spill =
231 MFI->getSpilledReg(MF, Index, i);
233 if (Spill.VGPR == AMDGPU::NoRegister) {
234 LLVMContext &Ctx = MF->getFunction()->getContext();
235 Ctx.emitError("Ran out of VGPRs for spilling SGPR");
239 SubReg = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0);
241 BuildMI(*MBB, MI, DL,
242 TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32),
246 .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
248 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
252 TII->insertNOPs(MI, 3);
253 MI->eraseFromParent();
257 // VGPR register spill
258 case AMDGPU::SI_SPILL_V512_SAVE:
259 case AMDGPU::SI_SPILL_V256_SAVE:
260 case AMDGPU::SI_SPILL_V128_SAVE:
261 case AMDGPU::SI_SPILL_V96_SAVE:
262 case AMDGPU::SI_SPILL_V64_SAVE:
263 case AMDGPU::SI_SPILL_V32_SAVE:
264 buildScratchLoadStore(MI, AMDGPU::BUFFER_STORE_DWORD_OFFSET,
265 TII->getNamedOperand(*MI, AMDGPU::OpName::src)->getReg(),
266 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(),
267 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(),
268 FrameInfo->getObjectOffset(Index), RS);
269 MI->eraseFromParent();
271 case AMDGPU::SI_SPILL_V32_RESTORE:
272 case AMDGPU::SI_SPILL_V64_RESTORE:
273 case AMDGPU::SI_SPILL_V96_RESTORE:
274 case AMDGPU::SI_SPILL_V128_RESTORE:
275 case AMDGPU::SI_SPILL_V256_RESTORE:
276 case AMDGPU::SI_SPILL_V512_RESTORE: {
277 buildScratchLoadStore(MI, AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
278 TII->getNamedOperand(*MI, AMDGPU::OpName::dst)->getReg(),
279 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(),
280 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(),
281 FrameInfo->getObjectOffset(Index), RS);
282 MI->eraseFromParent();
287 int64_t Offset = FrameInfo->getObjectOffset(Index);
288 FIOp.ChangeToImmediate(Offset);
289 if (!TII->isImmOperandLegal(MI, FIOperandNum, FIOp)) {
290 unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, SPAdj);
291 BuildMI(*MBB, MI, MI->getDebugLoc(),
292 TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
294 FIOp.ChangeToRegister(TmpReg, false, false, true);
300 const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
302 switch(VT.SimpleTy) {
304 case MVT::i32: return &AMDGPU::VGPR_32RegClass;
308 unsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const {
309 return getEncodingValue(Reg) & 0xff;
312 const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
313 assert(!TargetRegisterInfo::isVirtualRegister(Reg));
315 static const TargetRegisterClass *BaseClasses[] = {
316 &AMDGPU::VGPR_32RegClass,
317 &AMDGPU::SReg_32RegClass,
318 &AMDGPU::VReg_64RegClass,
319 &AMDGPU::SReg_64RegClass,
320 &AMDGPU::VReg_96RegClass,
321 &AMDGPU::VReg_128RegClass,
322 &AMDGPU::SReg_128RegClass,
323 &AMDGPU::VReg_256RegClass,
324 &AMDGPU::SReg_256RegClass,
325 &AMDGPU::VReg_512RegClass
328 for (const TargetRegisterClass *BaseClass : BaseClasses) {
329 if (BaseClass->contains(Reg)) {
336 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
337 return getCommonSubClass(&AMDGPU::VGPR_32RegClass, RC) ||
338 getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) ||
339 getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) ||
340 getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) ||
341 getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) ||
342 getCommonSubClass(&AMDGPU::VReg_512RegClass, RC);
345 const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
346 const TargetRegisterClass *SRC) const {
349 } else if (SRC == &AMDGPU::SCCRegRegClass) {
350 return &AMDGPU::VCCRegRegClass;
351 } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) {
352 return &AMDGPU::VGPR_32RegClass;
353 } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) {
354 return &AMDGPU::VReg_64RegClass;
355 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_128RegClass)) {
356 return &AMDGPU::VReg_128RegClass;
357 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_256RegClass)) {
358 return &AMDGPU::VReg_256RegClass;
359 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_512RegClass)) {
360 return &AMDGPU::VReg_512RegClass;
365 const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
366 const TargetRegisterClass *RC, unsigned SubIdx) const {
367 if (SubIdx == AMDGPU::NoSubRegister)
370 // If this register has a sub-register, we can safely assume it is a 32-bit
371 // register, because all of SI's sub-registers are 32-bit.
372 if (isSGPRClass(RC)) {
373 return &AMDGPU::SGPR_32RegClass;
375 return &AMDGPU::VGPR_32RegClass;
379 unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
380 const TargetRegisterClass *SubRC,
381 unsigned Channel) const {
386 case 0: return AMDGPU::VCC_LO;
387 case 1: return AMDGPU::VCC_HI;
388 default: llvm_unreachable("Invalid SubIdx for VCC");
391 case AMDGPU::FLAT_SCR:
394 return AMDGPU::FLAT_SCR_LO;
396 return AMDGPU::FLAT_SCR_HI;
398 llvm_unreachable("Invalid SubIdx for FLAT_SCR");
405 return AMDGPU::EXEC_LO;
407 return AMDGPU::EXEC_HI;
409 llvm_unreachable("Invalid SubIdx for EXEC");
414 const TargetRegisterClass *RC = getPhysRegClass(Reg);
415 // 32-bit registers don't have sub-registers, so we can just return the
416 // Reg. We need to have this check here, because the calculation below
417 // using getHWRegIndex() will fail with special 32-bit registers like
418 // VCC_LO, VCC_HI, EXEC_LO, EXEC_HI and M0.
419 if (RC->getSize() == 4) {
420 assert(Channel == 0);
424 unsigned Index = getHWRegIndex(Reg);
425 return SubRC->getRegister(Index + Channel);
428 bool SIRegisterInfo::opCanUseLiteralConstant(unsigned OpType) const {
429 return OpType == AMDGPU::OPERAND_REG_IMM32;
432 bool SIRegisterInfo::opCanUseInlineConstant(unsigned OpType) const {
433 if (opCanUseLiteralConstant(OpType))
436 return OpType == AMDGPU::OPERAND_REG_INLINE_C;
439 unsigned SIRegisterInfo::getPreloadedValue(const MachineFunction &MF,
440 enum PreloadedValue Value) const {
442 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
444 case SIRegisterInfo::TGID_X:
445 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 0);
446 case SIRegisterInfo::TGID_Y:
447 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 1);
448 case SIRegisterInfo::TGID_Z:
449 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 2);
450 case SIRegisterInfo::SCRATCH_WAVE_OFFSET:
451 if (MFI->getShaderType() != ShaderType::COMPUTE)
452 return MFI->ScratchOffsetReg;
453 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 4);
454 case SIRegisterInfo::SCRATCH_PTR:
455 return AMDGPU::SGPR2_SGPR3;
456 case SIRegisterInfo::INPUT_PTR:
457 return AMDGPU::SGPR0_SGPR1;
458 case SIRegisterInfo::TIDIG_X:
459 return AMDGPU::VGPR0;
460 case SIRegisterInfo::TIDIG_Y:
461 return AMDGPU::VGPR1;
462 case SIRegisterInfo::TIDIG_Z:
463 return AMDGPU::VGPR2;
465 llvm_unreachable("unexpected preloaded value type");
468 /// \brief Returns a register that is not used at any point in the function.
469 /// If all registers are used, then this function will return
470 // AMDGPU::NoRegister.
471 unsigned SIRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,
472 const TargetRegisterClass *RC) const {
474 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
476 if (!MRI.isPhysRegUsed(*I))
479 return AMDGPU::NoRegister;
482 unsigned SIRegisterInfo::getNumVGPRsAllowed(unsigned WaveCount) const {
497 unsigned SIRegisterInfo::getNumSGPRsAllowed(unsigned WaveCount) const {