1 //===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI implementation of the TargetRegisterInfo class.
13 //===----------------------------------------------------------------------===//
16 #include "SIRegisterInfo.h"
17 #include "AMDGPUSubtarget.h"
18 #include "SIInstrInfo.h"
22 SIRegisterInfo::SIRegisterInfo(const AMDGPUSubtarget &st)
23 : AMDGPURegisterInfo(st)
26 BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
27 BitVector Reserved(getNumRegs());
28 Reserved.set(AMDGPU::EXEC);
29 Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
30 const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
31 TII->reserveIndirectRegisters(Reserved, MF);
35 unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
36 MachineFunction &MF) const {
37 return RC->getNumRegs();
40 const TargetRegisterClass *
41 SIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const {
42 switch (rc->getID()) {
43 case AMDGPU::GPRF32RegClassID:
44 return &AMDGPU::VReg_32RegClass;
49 const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
53 case MVT::i32: return &AMDGPU::VReg_32RegClass;
57 unsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const {
58 return getEncodingValue(Reg) & 0xff;
61 const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
62 assert(!TargetRegisterInfo::isVirtualRegister(Reg));
64 const TargetRegisterClass *BaseClasses[] = {
65 &AMDGPU::VReg_32RegClass,
66 &AMDGPU::SReg_32RegClass,
67 &AMDGPU::VReg_64RegClass,
68 &AMDGPU::SReg_64RegClass,
69 &AMDGPU::SReg_128RegClass,
70 &AMDGPU::SReg_256RegClass
73 for (const TargetRegisterClass *BaseClass : BaseClasses) {
74 if (BaseClass->contains(Reg)) {
81 bool SIRegisterInfo::isSGPRClass(const TargetRegisterClass *RC) const {
88 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
89 return getCommonSubClass(&AMDGPU::VReg_32RegClass, RC) ||
90 getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) ||
91 getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) ||
92 getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) ||
93 getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) ||
94 getCommonSubClass(&AMDGPU::VReg_512RegClass, RC);
97 const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
98 const TargetRegisterClass *SRC) const {
101 } else if (SRC == &AMDGPU::SCCRegRegClass) {
102 return &AMDGPU::VCCRegRegClass;
103 } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) {
104 return &AMDGPU::VReg_32RegClass;
105 } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) {
106 return &AMDGPU::VReg_64RegClass;
107 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_128RegClass)) {
108 return &AMDGPU::VReg_128RegClass;
109 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_256RegClass)) {
110 return &AMDGPU::VReg_256RegClass;
111 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_512RegClass)) {
112 return &AMDGPU::VReg_512RegClass;
117 const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
118 const TargetRegisterClass *RC, unsigned SubIdx) const {
119 if (SubIdx == AMDGPU::NoSubRegister)
122 // If this register has a sub-register, we can safely assume it is a 32-bit
123 // register, because all of SI's sub-registers are 32-bit.
124 if (isSGPRClass(RC)) {
125 return &AMDGPU::SGPR_32RegClass;
127 return &AMDGPU::VGPR_32RegClass;
131 unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
132 const TargetRegisterClass *SubRC,
133 unsigned Channel) const {
134 unsigned Index = getHWRegIndex(Reg);
135 return SubRC->getRegister(Index + Channel);