1 //===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI implementation of the TargetRegisterInfo class.
13 //===----------------------------------------------------------------------===//
16 #include "SIRegisterInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIInstrInfo.h"
22 SIRegisterInfo::SIRegisterInfo(AMDGPUTargetMachine &tm)
23 : AMDGPURegisterInfo(tm),
27 BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
28 BitVector Reserved(getNumRegs());
29 Reserved.set(AMDGPU::EXEC);
30 Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
31 const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(TM.getInstrInfo());
32 TII->reserveIndirectRegisters(Reserved, MF);
36 unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
37 MachineFunction &MF) const {
38 return RC->getNumRegs();
41 const TargetRegisterClass *
42 SIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const {
43 switch (rc->getID()) {
44 case AMDGPU::GPRF32RegClassID:
45 return &AMDGPU::VReg_32RegClass;
50 const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
54 case MVT::i32: return &AMDGPU::VReg_32RegClass;
58 unsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const {
59 return getEncodingValue(Reg) & 0xff;
62 const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
63 assert(!TargetRegisterInfo::isVirtualRegister(Reg));
65 const TargetRegisterClass *BaseClasses[] = {
66 &AMDGPU::VReg_32RegClass,
67 &AMDGPU::SReg_32RegClass,
68 &AMDGPU::VReg_64RegClass,
69 &AMDGPU::SReg_64RegClass,
70 &AMDGPU::SReg_128RegClass,
71 &AMDGPU::SReg_256RegClass
74 for (const TargetRegisterClass *BaseClass : BaseClasses) {
75 if (BaseClass->contains(Reg)) {
82 bool SIRegisterInfo::isSGPRClass(const TargetRegisterClass *RC) const {
89 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
90 return getCommonSubClass(&AMDGPU::VReg_32RegClass, RC) ||
91 getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) ||
92 getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) ||
93 getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) ||
94 getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) ||
95 getCommonSubClass(&AMDGPU::VReg_512RegClass, RC);
98 const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
99 const TargetRegisterClass *SRC) const {
102 } else if (SRC == &AMDGPU::SCCRegRegClass) {
103 return &AMDGPU::VCCRegRegClass;
104 } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) {
105 return &AMDGPU::VReg_32RegClass;
106 } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) {
107 return &AMDGPU::VReg_64RegClass;
108 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_128RegClass)) {
109 return &AMDGPU::VReg_128RegClass;
110 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_256RegClass)) {
111 return &AMDGPU::VReg_256RegClass;
112 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_512RegClass)) {
113 return &AMDGPU::VReg_512RegClass;
118 const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
119 const TargetRegisterClass *RC, unsigned SubIdx) const {
120 if (SubIdx == AMDGPU::NoSubRegister)
123 // If this register has a sub-register, we can safely assume it is a 32-bit
124 // register, because all of SI's sub-registers are 32-bit.
125 if (isSGPRClass(RC)) {
126 return &AMDGPU::SGPR_32RegClass;
128 return &AMDGPU::VGPR_32RegClass;
132 unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
133 const TargetRegisterClass *SubRC,
134 unsigned Channel) const {
135 unsigned Index = getHWRegIndex(Reg);
136 return SubRC->getRegister(Index + Channel);