1 //===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI implementation of the TargetRegisterInfo class.
13 //===----------------------------------------------------------------------===//
16 #include "SIRegisterInfo.h"
17 #include "AMDGPUSubtarget.h"
18 #include "SIInstrInfo.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/RegisterScavenging.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/IR/LLVMContext.h"
28 SIRegisterInfo::SIRegisterInfo(const AMDGPUSubtarget &st)
29 : AMDGPURegisterInfo(st)
32 BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
33 BitVector Reserved(getNumRegs());
34 Reserved.set(AMDGPU::EXEC);
36 // EXEC_LO and EXEC_HI could be allocated and used as regular register,
37 // but this seems likely to result in bugs, so I'm marking them as reserved.
38 Reserved.set(AMDGPU::EXEC_LO);
39 Reserved.set(AMDGPU::EXEC_HI);
41 Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
42 Reserved.set(AMDGPU::FLAT_SCR);
43 Reserved.set(AMDGPU::FLAT_SCR_LO);
44 Reserved.set(AMDGPU::FLAT_SCR_HI);
46 // Reserve some VGPRs to use as temp registers in case we have to spill VGPRs
47 Reserved.set(AMDGPU::VGPR255);
48 Reserved.set(AMDGPU::VGPR254);
53 unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
54 MachineFunction &MF) const {
55 return RC->getNumRegs();
58 bool SIRegisterInfo::requiresRegisterScavenging(const MachineFunction &Fn) const {
59 return Fn.getFrameInfo()->hasStackObjects();
62 static unsigned getNumSubRegsForSpillOp(unsigned Op) {
65 case AMDGPU::SI_SPILL_S512_SAVE:
66 case AMDGPU::SI_SPILL_S512_RESTORE:
67 case AMDGPU::SI_SPILL_V512_SAVE:
68 case AMDGPU::SI_SPILL_V512_RESTORE:
70 case AMDGPU::SI_SPILL_S256_SAVE:
71 case AMDGPU::SI_SPILL_S256_RESTORE:
72 case AMDGPU::SI_SPILL_V256_SAVE:
73 case AMDGPU::SI_SPILL_V256_RESTORE:
75 case AMDGPU::SI_SPILL_S128_SAVE:
76 case AMDGPU::SI_SPILL_S128_RESTORE:
77 case AMDGPU::SI_SPILL_V128_SAVE:
78 case AMDGPU::SI_SPILL_V128_RESTORE:
80 case AMDGPU::SI_SPILL_V96_SAVE:
81 case AMDGPU::SI_SPILL_V96_RESTORE:
83 case AMDGPU::SI_SPILL_S64_SAVE:
84 case AMDGPU::SI_SPILL_S64_RESTORE:
85 case AMDGPU::SI_SPILL_V64_SAVE:
86 case AMDGPU::SI_SPILL_V64_RESTORE:
88 case AMDGPU::SI_SPILL_S32_SAVE:
89 case AMDGPU::SI_SPILL_S32_RESTORE:
90 case AMDGPU::SI_SPILL_V32_SAVE:
91 case AMDGPU::SI_SPILL_V32_RESTORE:
93 default: llvm_unreachable("Invalid spill opcode");
97 void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
98 int SPAdj, unsigned FIOperandNum,
99 RegScavenger *RS) const {
100 MachineFunction *MF = MI->getParent()->getParent();
101 MachineBasicBlock *MBB = MI->getParent();
102 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
103 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
104 const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
105 DebugLoc DL = MI->getDebugLoc();
107 MachineOperand &FIOp = MI->getOperand(FIOperandNum);
108 int Index = MI->getOperand(FIOperandNum).getIndex();
110 switch (MI->getOpcode()) {
111 // SGPR register spill
112 case AMDGPU::SI_SPILL_S512_SAVE:
113 case AMDGPU::SI_SPILL_S256_SAVE:
114 case AMDGPU::SI_SPILL_S128_SAVE:
115 case AMDGPU::SI_SPILL_S64_SAVE:
116 case AMDGPU::SI_SPILL_S32_SAVE: {
117 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
119 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
120 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
121 &AMDGPU::SGPR_32RegClass, i);
122 struct SIMachineFunctionInfo::SpilledReg Spill =
123 MFI->getSpilledReg(MF, Index, i);
125 if (Spill.VGPR == AMDGPU::NoRegister) {
126 LLVMContext &Ctx = MF->getFunction()->getContext();
127 Ctx.emitError("Ran out of VGPRs for spilling SGPR");
130 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_WRITELANE_B32), Spill.VGPR)
135 MI->eraseFromParent();
139 // SGPR register restore
140 case AMDGPU::SI_SPILL_S512_RESTORE:
141 case AMDGPU::SI_SPILL_S256_RESTORE:
142 case AMDGPU::SI_SPILL_S128_RESTORE:
143 case AMDGPU::SI_SPILL_S64_RESTORE:
144 case AMDGPU::SI_SPILL_S32_RESTORE: {
145 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
147 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
148 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
149 &AMDGPU::SGPR_32RegClass, i);
150 bool isM0 = SubReg == AMDGPU::M0;
151 struct SIMachineFunctionInfo::SpilledReg Spill =
152 MFI->getSpilledReg(MF, Index, i);
154 if (Spill.VGPR == AMDGPU::NoRegister) {
155 LLVMContext &Ctx = MF->getFunction()->getContext();
156 Ctx.emitError("Ran out of VGPRs for spilling SGPR");
160 SubReg = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0);
163 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READLANE_B32), SubReg)
167 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
171 TII->insertNOPs(MI, 3);
172 MI->eraseFromParent();
176 // VGPR register spill
177 case AMDGPU::SI_SPILL_V512_SAVE:
178 case AMDGPU::SI_SPILL_V256_SAVE:
179 case AMDGPU::SI_SPILL_V128_SAVE:
180 case AMDGPU::SI_SPILL_V96_SAVE:
181 case AMDGPU::SI_SPILL_V64_SAVE:
182 case AMDGPU::SI_SPILL_V32_SAVE: {
183 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
184 unsigned SrcReg = MI->getOperand(0).getReg();
185 int64_t Offset = FrameInfo->getObjectOffset(Index);
186 unsigned Size = NumSubRegs * 4;
187 unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
189 for (unsigned i = 0, e = NumSubRegs; i != e; ++i) {
190 unsigned SubReg = NumSubRegs > 1 ?
191 getPhysRegSubReg(SrcReg, &AMDGPU::VGPR_32RegClass, i) :
194 MFI->LDSWaveSpillSize = std::max((unsigned)Offset + 4, (unsigned)MFI->LDSWaveSpillSize);
196 unsigned AddrReg = TII->calculateLDSSpillAddress(*MBB, MI, RS, TmpReg,
199 if (AddrReg == AMDGPU::NoRegister) {
200 LLVMContext &Ctx = MF->getFunction()->getContext();
201 Ctx.emitError("Ran out of VGPRs for spilling VGPRS");
202 AddrReg = AMDGPU::VGPR0;
205 // Store the value in LDS
206 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::DS_WRITE_B32))
208 .addReg(AddrReg, RegState::Kill) // addr
209 .addReg(SubReg) // data0
210 .addImm(0); // offset
213 MI->eraseFromParent();
216 case AMDGPU::SI_SPILL_V32_RESTORE:
217 case AMDGPU::SI_SPILL_V64_RESTORE:
218 case AMDGPU::SI_SPILL_V128_RESTORE:
219 case AMDGPU::SI_SPILL_V256_RESTORE:
220 case AMDGPU::SI_SPILL_V512_RESTORE: {
221 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
222 unsigned DstReg = MI->getOperand(0).getReg();
223 int64_t Offset = FrameInfo->getObjectOffset(Index);
224 unsigned Size = NumSubRegs * 4;
225 unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
227 // FIXME: We could use DS_READ_B64 here to optimize for larger registers.
228 for (unsigned i = 0, e = NumSubRegs; i != e; ++i) {
229 unsigned SubReg = NumSubRegs > 1 ?
230 getPhysRegSubReg(DstReg, &AMDGPU::VGPR_32RegClass, i) :
234 unsigned AddrReg = TII->calculateLDSSpillAddress(*MBB, MI, RS, TmpReg,
236 if (AddrReg == AMDGPU::NoRegister) {
237 LLVMContext &Ctx = MF->getFunction()->getContext();
238 Ctx.emitError("Ran out of VGPRs for spilling VGPRs");
239 AddrReg = AMDGPU::VGPR0;
242 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::DS_READ_B32), SubReg)
244 .addReg(AddrReg, RegState::Kill) // addr
247 MI->eraseFromParent();
252 int64_t Offset = FrameInfo->getObjectOffset(Index);
253 FIOp.ChangeToImmediate(Offset);
254 if (!TII->isImmOperandLegal(MI, FIOperandNum, FIOp)) {
255 unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VReg_32RegClass, MI, SPAdj);
256 BuildMI(*MBB, MI, MI->getDebugLoc(),
257 TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
259 FIOp.ChangeToRegister(TmpReg, false);
265 const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
267 switch(VT.SimpleTy) {
269 case MVT::i32: return &AMDGPU::VReg_32RegClass;
273 unsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const {
274 return getEncodingValue(Reg) & 0xff;
277 const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
278 assert(!TargetRegisterInfo::isVirtualRegister(Reg));
280 static const TargetRegisterClass *BaseClasses[] = {
281 &AMDGPU::VReg_32RegClass,
282 &AMDGPU::SReg_32RegClass,
283 &AMDGPU::VReg_64RegClass,
284 &AMDGPU::SReg_64RegClass,
285 &AMDGPU::VReg_96RegClass,
286 &AMDGPU::VReg_128RegClass,
287 &AMDGPU::SReg_128RegClass,
288 &AMDGPU::VReg_256RegClass,
289 &AMDGPU::SReg_256RegClass,
290 &AMDGPU::VReg_512RegClass
293 for (const TargetRegisterClass *BaseClass : BaseClasses) {
294 if (BaseClass->contains(Reg)) {
301 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
302 return getCommonSubClass(&AMDGPU::VReg_32RegClass, RC) ||
303 getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) ||
304 getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) ||
305 getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) ||
306 getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) ||
307 getCommonSubClass(&AMDGPU::VReg_512RegClass, RC);
310 const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
311 const TargetRegisterClass *SRC) const {
314 } else if (SRC == &AMDGPU::SCCRegRegClass) {
315 return &AMDGPU::VCCRegRegClass;
316 } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) {
317 return &AMDGPU::VReg_32RegClass;
318 } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) {
319 return &AMDGPU::VReg_64RegClass;
320 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_128RegClass)) {
321 return &AMDGPU::VReg_128RegClass;
322 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_256RegClass)) {
323 return &AMDGPU::VReg_256RegClass;
324 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_512RegClass)) {
325 return &AMDGPU::VReg_512RegClass;
330 const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
331 const TargetRegisterClass *RC, unsigned SubIdx) const {
332 if (SubIdx == AMDGPU::NoSubRegister)
335 // If this register has a sub-register, we can safely assume it is a 32-bit
336 // register, because all of SI's sub-registers are 32-bit.
337 if (isSGPRClass(RC)) {
338 return &AMDGPU::SGPR_32RegClass;
340 return &AMDGPU::VGPR_32RegClass;
344 unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
345 const TargetRegisterClass *SubRC,
346 unsigned Channel) const {
351 case 0: return AMDGPU::VCC_LO;
352 case 1: return AMDGPU::VCC_HI;
353 default: llvm_unreachable("Invalid SubIdx for VCC");
356 case AMDGPU::FLAT_SCR:
359 return AMDGPU::FLAT_SCR_LO;
361 return AMDGPU::FLAT_SCR_HI;
363 llvm_unreachable("Invalid SubIdx for FLAT_SCR");
370 return AMDGPU::EXEC_LO;
372 return AMDGPU::EXEC_HI;
374 llvm_unreachable("Invalid SubIdx for EXEC");
379 const TargetRegisterClass *RC = getPhysRegClass(Reg);
380 // 32-bit registers don't have sub-registers, so we can just return the
381 // Reg. We need to have this check here, because the calculation below
382 // using getHWRegIndex() will fail with special 32-bit registers like
383 // VCC_LO, VCC_HI, EXEC_LO, EXEC_HI and M0.
384 if (RC->getSize() == 4) {
385 assert(Channel == 0);
389 unsigned Index = getHWRegIndex(Reg);
390 return SubRC->getRegister(Index + Channel);
393 bool SIRegisterInfo::regClassCanUseLiteralConstant(int RCID) const {
395 default: return false;
396 case AMDGPU::SSrc_32RegClassID:
397 case AMDGPU::SSrc_64RegClassID:
398 case AMDGPU::VSrc_32RegClassID:
399 case AMDGPU::VSrc_64RegClassID:
404 bool SIRegisterInfo::regClassCanUseLiteralConstant(
405 const TargetRegisterClass *RC) const {
406 return regClassCanUseLiteralConstant(RC->getID());
409 bool SIRegisterInfo::regClassCanUseInlineConstant(int RCID) const {
410 if (regClassCanUseLiteralConstant(RCID))
414 default: return false;
415 case AMDGPU::VCSrc_32RegClassID:
416 case AMDGPU::VCSrc_64RegClassID:
417 case AMDGPU::SCSrc_32RegClassID:
422 bool SIRegisterInfo::regClassCanUseInlineConstant(
423 const TargetRegisterClass *RC) const {
424 return regClassCanUseInlineConstant(RC->getID());
428 unsigned SIRegisterInfo::getPreloadedValue(const MachineFunction &MF,
429 enum PreloadedValue Value) const {
431 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
433 case SIRegisterInfo::TGID_X:
434 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 0);
435 case SIRegisterInfo::TGID_Y:
436 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 1);
437 case SIRegisterInfo::TGID_Z:
438 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 2);
439 case SIRegisterInfo::SCRATCH_WAVE_OFFSET:
440 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 4);
441 case SIRegisterInfo::SCRATCH_PTR:
442 return AMDGPU::SGPR2_SGPR3;
443 case SIRegisterInfo::INPUT_PTR:
444 return AMDGPU::SGPR0_SGPR1;
445 case SIRegisterInfo::TIDIG_X:
446 return AMDGPU::VGPR0;
447 case SIRegisterInfo::TIDIG_Y:
448 return AMDGPU::VGPR1;
449 case SIRegisterInfo::TIDIG_Z:
450 return AMDGPU::VGPR2;
452 llvm_unreachable("unexpected preloaded value type");
455 /// \brief Returns a register that is not used at any point in the function.
456 /// If all registers are used, then this function will return
457 // AMDGPU::NoRegister.
458 unsigned SIRegisterInfo::findUnusedVGPR(const MachineRegisterInfo &MRI) const {
460 const TargetRegisterClass *RC = &AMDGPU::VGPR_32RegClass;
462 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
464 if (!MRI.isPhysRegUsed(*I))
467 return AMDGPU::NoRegister;