1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIRegisterInfo
13 //===----------------------------------------------------------------------===//
16 #ifndef SIREGISTERINFO_H_
17 #define SIREGISTERINFO_H_
19 #include "AMDGPURegisterInfo.h"
23 class AMDGPUTargetMachine;
25 struct SIRegisterInfo : public AMDGPURegisterInfo {
26 AMDGPUTargetMachine &TM;
28 SIRegisterInfo(AMDGPUTargetMachine &tm);
30 BitVector getReservedRegs(const MachineFunction &MF) const override;
32 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
33 MachineFunction &MF) const override;
35 /// \param RC is an AMDIL reg class.
37 /// \returns the SI register class that is equivalent to \p RC.
38 const TargetRegisterClass *
39 getISARegClass(const TargetRegisterClass *RC) const override;
41 /// \brief get the register class of the specified type to use in the
43 const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override;
45 unsigned getHWRegIndex(unsigned Reg) const override;
47 /// \brief Return the 'base' register class for this register.
48 /// e.g. SGPR0 => SReg_32, VGPR => VReg_32 SGPR0_SGPR1 -> SReg_32, etc.
49 const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
51 /// \returns true if this class contains only SGPR registers
52 bool isSGPRClass(const TargetRegisterClass *RC) const;
54 /// \returns true if this class contains VGPR registers.
55 bool hasVGPRs(const TargetRegisterClass *RC) const;
57 /// \returns A VGPR reg class with the same width as \p SRC
58 const TargetRegisterClass *getEquivalentVGPRClass(
59 const TargetRegisterClass *SRC) const;
61 /// \returns The register class that is used for a sub-register of \p RC for
62 /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
64 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
65 unsigned SubIdx) const;
68 } // End namespace llvm
70 #endif // SIREGISTERINFO_H_