1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIRegisterInfo
13 //===----------------------------------------------------------------------===//
16 #ifndef SIREGISTERINFO_H_
17 #define SIREGISTERINFO_H_
19 #include "AMDGPURegisterInfo.h"
23 struct SIRegisterInfo : public AMDGPURegisterInfo {
25 SIRegisterInfo(const AMDGPUSubtarget &st);
27 BitVector getReservedRegs(const MachineFunction &MF) const override;
29 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
30 MachineFunction &MF) const override;
32 /// \brief get the register class of the specified type to use in the
34 const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override;
36 unsigned getHWRegIndex(unsigned Reg) const override;
38 /// \brief Return the 'base' register class for this register.
39 /// e.g. SGPR0 => SReg_32, VGPR => VReg_32 SGPR0_SGPR1 -> SReg_32, etc.
40 const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
42 /// \returns true if this class contains only SGPR registers
43 bool isSGPRClass(const TargetRegisterClass *RC) const;
45 /// \returns true if this class contains VGPR registers.
46 bool hasVGPRs(const TargetRegisterClass *RC) const;
48 /// \returns A VGPR reg class with the same width as \p SRC
49 const TargetRegisterClass *getEquivalentVGPRClass(
50 const TargetRegisterClass *SRC) const;
52 /// \returns The register class that is used for a sub-register of \p RC for
53 /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
55 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
56 unsigned SubIdx) const;
58 /// \p Channel This is the register channel (e.g. a value from 0-16), not the
60 /// \returns The sub-register of Reg that is in Channel.
61 unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC,
62 unsigned Channel) const;
64 /// \returns True if operands defined with this register class can accept
65 /// inline immediates.
66 bool regClassCanUseImmediate(int RCID) const;
68 /// \returns True if operands defined with this register class can accept
69 /// inline immediates.
70 bool regClassCanUseImmediate(const TargetRegisterClass *RC) const;
73 } // End namespace llvm
75 #endif // SIREGISTERINFO_H_