2 class SIReg <string n, bits<16> encoding = 0> : Register<n> {
3 let Namespace = "AMDGPU";
4 let HWEncoding = encoding;
7 class SI_64 <string n, list<Register> subregs, bits<16> encoding> : RegisterWithSubRegs<n, subregs> {
8 let Namespace = "AMDGPU";
9 let SubRegIndices = [sub0, sub1];
10 let HWEncoding = encoding;
13 class SGPR_32 <bits<16> num, string name> : SIReg<name, num>;
15 class VGPR_32 <bits<16> num, string name> : SIReg<name, num> {
16 let HWEncoding{8} = 1;
20 def VCC : SIReg<"VCC", 106>;
21 def EXEC_LO : SIReg <"EXEC LO", 126>;
22 def EXEC_HI : SIReg <"EXEC HI", 127>;
23 def EXEC : SI_64<"EXEC", [EXEC_LO, EXEC_HI], 126>;
24 def SCC : SIReg<"SCC", 253>;
25 def SREG_LIT_0 : SIReg <"S LIT 0", 128>;
26 def SI_LITERAL_CONSTANT : SIReg<"LITERAL CONSTANT", 255>;
27 def M0 : SIReg <"M0", 124>;
29 //Interpolation registers
30 def PERSP_SAMPLE_I : SIReg <"PERSP_SAMPLE_I">;
31 def PERSP_SAMPLE_J : SIReg <"PERSP_SAMPLE_J">;
32 def PERSP_CENTER_I : SIReg <"PERSP_CENTER_I">;
33 def PERSP_CENTER_J : SIReg <"PERSP_CENTER_J">;
34 def PERSP_CENTROID_I : SIReg <"PERSP_CENTROID_I">;
35 def PERSP_CENTROID_J : SIReg <"PERP_CENTROID_J">;
36 def PERSP_I_W : SIReg <"PERSP_I_W">;
37 def PERSP_J_W : SIReg <"PERSP_J_W">;
38 def PERSP_1_W : SIReg <"PERSP_1_W">;
39 def LINEAR_SAMPLE_I : SIReg <"LINEAR_SAMPLE_I">;
40 def LINEAR_SAMPLE_J : SIReg <"LINEAR_SAMPLE_J">;
41 def LINEAR_CENTER_I : SIReg <"LINEAR_CENTER_I">;
42 def LINEAR_CENTER_J : SIReg <"LINEAR_CENTER_J">;
43 def LINEAR_CENTROID_I : SIReg <"LINEAR_CENTROID_I">;
44 def LINEAR_CENTROID_J : SIReg <"LINEAR_CENTROID_J">;
45 def LINE_STIPPLE_TEX_COORD : SIReg <"LINE_STIPPLE_TEX_COORD">;
46 def POS_X_FLOAT : SIReg <"POS_X_FLOAT">;
47 def POS_Y_FLOAT : SIReg <"POS_Y_FLOAT">;
48 def POS_Z_FLOAT : SIReg <"POS_Z_FLOAT">;
49 def POS_W_FLOAT : SIReg <"POS_W_FLOAT">;
50 def FRONT_FACE : SIReg <"FRONT_FACE">;
51 def ANCILLARY : SIReg <"ANCILLARY">;
52 def SAMPLE_COVERAGE : SIReg <"SAMPLE_COVERAGE">;
53 def POS_FIXED_PT : SIReg <"POS_FIXED_PT">;
55 // SGPR 32-bit registers
56 foreach Index = 0-101 in {
57 def SGPR#Index : SGPR_32 <Index, "SGPR"#Index>;
60 def SGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
61 (add (sequence "SGPR%u", 0, 101))>;
63 // SGPR 64-bit registers
64 def SGPR_64 : RegisterTuples<[sub0, sub1],
65 [(add (decimate SGPR_32, 2)),
66 (add(decimate (rotl SGPR_32, 1), 2))]>;
68 // SGPR 128-bit registers
69 def SGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
70 [(add (decimate SGPR_32, 4)),
71 (add (decimate (rotl SGPR_32, 1), 4)),
72 (add (decimate (rotl SGPR_32, 2), 4)),
73 (add (decimate (rotl SGPR_32, 3), 4))]>;
75 // SGPR 256-bit registers
76 def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
77 [(add (decimate SGPR_32, 8)),
78 (add (decimate (rotl SGPR_32, 1), 8)),
79 (add (decimate (rotl SGPR_32, 2), 8)),
80 (add (decimate (rotl SGPR_32, 3), 8)),
81 (add (decimate (rotl SGPR_32, 4), 8)),
82 (add (decimate (rotl SGPR_32, 5), 8)),
83 (add (decimate (rotl SGPR_32, 6), 8)),
84 (add (decimate (rotl SGPR_32, 7), 8))]>;
86 // VGPR 32-bit registers
87 foreach Index = 0-255 in {
88 def VGPR#Index : VGPR_32 <Index, "VGPR"#Index>;
91 def VGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
92 (add (sequence "VGPR%u", 0, 255))>;
94 // VGPR 64-bit registers
95 def VGPR_64 : RegisterTuples<[sub0, sub1],
97 (add (rotl VGPR_32, 1))]>;
99 // VGPR 128-bit registers
100 def VGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
102 (add (rotl VGPR_32, 1)),
103 (add (rotl VGPR_32, 2)),
104 (add (rotl VGPR_32, 3))]>;
106 // VGPR 256-bit registers
107 def VGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
109 (add (rotl VGPR_32, 1)),
110 (add (rotl VGPR_32, 2)),
111 (add (rotl VGPR_32, 3)),
112 (add (rotl VGPR_32, 4)),
113 (add (rotl VGPR_32, 5)),
114 (add (rotl VGPR_32, 6)),
115 (add (rotl VGPR_32, 7))]>;
117 // VGPR 512-bit registers
118 def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
119 sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15],
121 (add (rotl VGPR_32, 1)),
122 (add (rotl VGPR_32, 2)),
123 (add (rotl VGPR_32, 3)),
124 (add (rotl VGPR_32, 4)),
125 (add (rotl VGPR_32, 5)),
126 (add (rotl VGPR_32, 6)),
127 (add (rotl VGPR_32, 7)),
128 (add (rotl VGPR_32, 8)),
129 (add (rotl VGPR_32, 9)),
130 (add (rotl VGPR_32, 10)),
131 (add (rotl VGPR_32, 11)),
132 (add (rotl VGPR_32, 12)),
133 (add (rotl VGPR_32, 13)),
134 (add (rotl VGPR_32, 14)),
135 (add (rotl VGPR_32, 15))]>;
137 // Register class for all scalar registers (SGPRs + Special Registers)
138 def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
139 (add SGPR_32, SREG_LIT_0, M0, EXEC_LO, EXEC_HI)
142 def SReg_64 : RegisterClass<"AMDGPU", [i64], 64, (add SGPR_64, VCC, EXEC)>;
144 def SReg_1 : RegisterClass<"AMDGPU", [i1], 1, (add VCC, SGPR_64, EXEC)>;
146 def SReg_128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add SGPR_128)>;
148 def SReg_256 : RegisterClass<"AMDGPU", [v8i32], 256, (add SGPR_256)>;
150 // Register class for all vector registers (VGPRs + Interploation Registers)
151 def VReg_32 : RegisterClass<"AMDGPU", [f32, i32, v1i32], 32,
153 PERSP_SAMPLE_I, PERSP_SAMPLE_J,
154 PERSP_CENTER_I, PERSP_CENTER_J,
155 PERSP_CENTROID_I, PERSP_CENTROID_J,
156 PERSP_I_W, PERSP_J_W, PERSP_1_W,
157 LINEAR_SAMPLE_I, LINEAR_SAMPLE_J,
158 LINEAR_CENTER_I, LINEAR_CENTER_J,
159 LINEAR_CENTROID_I, LINEAR_CENTROID_J,
160 LINE_STIPPLE_TEX_COORD,
172 def VReg_64 : RegisterClass<"AMDGPU", [i64, v2i32], 64, (add VGPR_64)>;
174 def VReg_128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add VGPR_128)>;
176 def VReg_256 : RegisterClass<"AMDGPU", [v8i32], 256, (add VGPR_256)>;
178 def VReg_512 : RegisterClass<"AMDGPU", [v16i32], 512, (add VGPR_512)>;
180 // AllReg_* - A set of all scalar and vector registers of a given width.
181 def AllReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32, (add VReg_32, SReg_32)>;
183 def AllReg_64 : RegisterClass<"AMDGPU", [f64, i64], 64, (add SReg_64, VReg_64)>;
185 // Special register classes for predicates and the M0 register
186 def SCCReg : RegisterClass<"AMDGPU", [i1], 1, (add SCC)>;
187 def VCCReg : RegisterClass<"AMDGPU", [i1], 1, (add VCC)>;
188 def EXECReg : RegisterClass<"AMDGPU", [i1], 1, (add EXEC)>;
189 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;