1 //===-- SIRegisterInfo.td - SI Register defs ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the SI registers
12 //===----------------------------------------------------------------------===//
14 class SIReg <string n, bits<16> encoding = 0> : Register<n> {
15 let Namespace = "AMDGPU";
16 let HWEncoding = encoding;
20 def VCC_LO : SIReg<"vcc_lo", 106>;
21 def VCC_HI : SIReg<"vcc_hi", 107>;
23 // VCC for 64-bit instructions
24 def VCC : RegisterWithSubRegs<"VCC", [VCC_LO, VCC_HI]> {
25 let Namespace = "AMDGPU";
26 let SubRegIndices = [sub0, sub1];
30 def EXEC_LO : SIReg<"EXEC", 126>;
31 def EXEC_HI : SIReg<"EXEC", 127>;
33 def EXEC : RegisterWithSubRegs<"EXEC", [EXEC_LO, EXEC_HI]> {
34 let Namespace = "AMDGPU";
35 let SubRegIndices = [sub0, sub1];
39 def SCC : SIReg<"SCC", 253>;
40 def M0 : SIReg <"M0", 124>;
43 foreach Index = 0-101 in {
44 def SGPR#Index : SIReg <"SGPR"#Index, Index>;
48 foreach Index = 0-255 in {
49 def VGPR#Index : SIReg <"VGPR"#Index, Index> {
50 let HWEncoding{8} = 1;
54 //===----------------------------------------------------------------------===//
55 // Groupings using register classes and tuples
56 //===----------------------------------------------------------------------===//
58 // SGPR 32-bit registers
59 def SGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
60 (add (sequence "SGPR%u", 0, 101))>;
62 // SGPR 64-bit registers
63 def SGPR_64Regs : RegisterTuples<[sub0, sub1],
64 [(add (decimate (trunc SGPR_32, 101), 2)),
65 (add (decimate (shl SGPR_32, 1), 2))]>;
67 // SGPR 128-bit registers
68 def SGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
69 [(add (decimate (trunc SGPR_32, 99), 4)),
70 (add (decimate (shl SGPR_32, 1), 4)),
71 (add (decimate (shl SGPR_32, 2), 4)),
72 (add (decimate (shl SGPR_32, 3), 4))]>;
74 // SGPR 256-bit registers
75 def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
76 [(add (decimate (trunc SGPR_32, 95), 4)),
77 (add (decimate (shl SGPR_32, 1), 4)),
78 (add (decimate (shl SGPR_32, 2), 4)),
79 (add (decimate (shl SGPR_32, 3), 4)),
80 (add (decimate (shl SGPR_32, 4), 4)),
81 (add (decimate (shl SGPR_32, 5), 4)),
82 (add (decimate (shl SGPR_32, 6), 4)),
83 (add (decimate (shl SGPR_32, 7), 4))]>;
85 // SGPR 512-bit registers
86 def SGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
87 sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15],
88 [(add (decimate (trunc SGPR_32, 87), 4)),
89 (add (decimate (shl SGPR_32, 1), 4)),
90 (add (decimate (shl SGPR_32, 2), 4)),
91 (add (decimate (shl SGPR_32, 3), 4)),
92 (add (decimate (shl SGPR_32, 4), 4)),
93 (add (decimate (shl SGPR_32, 5), 4)),
94 (add (decimate (shl SGPR_32, 6), 4)),
95 (add (decimate (shl SGPR_32, 7), 4)),
96 (add (decimate (shl SGPR_32, 8), 4)),
97 (add (decimate (shl SGPR_32, 9), 4)),
98 (add (decimate (shl SGPR_32, 10), 4)),
99 (add (decimate (shl SGPR_32, 11), 4)),
100 (add (decimate (shl SGPR_32, 12), 4)),
101 (add (decimate (shl SGPR_32, 13), 4)),
102 (add (decimate (shl SGPR_32, 14), 4)),
103 (add (decimate (shl SGPR_32, 15), 4))]>;
105 // VGPR 32-bit registers
106 def VGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
107 (add (sequence "VGPR%u", 0, 255))>;
109 // VGPR 64-bit registers
110 def VGPR_64 : RegisterTuples<[sub0, sub1],
111 [(add (trunc VGPR_32, 255)),
112 (add (shl VGPR_32, 1))]>;
114 // VGPR 96-bit registers
115 def VGPR_96 : RegisterTuples<[sub0, sub1, sub2],
116 [(add (trunc VGPR_32, 254)),
117 (add (shl VGPR_32, 1)),
118 (add (shl VGPR_32, 2))]>;
120 // VGPR 128-bit registers
121 def VGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
122 [(add (trunc VGPR_32, 253)),
123 (add (shl VGPR_32, 1)),
124 (add (shl VGPR_32, 2)),
125 (add (shl VGPR_32, 3))]>;
127 // VGPR 256-bit registers
128 def VGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
129 [(add (trunc VGPR_32, 249)),
130 (add (shl VGPR_32, 1)),
131 (add (shl VGPR_32, 2)),
132 (add (shl VGPR_32, 3)),
133 (add (shl VGPR_32, 4)),
134 (add (shl VGPR_32, 5)),
135 (add (shl VGPR_32, 6)),
136 (add (shl VGPR_32, 7))]>;
138 // VGPR 512-bit registers
139 def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
140 sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15],
141 [(add (trunc VGPR_32, 241)),
142 (add (shl VGPR_32, 1)),
143 (add (shl VGPR_32, 2)),
144 (add (shl VGPR_32, 3)),
145 (add (shl VGPR_32, 4)),
146 (add (shl VGPR_32, 5)),
147 (add (shl VGPR_32, 6)),
148 (add (shl VGPR_32, 7)),
149 (add (shl VGPR_32, 8)),
150 (add (shl VGPR_32, 9)),
151 (add (shl VGPR_32, 10)),
152 (add (shl VGPR_32, 11)),
153 (add (shl VGPR_32, 12)),
154 (add (shl VGPR_32, 13)),
155 (add (shl VGPR_32, 14)),
156 (add (shl VGPR_32, 15))]>;
158 //===----------------------------------------------------------------------===//
159 // Register classes used as source and destination
160 //===----------------------------------------------------------------------===//
162 // Special register classes for predicates and the M0 register
163 def SCCReg : RegisterClass<"AMDGPU", [i32, i1], 32, (add SCC)>;
164 def VCCReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add VCC)>;
165 def EXECReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add EXEC)>;
166 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
168 // Register class for all scalar registers (SGPRs + Special Registers)
169 def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
170 (add SGPR_32, M0Reg, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI)
173 def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64], 64, (add SGPR_64Regs)>;
175 def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, i1], 64,
176 (add SGPR_64, VCCReg, EXECReg)
179 def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8], 128, (add SGPR_128)>;
181 def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add SGPR_256)>;
183 def SReg_512 : RegisterClass<"AMDGPU", [v64i8, v16i32], 512, (add SGPR_512)>;
185 // Register class for all vector registers (VGPRs + Interploation Registers)
186 def VReg_32 : RegisterClass<"AMDGPU", [i32, f32, v1i32], 32, (add VGPR_32)>;
188 def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32], 64, (add VGPR_64)>;
190 def VReg_96 : RegisterClass<"AMDGPU", [untyped], 96, (add VGPR_96)> {
194 def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32], 128, (add VGPR_128)>;
196 def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256)>;
198 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>;
200 def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)>;
202 //===----------------------------------------------------------------------===//
203 // [SV]Src_(32|64) register classes, can have either an immediate or an register
204 //===----------------------------------------------------------------------===//
206 def SSrc_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add SReg_32)>;
208 def SSrc_64 : RegisterClass<"AMDGPU", [i64, f64, i1], 64, (add SReg_64)>;
210 def VSrc_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VReg_32, SReg_32)>;
212 def VSrc_64 : RegisterClass<"AMDGPU", [i64, f64], 64, (add VReg_64, SReg_64)>;
214 //===----------------------------------------------------------------------===//
215 // SGPR and VGPR register classes
216 //===----------------------------------------------------------------------===//
218 def VSrc_128 : RegisterClass<"AMDGPU", [v4i32, v4f32], 128,
219 (add VReg_128, SReg_128)>;