1 //===-- SIRegisterInfo.td - SI Register defs ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the SI registers
12 //===----------------------------------------------------------------------===//
14 class SIReg <string n, bits<16> encoding = 0> : Register<n> {
15 let Namespace = "AMDGPU";
16 let HWEncoding = encoding;
20 def VCC_LO : SIReg<"vcc_lo", 106>;
21 def VCC_HI : SIReg<"vcc_hi", 107>;
23 // VCC for 64-bit instructions
24 def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]> {
25 let Namespace = "AMDGPU";
26 let SubRegIndices = [sub0, sub1];
30 def EXEC_LO : SIReg<"exec_lo", 126>;
31 def EXEC_HI : SIReg<"exec_hi", 127>;
33 def EXEC : RegisterWithSubRegs<"EXEC", [EXEC_LO, EXEC_HI]> {
34 let Namespace = "AMDGPU";
35 let SubRegIndices = [sub0, sub1];
39 def SCC : SIReg<"scc", 253>;
40 def M0 : SIReg <"m0", 124>;
42 def FLAT_SCR_LO : SIReg<"flat_scr_lo", 104>; // Offset in units of 256-bytes.
43 def FLAT_SCR_HI : SIReg<"flat_scr_hi", 105>; // Size is the per-thread scratch size, in bytes.
45 // Pair to indicate location of scratch space for flat accesses.
46 def FLAT_SCR : RegisterWithSubRegs <"flat_scr", [FLAT_SCR_LO, FLAT_SCR_HI]> {
47 let Namespace = "AMDGPU";
48 let SubRegIndices = [sub0, sub1];
53 foreach Index = 0-101 in {
54 def SGPR#Index : SIReg <"SGPR"#Index, Index>;
58 foreach Index = 0-255 in {
59 def VGPR#Index : SIReg <"VGPR"#Index, Index> {
60 let HWEncoding{8} = 1;
64 //===----------------------------------------------------------------------===//
65 // Groupings using register classes and tuples
66 //===----------------------------------------------------------------------===//
68 // SGPR 32-bit registers
69 def SGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
70 (add (sequence "SGPR%u", 0, 101))>;
72 // SGPR 64-bit registers
73 def SGPR_64Regs : RegisterTuples<[sub0, sub1],
74 [(add (decimate (trunc SGPR_32, 101), 2)),
75 (add (decimate (shl SGPR_32, 1), 2))]>;
77 // SGPR 128-bit registers
78 def SGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
79 [(add (decimate (trunc SGPR_32, 99), 4)),
80 (add (decimate (shl SGPR_32, 1), 4)),
81 (add (decimate (shl SGPR_32, 2), 4)),
82 (add (decimate (shl SGPR_32, 3), 4))]>;
84 // SGPR 256-bit registers
85 def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
86 [(add (decimate (trunc SGPR_32, 95), 4)),
87 (add (decimate (shl SGPR_32, 1), 4)),
88 (add (decimate (shl SGPR_32, 2), 4)),
89 (add (decimate (shl SGPR_32, 3), 4)),
90 (add (decimate (shl SGPR_32, 4), 4)),
91 (add (decimate (shl SGPR_32, 5), 4)),
92 (add (decimate (shl SGPR_32, 6), 4)),
93 (add (decimate (shl SGPR_32, 7), 4))]>;
95 // SGPR 512-bit registers
96 def SGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
97 sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15],
98 [(add (decimate (trunc SGPR_32, 87), 4)),
99 (add (decimate (shl SGPR_32, 1), 4)),
100 (add (decimate (shl SGPR_32, 2), 4)),
101 (add (decimate (shl SGPR_32, 3), 4)),
102 (add (decimate (shl SGPR_32, 4), 4)),
103 (add (decimate (shl SGPR_32, 5), 4)),
104 (add (decimate (shl SGPR_32, 6), 4)),
105 (add (decimate (shl SGPR_32, 7), 4)),
106 (add (decimate (shl SGPR_32, 8), 4)),
107 (add (decimate (shl SGPR_32, 9), 4)),
108 (add (decimate (shl SGPR_32, 10), 4)),
109 (add (decimate (shl SGPR_32, 11), 4)),
110 (add (decimate (shl SGPR_32, 12), 4)),
111 (add (decimate (shl SGPR_32, 13), 4)),
112 (add (decimate (shl SGPR_32, 14), 4)),
113 (add (decimate (shl SGPR_32, 15), 4))]>;
115 // VGPR 32-bit registers
116 def VGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
117 (add (sequence "VGPR%u", 0, 255))>;
119 // VGPR 64-bit registers
120 def VGPR_64 : RegisterTuples<[sub0, sub1],
121 [(add (trunc VGPR_32, 255)),
122 (add (shl VGPR_32, 1))]>;
124 // VGPR 96-bit registers
125 def VGPR_96 : RegisterTuples<[sub0, sub1, sub2],
126 [(add (trunc VGPR_32, 254)),
127 (add (shl VGPR_32, 1)),
128 (add (shl VGPR_32, 2))]>;
130 // VGPR 128-bit registers
131 def VGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
132 [(add (trunc VGPR_32, 253)),
133 (add (shl VGPR_32, 1)),
134 (add (shl VGPR_32, 2)),
135 (add (shl VGPR_32, 3))]>;
137 // VGPR 256-bit registers
138 def VGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
139 [(add (trunc VGPR_32, 249)),
140 (add (shl VGPR_32, 1)),
141 (add (shl VGPR_32, 2)),
142 (add (shl VGPR_32, 3)),
143 (add (shl VGPR_32, 4)),
144 (add (shl VGPR_32, 5)),
145 (add (shl VGPR_32, 6)),
146 (add (shl VGPR_32, 7))]>;
148 // VGPR 512-bit registers
149 def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
150 sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15],
151 [(add (trunc VGPR_32, 241)),
152 (add (shl VGPR_32, 1)),
153 (add (shl VGPR_32, 2)),
154 (add (shl VGPR_32, 3)),
155 (add (shl VGPR_32, 4)),
156 (add (shl VGPR_32, 5)),
157 (add (shl VGPR_32, 6)),
158 (add (shl VGPR_32, 7)),
159 (add (shl VGPR_32, 8)),
160 (add (shl VGPR_32, 9)),
161 (add (shl VGPR_32, 10)),
162 (add (shl VGPR_32, 11)),
163 (add (shl VGPR_32, 12)),
164 (add (shl VGPR_32, 13)),
165 (add (shl VGPR_32, 14)),
166 (add (shl VGPR_32, 15))]>;
168 //===----------------------------------------------------------------------===//
169 // Register classes used as source and destination
170 //===----------------------------------------------------------------------===//
172 // Special register classes for predicates and the M0 register
173 def SCCReg : RegisterClass<"AMDGPU", [i32, i1], 32, (add SCC)> {
174 let CopyCost = -1; // Theoretically it is possible to read from SCC,
175 // but it should never be necessary.
178 def VCCReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add VCC)>;
179 def EXECReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add EXEC)>;
180 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
182 // Register class for all scalar registers (SGPRs + Special Registers)
183 def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
184 (add SGPR_32, M0Reg, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI)
187 def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 64, (add SGPR_64Regs)>;
189 def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 64,
190 (add SGPR_64, VCCReg, EXECReg, FLAT_SCR)
193 def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8], 128, (add SGPR_128)>;
195 def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add SGPR_256)>;
197 def SReg_512 : RegisterClass<"AMDGPU", [v64i8, v16i32], 512, (add SGPR_512)>;
199 // Register class for all vector registers (VGPRs + Interploation Registers)
200 def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32], 64, (add VGPR_64)>;
202 def VReg_96 : RegisterClass<"AMDGPU", [untyped], 96, (add VGPR_96)> {
206 def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32], 128, (add VGPR_128)>;
208 def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256)>;
210 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>;
212 def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> {
216 class RegImmOperand <RegisterClass rc> : RegisterOperand<rc> {
217 let OperandNamespace = "AMDGPU";
218 let OperandType = "OPERAND_REG_IMM32";
221 class RegInlineOperand <RegisterClass rc> : RegisterOperand<rc> {
222 let OperandNamespace = "AMDGPU";
223 let OperandType = "OPERAND_REG_INLINE_C";
226 //===----------------------------------------------------------------------===//
227 // SSrc_* Operands with an SGPR or a 32-bit immediate
228 //===----------------------------------------------------------------------===//
230 def SSrc_32 : RegImmOperand<SReg_32>;
232 def SSrc_64 : RegImmOperand<SReg_64>;
234 //===----------------------------------------------------------------------===//
235 // SCSrc_* Operands with an SGPR or a inline constant
236 //===----------------------------------------------------------------------===//
238 def SCSrc_32 : RegInlineOperand<SReg_32>;
240 //===----------------------------------------------------------------------===//
241 // VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate
242 //===----------------------------------------------------------------------===//
244 def VS_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VGPR_32, SReg_32)>;
246 def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 64, (add VReg_64, SReg_64)>;
248 def VSrc_32 : RegImmOperand<VS_32>;
250 def VSrc_64 : RegImmOperand<VS_64>;
252 //===----------------------------------------------------------------------===//
253 // VCSrc_* Operands with an SGPR, VGPR or an inline constant
254 //===----------------------------------------------------------------------===//
256 def VCSrc_32 : RegInlineOperand<VS_32>;
258 def VCSrc_64 : RegInlineOperand<VS_64>;
260 //===----------------------------------------------------------------------===//
261 // SGPR and VGPR register classes
262 //===----------------------------------------------------------------------===//
264 def VSrc_128 : RegisterClass<"AMDGPU", [v4i32, v4f32], 128,
265 (add VReg_128, SReg_128)>;