1 //===-- SIRegisterInfo.td - SI Register defs ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the SI registers
12 //===----------------------------------------------------------------------===//
14 class SIReg <string n, bits<16> encoding = 0> : Register<n> {
15 let Namespace = "AMDGPU";
16 let HWEncoding = encoding;
20 def VCC_LO : SIReg<"vcc_lo", 106>;
21 def VCC_HI : SIReg<"vcc_hi", 107>;
23 // VCC for 64-bit instructions
24 def VCC : RegisterWithSubRegs<"VCC", [VCC_LO, VCC_HI]> {
25 let Namespace = "AMDGPU";
26 let SubRegIndices = [sub0, sub1];
30 def EXEC : SIReg<"EXEC", 126>;
31 def SCC : SIReg<"SCC", 253>;
32 def M0 : SIReg <"M0", 124>;
35 foreach Index = 0-101 in {
36 def SGPR#Index : SIReg <"SGPR"#Index, Index>;
40 foreach Index = 0-255 in {
41 def VGPR#Index : SIReg <"VGPR"#Index, Index> {
42 let HWEncoding{8} = 1;
46 //===----------------------------------------------------------------------===//
47 // Groupings using register classes and tuples
48 //===----------------------------------------------------------------------===//
50 // SGPR 32-bit registers
51 def SGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
52 (add (sequence "SGPR%u", 0, 101))>;
54 // SGPR 64-bit registers
55 def SGPR_64Regs : RegisterTuples<[sub0, sub1],
56 [(add (decimate (trunc SGPR_32, 101), 2)),
57 (add (decimate (shl SGPR_32, 1), 2))]>;
59 // SGPR 128-bit registers
60 def SGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
61 [(add (decimate (trunc SGPR_32, 99), 4)),
62 (add (decimate (shl SGPR_32, 1), 4)),
63 (add (decimate (shl SGPR_32, 2), 4)),
64 (add (decimate (shl SGPR_32, 3), 4))]>;
66 // SGPR 256-bit registers
67 def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
68 [(add (decimate (trunc SGPR_32, 95), 4)),
69 (add (decimate (shl SGPR_32, 1), 4)),
70 (add (decimate (shl SGPR_32, 2), 4)),
71 (add (decimate (shl SGPR_32, 3), 4)),
72 (add (decimate (shl SGPR_32, 4), 4)),
73 (add (decimate (shl SGPR_32, 5), 4)),
74 (add (decimate (shl SGPR_32, 6), 4)),
75 (add (decimate (shl SGPR_32, 7), 4))]>;
77 // SGPR 512-bit registers
78 def SGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
79 sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15],
80 [(add (decimate (trunc SGPR_32, 87), 4)),
81 (add (decimate (shl SGPR_32, 1), 4)),
82 (add (decimate (shl SGPR_32, 2), 4)),
83 (add (decimate (shl SGPR_32, 3), 4)),
84 (add (decimate (shl SGPR_32, 4), 4)),
85 (add (decimate (shl SGPR_32, 5), 4)),
86 (add (decimate (shl SGPR_32, 6), 4)),
87 (add (decimate (shl SGPR_32, 7), 4)),
88 (add (decimate (shl SGPR_32, 8), 4)),
89 (add (decimate (shl SGPR_32, 9), 4)),
90 (add (decimate (shl SGPR_32, 10), 4)),
91 (add (decimate (shl SGPR_32, 11), 4)),
92 (add (decimate (shl SGPR_32, 12), 4)),
93 (add (decimate (shl SGPR_32, 13), 4)),
94 (add (decimate (shl SGPR_32, 14), 4)),
95 (add (decimate (shl SGPR_32, 15), 4))]>;
97 // VGPR 32-bit registers
98 def VGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
99 (add (sequence "VGPR%u", 0, 255))>;
101 // VGPR 64-bit registers
102 def VGPR_64 : RegisterTuples<[sub0, sub1],
103 [(add (trunc VGPR_32, 255)),
104 (add (shl VGPR_32, 1))]>;
106 // VGPR 96-bit registers
107 def VGPR_96 : RegisterTuples<[sub0, sub1, sub2],
108 [(add (trunc VGPR_32, 254)),
109 (add (shl VGPR_32, 1)),
110 (add (shl VGPR_32, 2))]>;
112 // VGPR 128-bit registers
113 def VGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
114 [(add (trunc VGPR_32, 253)),
115 (add (shl VGPR_32, 1)),
116 (add (shl VGPR_32, 2)),
117 (add (shl VGPR_32, 3))]>;
119 // VGPR 256-bit registers
120 def VGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
121 [(add (trunc VGPR_32, 249)),
122 (add (shl VGPR_32, 1)),
123 (add (shl VGPR_32, 2)),
124 (add (shl VGPR_32, 3)),
125 (add (shl VGPR_32, 4)),
126 (add (shl VGPR_32, 5)),
127 (add (shl VGPR_32, 6)),
128 (add (shl VGPR_32, 7))]>;
130 // VGPR 512-bit registers
131 def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
132 sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15],
133 [(add (trunc VGPR_32, 241)),
134 (add (shl VGPR_32, 1)),
135 (add (shl VGPR_32, 2)),
136 (add (shl VGPR_32, 3)),
137 (add (shl VGPR_32, 4)),
138 (add (shl VGPR_32, 5)),
139 (add (shl VGPR_32, 6)),
140 (add (shl VGPR_32, 7)),
141 (add (shl VGPR_32, 8)),
142 (add (shl VGPR_32, 9)),
143 (add (shl VGPR_32, 10)),
144 (add (shl VGPR_32, 11)),
145 (add (shl VGPR_32, 12)),
146 (add (shl VGPR_32, 13)),
147 (add (shl VGPR_32, 14)),
148 (add (shl VGPR_32, 15))]>;
150 //===----------------------------------------------------------------------===//
151 // Register classes used as source and destination
152 //===----------------------------------------------------------------------===//
154 // Special register classes for predicates and the M0 register
155 def SCCReg : RegisterClass<"AMDGPU", [i32, i1], 32, (add SCC)>;
156 def VCCReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add VCC)>;
157 def EXECReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add EXEC)>;
158 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
160 // Register class for all scalar registers (SGPRs + Special Registers)
161 def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
162 (add SGPR_32, M0Reg, VCC_LO)
165 def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64], 64, (add SGPR_64Regs)>;
167 def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, i1], 64,
168 (add SGPR_64Regs, VCCReg, EXECReg)
171 def SReg_128 : RegisterClass<"AMDGPU", [v4i32], 128, (add SGPR_128)>;
173 def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add SGPR_256)>;
175 def SReg_512 : RegisterClass<"AMDGPU", [v64i8, v16i32], 512, (add SGPR_512)>;
177 // Register class for all vector registers (VGPRs + Interploation Registers)
178 def VReg_32 : RegisterClass<"AMDGPU", [i32, f32, v1i32], 32, (add VGPR_32)>;
180 def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32], 64, (add VGPR_64)>;
182 def VReg_96 : RegisterClass<"AMDGPU", [untyped], 96, (add VGPR_96)> {
186 def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32], 128, (add VGPR_128)>;
188 def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256)>;
190 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>;
192 def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)>;
194 //===----------------------------------------------------------------------===//
195 // [SV]Src_(32|64) register classes, can have either an immediate or an register
196 //===----------------------------------------------------------------------===//
198 def SSrc_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add SReg_32)>;
200 def SSrc_64 : RegisterClass<"AMDGPU", [i64, f64, i1], 64, (add SReg_64)>;
202 def VSrc_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VReg_32, SReg_32)>;
204 def VSrc_64 : RegisterClass<"AMDGPU", [i64, f64], 64, (add VReg_64, SReg_64)>;
206 //===----------------------------------------------------------------------===//
207 // SGPR and VGPR register classes
208 //===----------------------------------------------------------------------===//
210 def VSrc_128 : RegisterClass<"AMDGPU", [v4i32, v4f32], 128,
211 (add VReg_128, SReg_128)>;