1 //===-- SISchedule.td - SI Scheduling definitons -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // MachineModel definitions for Southern Islands (SI)
12 //===----------------------------------------------------------------------===//
14 def WriteBranch : SchedWrite;
15 def WriteExport : SchedWrite;
16 def WriteLDS : SchedWrite;
17 def WriteSALU : SchedWrite;
18 def WriteSMEM : SchedWrite;
19 def WriteVMEM : SchedWrite;
21 // Vector ALU instructions
22 def Write32Bit : SchedWrite;
23 def WriteQuarterRate32 : SchedWrite;
25 def WriteFloatFMA : SchedWrite;
27 def WriteDouble : SchedWrite;
28 def WriteDoubleAdd : SchedWrite;
30 def SIFullSpeedModel : SchedMachineModel;
31 def SIQuarterSpeedModel : SchedMachineModel;
33 // BufferSize = 0 means the processors are in-order.
34 let BufferSize = 0 in {
36 // XXX: Are the resource counts correct?
37 def HWBranch : ProcResource<1>;
38 def HWExport : ProcResource<7>; // Taken from S_WAITCNT
39 def HWLGKM : ProcResource<31>; // Taken from S_WAITCNT
40 def HWSALU : ProcResource<1>;
41 def HWVMEM : ProcResource<15>; // Taken from S_WAITCNT
42 def HWVALU : ProcResource<1>;
46 class HWWriteRes<SchedWrite write, list<ProcResourceKind> resources,
47 int latency> : WriteRes<write, resources> {
48 let Latency = latency;
51 class HWVALUWriteRes<SchedWrite write, int latency> :
52 HWWriteRes<write, [HWVALU], latency>;
55 // The latency numbers are taken from AMD Accelerated Parallel Processing
56 // guide. They may not be acurate.
58 // The latency values are 1 / (operations / cycle) / 4.
59 multiclass SICommonWriteRes {
61 def : HWWriteRes<WriteBranch, [HWBranch], 100>; // XXX: Guessed ???
62 def : HWWriteRes<WriteExport, [HWExport], 100>; // XXX: Guessed ???
63 def : HWWriteRes<WriteLDS, [HWLGKM], 32>; // 2 - 64
64 def : HWWriteRes<WriteSALU, [HWSALU], 1>;
65 def : HWWriteRes<WriteSMEM, [HWLGKM], 10>; // XXX: Guessed ???
66 def : HWWriteRes<WriteVMEM, [HWVMEM], 450>; // 300 - 600
68 def : HWVALUWriteRes<Write32Bit, 1>;
69 def : HWVALUWriteRes<WriteQuarterRate32, 4>;
73 let SchedModel = SIFullSpeedModel in {
75 defm : SICommonWriteRes;
77 def : HWVALUWriteRes<WriteFloatFMA, 1>;
78 def : HWVALUWriteRes<WriteDouble, 4>;
79 def : HWVALUWriteRes<WriteDoubleAdd, 2>;
81 } // End SchedModel = SIFullSpeedModel
83 let SchedModel = SIQuarterSpeedModel in {
85 defm : SICommonWriteRes;
87 def : HWVALUWriteRes<WriteFloatFMA, 16>;
88 def : HWVALUWriteRes<WriteDouble, 16>;
89 def : HWVALUWriteRes<WriteDoubleAdd, 8>;
91 } // End SchedModel = SIQuarterSpeedModel