1 //===-- SIShrinkInstructions.cpp - Shrink Instructions --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 /// The pass tries to use the 32-bit encoding for instructions when possible.
9 //===----------------------------------------------------------------------===//
13 #include "SIInstrInfo.h"
14 #include "llvm/ADT/Statistic.h"
15 #include "llvm/CodeGen/MachineFunctionPass.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/IR/Constants.h"
19 #include "llvm/IR/LLVMContext.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Target/TargetMachine.h"
24 #define DEBUG_TYPE "si-shrink-instructions"
26 STATISTIC(NumInstructionsShrunk,
27 "Number of 64-bit instruction reduced to 32-bit.");
28 STATISTIC(NumLiteralConstantsFolded,
29 "Number of literal constants folded into 32-bit instructions.");
32 void initializeSIShrinkInstructionsPass(PassRegistry&);
39 class SIShrinkInstructions : public MachineFunctionPass {
44 SIShrinkInstructions() : MachineFunctionPass(ID) {
47 virtual bool runOnMachineFunction(MachineFunction &MF) override;
49 virtual const char *getPassName() const override {
50 return "SI Shrink Instructions";
53 virtual void getAnalysisUsage(AnalysisUsage &AU) const override {
55 MachineFunctionPass::getAnalysisUsage(AU);
59 } // End anonymous namespace.
61 INITIALIZE_PASS_BEGIN(SIShrinkInstructions, DEBUG_TYPE,
62 "SI Lower il Copies", false, false)
63 INITIALIZE_PASS_END(SIShrinkInstructions, DEBUG_TYPE,
64 "SI Lower il Copies", false, false)
66 char SIShrinkInstructions::ID = 0;
68 FunctionPass *llvm::createSIShrinkInstructionsPass() {
69 return new SIShrinkInstructions();
72 static bool isVGPR(const MachineOperand *MO, const SIRegisterInfo &TRI,
73 const MachineRegisterInfo &MRI) {
77 if (TargetRegisterInfo::isVirtualRegister(MO->getReg()))
78 return TRI.hasVGPRs(MRI.getRegClass(MO->getReg()));
80 return TRI.hasVGPRs(TRI.getPhysRegClass(MO->getReg()));
83 static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII,
84 const SIRegisterInfo &TRI,
85 const MachineRegisterInfo &MRI) {
87 const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2);
88 // Can't shrink instruction with three operands.
92 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
93 const MachineOperand *Src1Mod =
94 TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers);
96 if (Src1 && (!isVGPR(Src1, TRI, MRI) || (Src1Mod && Src1Mod->getImm() != 0)))
99 // We don't need to check src0, all input types are legal, so just make
100 // sure src0 isn't using any modifiers.
101 const MachineOperand *Src0Mod =
102 TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers);
103 if (Src0Mod && Src0Mod->getImm() != 0)
106 // Check output modifiers
107 const MachineOperand *Omod = TII->getNamedOperand(MI, AMDGPU::OpName::omod);
108 if (Omod && Omod->getImm() != 0)
111 const MachineOperand *Clamp = TII->getNamedOperand(MI, AMDGPU::OpName::clamp);
112 return !Clamp || Clamp->getImm() == 0;
115 /// \brief This function checks \p MI for operands defined by a move immediate
116 /// instruction and then folds the literal constant into the instruction if it
117 /// can. This function assumes that \p MI is a VOP1, VOP2, or VOPC instruction
118 /// and will only fold literal constants if we are still in SSA.
119 static void foldImmediates(MachineInstr &MI, const SIInstrInfo *TII,
120 MachineRegisterInfo &MRI, bool TryToCommute = true) {
125 assert(TII->isVOP1(MI.getOpcode()) || TII->isVOP2(MI.getOpcode()) ||
126 TII->isVOPC(MI.getOpcode()));
128 const SIRegisterInfo &TRI = TII->getRegisterInfo();
129 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
131 // Only one literal constant is allowed per instruction, so if src0 is a
132 // literal constant then we can't do any folding.
133 if (Src0->isImm() && TII->isLiteralConstant(*Src0))
137 // Literal constants and SGPRs can only be used in Src0, so if Src0 is an
138 // SGPR, we cannot commute the instruction, so we can't fold any literal
140 if (Src0->isReg() && !isVGPR(Src0, TRI, MRI))
145 unsigned Reg = Src0->getReg();
146 MachineInstr *Def = MRI.getUniqueVRegDef(Reg);
147 if (Def && Def->isMoveImmediate()) {
148 MachineOperand &MovSrc = Def->getOperand(1);
149 bool ConstantFolded = false;
151 if (MovSrc.isImm() && isUInt<32>(MovSrc.getImm())) {
152 Src0->ChangeToImmediate(MovSrc.getImm());
153 ConstantFolded = true;
154 } else if (MovSrc.isFPImm()) {
155 const APFloat &APF = MovSrc.getFPImm()->getValueAPF();
156 if (&APF.getSemantics() == &APFloat::IEEEsingle) {
157 MRI.removeRegOperandFromUseList(Src0);
158 Src0->ChangeToImmediate(APF.bitcastToAPInt().getZExtValue());
159 ConstantFolded = true;
162 if (ConstantFolded) {
163 for (MachineOperand &Use : MRI.use_operands(Reg))
164 Use.getParent()->dump();
165 if (MRI.use_empty(Reg))
166 Def->eraseFromParent();
167 ++NumLiteralConstantsFolded;
173 // We have failed to fold src0, so commute the instruction and try again.
174 if (TryToCommute && MI.isCommutable() && TII->commuteInstruction(&MI))
175 foldImmediates(MI, TII, MRI, false);
179 bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
180 MachineRegisterInfo &MRI = MF.getRegInfo();
181 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
182 MF.getTarget().getInstrInfo());
183 const SIRegisterInfo &TRI = TII->getRegisterInfo();
184 std::vector<unsigned> I1Defs;
186 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
189 MachineBasicBlock &MBB = *BI;
190 MachineBasicBlock::iterator I, Next;
191 for (I = MBB.begin(); I != MBB.end(); I = Next) {
193 MachineInstr &MI = *I;
195 if (!TII->hasVALU32BitEncoding(MI.getOpcode()))
198 if (!canShrink(MI, TII, TRI, MRI)) {
199 // Try commtuing the instruction and see if that enables us to shrink
201 if (!MI.isCommutable() || !TII->commuteInstruction(&MI) ||
202 !canShrink(MI, TII, TRI, MRI))
206 int Op32 = AMDGPU::getVOPe32(MI.getOpcode());
208 // Op32 could be -1 here if we started with an instruction that had a
209 // a 32-bit encoding and then commuted it to an instruction that did not.
213 if (TII->isVOPC(Op32)) {
214 unsigned DstReg = MI.getOperand(0).getReg();
215 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
216 // VOPC instructions can only write to the VCC register. We can't
217 // force them to use VCC here, because the register allocator
218 // has trouble with sequences like this, which cause the allocator
219 // to run out of registes if vreg0 and vreg1 belong to the VCCReg
223 // S_AND_B64 vreg0, vreg1
225 // So, instead of forcing the instruction to write to VCC, we provide a
226 // hint to the register allocator to use VCC and then we
227 // we will run this pass again after RA and shrink it if it outpus to
229 MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, AMDGPU::VCC);
232 if (DstReg != AMDGPU::VCC)
236 // We can shrink this instruction
237 DEBUG(dbgs() << "Shrinking "; MI.dump(); dbgs() << '\n';);
239 MachineInstrBuilder Inst32 =
240 BuildMI(MBB, I, MI.getDebugLoc(), TII->get(Op32));
243 Inst32.addOperand(MI.getOperand(0));
245 Inst32.addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::src0));
247 const MachineOperand *Src1 =
248 TII->getNamedOperand(MI, AMDGPU::OpName::src1);
250 Inst32.addOperand(*Src1);
252 ++NumInstructionsShrunk;
253 MI.eraseFromParent();
255 foldImmediates(*Inst32, TII, MRI);
256 DEBUG(dbgs() << "e32 MI = " << *Inst32 << '\n');