1 //===-- SIShrinkInstructions.cpp - Shrink Instructions --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 /// The pass tries to use the 32-bit encoding for instructions when possible.
9 //===----------------------------------------------------------------------===//
13 #include "SIInstrInfo.h"
14 #include "llvm/ADT/Statistic.h"
15 #include "llvm/CodeGen/MachineFunctionPass.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/IR/LLVMContext.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Target/TargetMachine.h"
23 #define DEBUG_TYPE "si-shrink-instructions"
25 STATISTIC(NumInstructionsShrunk,
26 "Number of 64-bit instruction reduced to 32-bit.");
29 void initializeSIShrinkInstructionsPass(PassRegistry&);
36 class SIShrinkInstructions : public MachineFunctionPass {
41 SIShrinkInstructions() : MachineFunctionPass(ID) {
44 virtual bool runOnMachineFunction(MachineFunction &MF) override;
46 virtual const char *getPassName() const override {
47 return "SI Shrink Instructions";
50 virtual void getAnalysisUsage(AnalysisUsage &AU) const override {
52 MachineFunctionPass::getAnalysisUsage(AU);
56 } // End anonymous namespace.
58 INITIALIZE_PASS_BEGIN(SIShrinkInstructions, DEBUG_TYPE,
59 "SI Lower il Copies", false, false)
60 INITIALIZE_PASS_END(SIShrinkInstructions, DEBUG_TYPE,
61 "SI Lower il Copies", false, false)
63 char SIShrinkInstructions::ID = 0;
65 FunctionPass *llvm::createSIShrinkInstructionsPass() {
66 return new SIShrinkInstructions();
69 static bool isVGPR(const MachineOperand *MO, const SIRegisterInfo &TRI,
70 const MachineRegisterInfo &MRI) {
74 if (TargetRegisterInfo::isVirtualRegister(MO->getReg()))
75 return TRI.hasVGPRs(MRI.getRegClass(MO->getReg()));
77 return TRI.hasVGPRs(TRI.getPhysRegClass(MO->getReg()));
80 static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII,
81 const SIRegisterInfo &TRI,
82 const MachineRegisterInfo &MRI) {
84 const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2);
85 // Can't shrink instruction with three operands.
89 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
90 const MachineOperand *Src1Mod =
91 TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers);
93 if (Src1 && (!isVGPR(Src1, TRI, MRI) || Src1Mod->getImm() != 0))
96 // We don't need to check src0, all input types are legal, so just make
97 // sure src0 isn't using any modifiers.
98 const MachineOperand *Src0Mod =
99 TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers);
100 if (Src0Mod && Src0Mod->getImm() != 0)
103 // Check output modifiers
104 const MachineOperand *Omod = TII->getNamedOperand(MI, AMDGPU::OpName::omod);
105 if (Omod && Omod->getImm() != 0)
108 const MachineOperand *Clamp = TII->getNamedOperand(MI, AMDGPU::OpName::clamp);
109 return !Clamp || Clamp->getImm() == 0;
112 bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
113 MachineRegisterInfo &MRI = MF.getRegInfo();
114 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
115 MF.getTarget().getInstrInfo());
116 const SIRegisterInfo &TRI = TII->getRegisterInfo();
117 std::vector<unsigned> I1Defs;
119 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
122 MachineBasicBlock &MBB = *BI;
123 MachineBasicBlock::iterator I, Next;
124 for (I = MBB.begin(); I != MBB.end(); I = Next) {
126 MachineInstr &MI = *I;
128 if (!TII->hasVALU32BitEncoding(MI.getOpcode()))
131 if (!canShrink(MI, TII, TRI, MRI)) {
132 // Try commtuing the instruction and see if that enables us to shrink
134 if (!MI.isCommutable() || !TII->commuteInstruction(&MI) ||
135 !canShrink(MI, TII, TRI, MRI))
139 int Op32 = AMDGPU::getVOPe32(MI.getOpcode());
141 // Op32 could be -1 here if we started with an instruction that had a
142 // a 32-bit encoding and then commuted it to an instruction that did not.
146 if (TII->isVOPC(Op32)) {
147 unsigned DstReg = MI.getOperand(0).getReg();
148 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
149 // VOPC instructions can only write to the VCC register. We can't
150 // force them to use VCC here, because the register allocator
151 // has trouble with sequences like this, which cause the allocator
152 // to run out of registes if vreg0 and vreg1 belong to the VCCReg
156 // S_AND_B64 vreg0, vreg1
158 // So, instead of forcing the instruction to write to VCC, we provide a
159 // hint to the register allocator to use VCC and then we
160 // we will run this pass again after RA and shrink it if it outpus to
162 MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, AMDGPU::VCC);
165 if (DstReg != AMDGPU::VCC)
169 // We can shrink this instruction
170 DEBUG(dbgs() << "Shrinking "; MI.dump(); dbgs() << "\n";);
172 MachineInstrBuilder MIB =
173 BuildMI(MBB, I, MI.getDebugLoc(), TII->get(Op32));
176 MIB.addOperand(MI.getOperand(0));
178 MIB.addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::src0));
180 const MachineOperand *Src1 =
181 TII->getNamedOperand(MI, AMDGPU::OpName::src1);
183 MIB.addOperand(*Src1);
185 for (const MachineOperand &MO : MI.implicit_operands())
188 DEBUG(dbgs() << "e32 MI = "; MI.dump(); dbgs() << "\n";);
189 ++NumInstructionsShrunk;
190 MI.eraseFromParent();