1 //===-- SIShrinkInstructions.cpp - Shrink Instructions --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 /// The pass tries to use the 32-bit encoding for instructions when possible.
9 //===----------------------------------------------------------------------===//
13 #include "AMDGPUSubtarget.h"
14 #include "SIInstrInfo.h"
15 #include "llvm/ADT/Statistic.h"
16 #include "llvm/CodeGen/MachineFunctionPass.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/IR/Constants.h"
20 #include "llvm/IR/LLVMContext.h"
21 #include "llvm/IR/Function.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Target/TargetMachine.h"
25 #define DEBUG_TYPE "si-shrink-instructions"
27 STATISTIC(NumInstructionsShrunk,
28 "Number of 64-bit instruction reduced to 32-bit.");
29 STATISTIC(NumLiteralConstantsFolded,
30 "Number of literal constants folded into 32-bit instructions.");
33 void initializeSIShrinkInstructionsPass(PassRegistry&);
40 class SIShrinkInstructions : public MachineFunctionPass {
45 SIShrinkInstructions() : MachineFunctionPass(ID) {
48 bool runOnMachineFunction(MachineFunction &MF) override;
50 const char *getPassName() const override {
51 return "SI Shrink Instructions";
54 void getAnalysisUsage(AnalysisUsage &AU) const override {
56 MachineFunctionPass::getAnalysisUsage(AU);
60 } // End anonymous namespace.
62 INITIALIZE_PASS_BEGIN(SIShrinkInstructions, DEBUG_TYPE,
63 "SI Lower il Copies", false, false)
64 INITIALIZE_PASS_END(SIShrinkInstructions, DEBUG_TYPE,
65 "SI Lower il Copies", false, false)
67 char SIShrinkInstructions::ID = 0;
69 FunctionPass *llvm::createSIShrinkInstructionsPass() {
70 return new SIShrinkInstructions();
73 static bool isVGPR(const MachineOperand *MO, const SIRegisterInfo &TRI,
74 const MachineRegisterInfo &MRI) {
78 if (TargetRegisterInfo::isVirtualRegister(MO->getReg()))
79 return TRI.hasVGPRs(MRI.getRegClass(MO->getReg()));
81 return TRI.hasVGPRs(TRI.getPhysRegClass(MO->getReg()));
84 static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII,
85 const SIRegisterInfo &TRI,
86 const MachineRegisterInfo &MRI) {
88 const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2);
89 // Can't shrink instruction with three operands.
93 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
94 const MachineOperand *Src1Mod =
95 TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers);
97 if (Src1 && (!isVGPR(Src1, TRI, MRI) || (Src1Mod && Src1Mod->getImm() != 0)))
100 // We don't need to check src0, all input types are legal, so just make sure
101 // src0 isn't using any modifiers.
102 if (TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers))
105 // Check output modifiers
106 if (TII->hasModifiersSet(MI, AMDGPU::OpName::omod))
109 if (TII->hasModifiersSet(MI, AMDGPU::OpName::clamp))
115 /// \brief This function checks \p MI for operands defined by a move immediate
116 /// instruction and then folds the literal constant into the instruction if it
117 /// can. This function assumes that \p MI is a VOP1, VOP2, or VOPC instruction
118 /// and will only fold literal constants if we are still in SSA.
119 static void foldImmediates(MachineInstr &MI, const SIInstrInfo *TII,
120 MachineRegisterInfo &MRI, bool TryToCommute = true) {
125 assert(TII->isVOP1(MI.getOpcode()) || TII->isVOP2(MI.getOpcode()) ||
126 TII->isVOPC(MI.getOpcode()));
128 const SIRegisterInfo &TRI = TII->getRegisterInfo();
129 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
131 // Only one literal constant is allowed per instruction, so if src0 is a
132 // literal constant then we can't do any folding.
133 if ((Src0->isImm() || Src0->isFPImm()) && TII->isLiteralConstant(*Src0))
137 // Literal constants and SGPRs can only be used in Src0, so if Src0 is an
138 // SGPR, we cannot commute the instruction, so we can't fold any literal
140 if (Src0->isReg() && !isVGPR(Src0, TRI, MRI))
145 unsigned Reg = Src0->getReg();
146 MachineInstr *Def = MRI.getUniqueVRegDef(Reg);
147 if (Def && Def->isMoveImmediate()) {
148 MachineOperand &MovSrc = Def->getOperand(1);
149 bool ConstantFolded = false;
151 if (MovSrc.isImm() && isUInt<32>(MovSrc.getImm())) {
152 Src0->ChangeToImmediate(MovSrc.getImm());
153 ConstantFolded = true;
154 } else if (MovSrc.isFPImm()) {
155 const ConstantFP *CFP = MovSrc.getFPImm();
156 if (&CFP->getValueAPF().getSemantics() == &APFloat::IEEEsingle) {
157 Src0->ChangeToFPImmediate(CFP);
158 ConstantFolded = true;
161 if (ConstantFolded) {
162 if (MRI.use_empty(Reg))
163 Def->eraseFromParent();
164 ++NumLiteralConstantsFolded;
170 // We have failed to fold src0, so commute the instruction and try again.
171 if (TryToCommute && MI.isCommutable() && TII->commuteInstruction(&MI))
172 foldImmediates(MI, TII, MRI, false);
176 bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
177 MachineRegisterInfo &MRI = MF.getRegInfo();
178 const SIInstrInfo *TII =
179 static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());
180 const SIRegisterInfo &TRI = TII->getRegisterInfo();
181 std::vector<unsigned> I1Defs;
183 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
186 MachineBasicBlock &MBB = *BI;
187 MachineBasicBlock::iterator I, Next;
188 for (I = MBB.begin(); I != MBB.end(); I = Next) {
190 MachineInstr &MI = *I;
192 // Try to use S_MOVK_I32, which will save 4 bytes for small immediates.
193 if (MI.getOpcode() == AMDGPU::S_MOV_B32) {
194 const MachineOperand &Src = MI.getOperand(1);
196 // TODO: Handle FPImm?
198 if (isInt<16>(Src.getImm()) && !TII->isInlineConstant(Src)) {
199 MI.setDesc(TII->get(AMDGPU::S_MOVK_I32));
205 if (!TII->hasVALU32BitEncoding(MI.getOpcode()))
208 if (!canShrink(MI, TII, TRI, MRI)) {
209 // Try commuting the instruction and see if that enables us to shrink
211 if (!MI.isCommutable() || !TII->commuteInstruction(&MI) ||
212 !canShrink(MI, TII, TRI, MRI))
216 int Op32 = AMDGPU::getVOPe32(MI.getOpcode());
218 // Op32 could be -1 here if we started with an instruction that had a
219 // a 32-bit encoding and then commuted it to an instruction that did not.
223 if (TII->isVOPC(Op32)) {
224 unsigned DstReg = MI.getOperand(0).getReg();
225 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
226 // VOPC instructions can only write to the VCC register. We can't
227 // force them to use VCC here, because the register allocator has
228 // trouble with sequences like this, which cause the allocator to run
229 // out of registers if vreg0 and vreg1 belong to the VCCReg register
233 // S_AND_B64 vreg0, vreg1
235 // So, instead of forcing the instruction to write to VCC, we provide
236 // a hint to the register allocator to use VCC and then we we will run
237 // this pass again after RA and shrink it if it outputs to VCC.
238 MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, AMDGPU::VCC);
241 if (DstReg != AMDGPU::VCC)
245 // We can shrink this instruction
246 DEBUG(dbgs() << "Shrinking "; MI.dump(); dbgs() << '\n';);
248 MachineInstrBuilder Inst32 =
249 BuildMI(MBB, I, MI.getDebugLoc(), TII->get(Op32));
252 Inst32.addOperand(MI.getOperand(0));
254 Inst32.addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::src0));
256 const MachineOperand *Src1 =
257 TII->getNamedOperand(MI, AMDGPU::OpName::src1);
259 Inst32.addOperand(*Src1);
261 ++NumInstructionsShrunk;
262 MI.eraseFromParent();
264 foldImmediates(*Inst32, TII, MRI);
265 DEBUG(dbgs() << "e32 MI = " << *Inst32 << '\n');