1 //===-- VIInstructions.td - VI Instruction Defintions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // Instruction definitions for VI and newer.
10 //===----------------------------------------------------------------------===//
12 let SubtargetPredicate = isVI in {
14 def V_LDEXP_F32 : VOP3InstVI <0x288, "v_ldexp_f32", VOP_F32_F32_I32,
17 def V_BFM_B32 : VOP3InstVI <0x293, "v_bfm_b32", VOP_I32_I32_I32, AMDGPUbfm>;
18 def V_BCNT_U32_B32 : VOP3InstVI <0x28b, "v_bcnt_u32_b32", VOP_I32_I32_I32>;
19 def V_MBCNT_LO_U32_B32 : VOP3InstVI <0x28c, "v_mbcnt_lo_u32_b32",
22 def V_MBCNT_HI_U32_B32 : VOP3InstVI <0x28d, "v_mbcnt_hi_u32_b32",
26 def V_CVT_PKRTZ_F16_F32 : VOP3InstVI <0x296, "v_cvt_pkrtz_f16_f32",
27 VOP_I32_F32_F32, int_SI_packf16
30 defm BUFFER_LOAD_DWORD_VI : MUBUF_Load_Helper_vi <
31 0x14, "buffer_load_dword", VGPR_32, i32, global_load
34 defm BUFFER_LOAD_FORMAT_XYZW_VI : MUBUF_Load_Helper_vi <
35 0x03, "buffer_load_format_xyzw", VReg_128
38 } // End SubtargetPredicate = isVI
40 //===----------------------------------------------------------------------===//
42 //===----------------------------------------------------------------------===//
44 let Predicates = [isVI] in {
48 (V_MBCNT_HI_U32_B32 0xffffffff,
49 (V_MBCNT_LO_U32_B32 0xffffffff, 0))
52 //===----------------------------------------------------------------------===//
54 //===----------------------------------------------------------------------===//
56 // 1. Offset as 8bit DWORD immediate
58 (SIload_constant v4i32:$sbase, IMM20bit:$offset),
59 (S_BUFFER_LOAD_DWORD_IMM $sbase, (as_i32imm $offset))
62 //===----------------------------------------------------------------------===//
64 //===----------------------------------------------------------------------===//
66 // Offset in an 32Bit VGPR
68 (SIload_constant v4i32:$sbase, i32:$voff),
69 (BUFFER_LOAD_DWORD_VI_OFFEN $sbase, $voff, 0, 0, 0, 0, 0)
72 // Offset in an 32Bit VGPR
74 (SIload_constant v4i32:$sbase, i32:$voff),
75 (BUFFER_LOAD_DWORD_VI_OFFEN $sbase, $voff, 0, 0, 0, 0, 0)
78 /* int_SI_vs_load_input */
80 (SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr),
81 (BUFFER_LOAD_FORMAT_XYZW_VI_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0)
84 defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_VI_OFFSET,
85 BUFFER_LOAD_DWORD_VI_OFFEN,
86 BUFFER_LOAD_DWORD_VI_IDXEN,
87 BUFFER_LOAD_DWORD_VI_BOTHEN>;
89 } // End Predicates = [isVI]