1 Target Independent Opportunities:
3 //===---------------------------------------------------------------------===//
5 We should make the following changes to clean up MachineInstr:
7 1. Add an Opcode field to TargetInstrDescriptor, so you can tell the opcode of
8 an instruction with just a TargetInstrDescriptor*.
9 2. Remove the Opcode field from MachineInstr, replacing it with a
10 TargetInstrDescriptor*.
11 3. Getting information about a machine instr then becomes:
12 MI->getInfo()->isTwoAddress()
14 const TargetInstrInfo &TII = ...
15 TII.isTwoAddrInstr(MI->getOpcode())
17 //===---------------------------------------------------------------------===//
19 FreeBench/mason contains code like this:
21 static p_type m0u(p_type p) {
22 int m[]={0, 8, 1, 2, 16, 5, 13, 7, 14, 9, 3, 4, 11, 12, 15, 10, 17, 6};
30 We currently compile this into a memcpy from a static array into 'm', then
31 a bunch of loads from m. It would be better to avoid the memcpy and just do
32 loads from the static array.
34 //===---------------------------------------------------------------------===//
36 Make the PPC branch selector target independant
38 //===---------------------------------------------------------------------===//
40 Get the C front-end to expand hypot(x,y) -> llvm.sqrt(x*x+y*y) when errno and
41 precision don't matter (ffastmath). Misc/mandel will like this. :)
43 //===---------------------------------------------------------------------===//
45 Solve this DAG isel folding deficiency:
63 The problem is the store's chain operand is not the load X but rather
64 a TokenFactor of the load X and load Y, which prevents the folding.
66 There are two ways to fix this:
68 1. The dag combiner can start using alias analysis to realize that y/x
69 don't alias, making the store to X not dependent on the load from Y.
70 2. The generated isel could be made smarter in the case it can't
71 disambiguate the pointers.
73 Number 1 is the preferred solution.
75 This has been "fixed" by a TableGen hack. But that is a short term workaround
76 which will be removed once the proper fix is made.
78 //===---------------------------------------------------------------------===//
80 On targets with expensive 64-bit multiply, we could LSR this:
87 for (i = ...; ++i, tmp+=tmp)
90 This would be a win on ppc32, but not x86 or ppc64.
92 //===---------------------------------------------------------------------===//
94 Shrink: (setlt (loadi32 P), 0) -> (setlt (loadi8 Phi), 0)
96 //===---------------------------------------------------------------------===//
98 Reassociate should turn: X*X*X*X -> t=(X*X) (t*t) to eliminate a multiply.
100 //===---------------------------------------------------------------------===//
102 Interesting? testcase for add/shift/mul reassoc:
104 int bar(int x, int y) {
105 return x*x*x+y+x*x*x*x*x*y*y*y*y;
107 int foo(int z, int n) {
108 return bar(z, n) + bar(2*z, 2*n);
111 //===---------------------------------------------------------------------===//
113 These two functions should generate the same code on big-endian systems:
115 int g(int *j,int *l) { return memcmp(j,l,4); }
116 int h(int *j, int *l) { return *j - *l; }
118 this could be done in SelectionDAGISel.cpp, along with other special cases,
121 //===---------------------------------------------------------------------===//
124 int rot(unsigned char b) { int a = ((b>>1) ^ (b<<7)) & 0xff; return a; }
126 Can be improved in two ways:
128 1. The instcombiner should eliminate the type conversions.
129 2. The X86 backend should turn this into a rotate by one bit.
131 //===---------------------------------------------------------------------===//
133 Add LSR exit value substitution. It'll probably be a win for Ackermann, etc.
135 //===---------------------------------------------------------------------===//
137 It would be nice to revert this patch:
138 http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20060213/031986.html
140 And teach the dag combiner enough to simplify the code expanded before
141 legalize. It seems plausible that this knowledge would let it simplify other
144 //===---------------------------------------------------------------------===//
146 For packed types, TargetData.cpp::getTypeInfo() returns alignment that is equal
147 to the type size. It works but can be overly conservative as the alignment of
148 specific packed types are target dependent.
150 //===---------------------------------------------------------------------===//
152 We should add 'unaligned load/store' nodes, and produce them from code like
155 v4sf example(float *P) {
156 return (v4sf){P[0], P[1], P[2], P[3] };
159 //===---------------------------------------------------------------------===//
161 We should constant fold packed type casts at the LLVM level, regardless of the
162 cast. Currently we cannot fold some casts because we don't have TargetData
163 information in the constant folder, so we don't know the endianness of the
166 //===---------------------------------------------------------------------===//
168 Add support for conditional increments, and other related patterns. Instead
173 je LBB16_2 #cond_next
184 //===---------------------------------------------------------------------===//
186 Combine: a = sin(x), b = cos(x) into a,b = sincos(x).
188 Expand these to calls of sin/cos and stores:
189 double sincos(double x, double *sin, double *cos);
190 float sincosf(float x, float *sin, float *cos);
191 long double sincosl(long double x, long double *sin, long double *cos);
193 Doing so could allow SROA of the destination pointers. See also:
194 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=17687
196 //===---------------------------------------------------------------------===//
198 Scalar Repl cannot currently promote this testcase to 'ret long cst':
200 %struct.X = type { int, int }
201 %struct.Y = type { %struct.X }
203 %retval = alloca %struct.Y, align 8 ; <%struct.Y*> [#uses=3]
204 %tmp12 = getelementptr %struct.Y* %retval, int 0, uint 0, uint 0
205 store int 0, int* %tmp12
206 %tmp15 = getelementptr %struct.Y* %retval, int 0, uint 0, uint 1
207 store int 1, int* %tmp15
208 %retval = cast %struct.Y* %retval to ulong*
209 %retval = load ulong* %retval ; <ulong> [#uses=1]
213 it should be extended to do so.
215 //===---------------------------------------------------------------------===//
217 Turn this into a single byte store with no load (the other 3 bytes are
220 void %test(uint* %P) {
222 %tmp14 = or uint %tmp, 3305111552
223 %tmp15 = and uint %tmp14, 3321888767
224 store uint %tmp15, uint* %P
228 //===---------------------------------------------------------------------===//
230 dag/inst combine "clz(x)>>5 -> x==0" for 32-bit x.
236 int t = __builtin_clz(x);
246 //===---------------------------------------------------------------------===//
248 Legalize should lower ctlz like this:
249 ctlz(x) = popcnt((x-1) & ~x)
251 on targets that have popcnt but not ctlz. itanium, what else?
253 //===---------------------------------------------------------------------===//
255 quantum_sigma_x in 462.libquantum contains the following loop:
257 for(i=0; i<reg->size; i++)
259 /* Flip the target bit of each basis state */
260 reg->node[i].state ^= ((MAX_UNSIGNED) 1 << target);
263 Where MAX_UNSIGNED/state is a 64-bit int. On a 32-bit platform it would be just
264 so cool to turn it into something like:
266 long long Res = ((MAX_UNSIGNED) 1 << target);
268 for(i=0; i<reg->size; i++)
269 reg->node[i].state ^= Res & 0xFFFFFFFFULL;
271 for(i=0; i<reg->size; i++)
272 reg->node[i].state ^= Res & 0xFFFFFFFF00000000ULL
275 ... which would only do one 32-bit XOR per loop iteration instead of two.
277 It would also be nice to recognize the reg->size doesn't alias reg->node[i], but
280 //===---------------------------------------------------------------------===//
282 This isn't recognized as bswap by instcombine:
284 unsigned int swap_32(unsigned int v) {
285 v = ((v & 0x00ff00ffU) << 8) | ((v & 0xff00ff00U) >> 8);
286 v = ((v & 0x0000ffffU) << 16) | ((v & 0xffff0000U) >> 16);
290 //===---------------------------------------------------------------------===//
292 These should turn into single 16-bit (unaligned?) loads on little/big endian
295 unsigned short read_16_le(const unsigned char *adr) {
296 return adr[0] | (adr[1] << 8);
298 unsigned short read_16_be(const unsigned char *adr) {
299 return (adr[0] << 8) | adr[1];
302 //===---------------------------------------------------------------------===//