1 //===-- SchedInfo.cpp - Generic code to support target schedulers ----------==//
3 // This file implements the generic part of a Scheduler description for a
4 // target. This functionality is defined in the llvm/Target/SchedInfo.h file.
6 //===----------------------------------------------------------------------===//
8 #include "llvm/Target/SchedInfo.h"
10 // External object describing the machine instructions
11 // Initialized only when the TargetMachine class is created
12 // and reset when that class is destroyed.
14 const MachineInstrDescriptor* TargetInstrDescriptors = 0;
16 resourceId_t MachineResource::nextId = 0;
18 // Check if fromRVec and toRVec have *any* common entries.
19 // Assume the vectors are sorted in increasing order.
20 // Algorithm copied from function set_intersection() for sorted ranges
23 inline static bool RUConflict(const vector<resourceId_t>& fromRVec,
24 const vector<resourceId_t>& toRVec) {
26 unsigned fN = fromRVec.size(), tN = toRVec.size();
27 unsigned fi = 0, ti = 0;
29 while (fi < fN && ti < tN) {
30 if (fromRVec[fi] < toRVec[ti])
32 else if (toRVec[ti] < fromRVec[fi])
41 static cycles_t ComputeMinGap(const InstrRUsage &fromRU,
42 const InstrRUsage &toRU) {
45 if (fromRU.numBubbles > 0)
46 minGap = fromRU.numBubbles;
48 if (minGap < fromRU.numCycles) {
49 // only need to check from cycle `minGap' onwards
50 for (cycles_t gap=minGap; gap <= fromRU.numCycles-1; gap++) {
51 // check if instr. #2 can start executing `gap' cycles after #1
52 // by checking for resource conflicts in each overlapping cycle
53 cycles_t numOverlap = min(fromRU.numCycles - gap, toRU.numCycles);
54 for (cycles_t c = 0; c <= numOverlap-1; c++)
55 if (RUConflict(fromRU.resourcesByCycle[gap + c],
56 toRU.resourcesByCycle[c])) {
57 // conflict found so minGap must be more than `gap'
68 //---------------------------------------------------------------------------
69 // class MachineSchedInfo
70 // Interface to machine description for instruction scheduling
71 //---------------------------------------------------------------------------
73 MachineSchedInfo::MachineSchedInfo(int NumSchedClasses,
74 const MachineInstrInfo* Mii,
75 const InstrClassRUsage* ClassRUsages,
76 const InstrRUsageDelta* UsageDeltas,
77 const InstrIssueDelta* IssueDeltas,
78 unsigned int NumUsageDeltas,
79 unsigned int NumIssueDeltas)
80 : numSchedClasses(NumSchedClasses), mii(Mii),
81 classRUsages(ClassRUsages), usageDeltas(UsageDeltas),
82 issueDeltas(IssueDeltas), numUsageDeltas(NumUsageDeltas),
83 numIssueDeltas(NumIssueDeltas) {
86 void MachineSchedInfo::initializeResources() {
87 assert(MAX_NUM_SLOTS >= (int)getMaxNumIssueTotal()
88 && "Insufficient slots for static data! Increase MAX_NUM_SLOTS");
90 // First, compute common resource usage info for each class because
91 // most instructions will probably behave the same as their class.
92 // Cannot allocate a vector of InstrRUsage so new each one.
94 vector<InstrRUsage> instrRUForClasses;
95 instrRUForClasses.resize(numSchedClasses);
96 for (InstrSchedClass sc = 0; sc < numSchedClasses; sc++) {
97 // instrRUForClasses.push_back(new InstrRUsage);
98 instrRUForClasses[sc].setMaxSlots(getMaxNumIssueTotal());
99 instrRUForClasses[sc] = classRUsages[sc];
102 computeInstrResources(instrRUForClasses);
103 computeIssueGaps(instrRUForClasses);
107 void MachineSchedInfo::computeInstrResources(
108 const vector<InstrRUsage> &instrRUForClasses) {
109 int numOpCodes = mii->getNumRealOpCodes();
110 instrRUsages.resize(numOpCodes);
112 // First get the resource usage information from the class resource usages.
113 for (MachineOpCode op = 0; op < numOpCodes; ++op) {
114 InstrSchedClass sc = getSchedClass(op);
115 assert(sc >= 0 && sc < numSchedClasses);
116 instrRUsages[op] = instrRUForClasses[sc];
119 // Now, modify the resource usages as specified in the deltas.
120 for (unsigned i = 0; i < numUsageDeltas; ++i) {
121 MachineOpCode op = usageDeltas[i].opCode;
122 assert(op < numOpCodes);
123 instrRUsages[op].addUsageDelta(usageDeltas[i]);
126 // Then modify the issue restrictions as specified in the deltas.
127 for (unsigned i = 0; i < numIssueDeltas; ++i) {
128 MachineOpCode op = issueDeltas[i].opCode;
129 assert(op < numOpCodes);
130 instrRUsages[issueDeltas[i].opCode].addIssueDelta(issueDeltas[i]);
135 void MachineSchedInfo::computeIssueGaps(
136 const vector<InstrRUsage> &instrRUForClasses) {
137 int numOpCodes = mii->getNumRealOpCodes();
138 instrRUsages.resize(numOpCodes);
140 assert(numOpCodes < (1 << MAX_OPCODE_SIZE) - 1
141 && "numOpCodes invalid for implementation of class OpCodePair!");
143 // First, compute issue gaps between pairs of classes based on common
144 // resources usages for each class, because most instruction pairs will
145 // usually behave the same as their class.
147 int classPairGaps[numSchedClasses][numSchedClasses];
148 for (InstrSchedClass fromSC=0; fromSC < numSchedClasses; fromSC++)
149 for (InstrSchedClass toSC=0; toSC < numSchedClasses; toSC++) {
150 int classPairGap = ComputeMinGap(instrRUForClasses[fromSC],
151 instrRUForClasses[toSC]);
152 classPairGaps[fromSC][toSC] = classPairGap;
155 // Now, for each pair of instructions, use the class pair gap if both
156 // instructions have identical resource usage as their respective classes.
157 // If not, recompute the gap for the pair from scratch.
159 longestIssueConflict = 0;
161 for (MachineOpCode fromOp=0; fromOp < numOpCodes; fromOp++)
162 for (MachineOpCode toOp=0; toOp < numOpCodes; toOp++) {
164 (instrRUsages[fromOp].sameAsClass && instrRUsages[toOp].sameAsClass)
165 ? classPairGaps[getSchedClass(fromOp)][getSchedClass(toOp)]
166 : ComputeMinGap(instrRUsages[fromOp], instrRUsages[toOp]);
168 if (instrPairGap > 0) {
169 issueGaps[OpCodePair(fromOp,toOp)] = instrPairGap;
170 conflictLists[fromOp].push_back(toOp);
171 longestIssueConflict = max(longestIssueConflict, instrPairGap);