1 //===-- SparcAsmParser.cpp - Parse Sparc assembly to MCInst instructions --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/SparcMCTargetDesc.h"
11 #include "MCTargetDesc/SparcMCExpr.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCObjectFileInfo.h"
16 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/MC/MCSubtargetInfo.h"
19 #include "llvm/MC/MCSymbol.h"
20 #include "llvm/MC/MCTargetAsmParser.h"
21 #include "llvm/Support/TargetRegistry.h"
25 // The generated AsmMatcher SparcGenAsmMatcher uses "Sparc" as the target
26 // namespace. But SPARC backend uses "SP" as its namespace.
35 class SparcAsmParser : public MCTargetAsmParser {
40 /// @name Auto-generated Match Functions
43 #define GET_ASSEMBLER_HEADER
44 #include "SparcGenAsmMatcher.inc"
48 // public interface of the MCTargetAsmParser.
49 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
50 OperandVector &Operands, MCStreamer &Out,
52 bool MatchingInlineAsm) override;
53 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
54 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
55 SMLoc NameLoc, OperandVector &Operands) override;
56 bool ParseDirective(AsmToken DirectiveID) override;
58 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
59 unsigned Kind) override;
61 // Custom parse functions for Sparc specific operands.
62 OperandMatchResultTy parseMEMOperand(OperandVector &Operands);
64 OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Name);
67 parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Operand,
70 OperandMatchResultTy parseBranchModifiers(OperandVector &Operands);
72 // returns true if Tok is matched to a register and returns register in RegNo.
73 bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
76 bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc);
77 bool parseDirectiveWord(unsigned Size, SMLoc L);
79 bool is64Bit() const {
80 return STI.getTargetTriple().getArch() == Triple::sparcv9;
83 void expandSET(MCInst &Inst, SMLoc IDLoc,
84 SmallVectorImpl<MCInst> &Instructions);
87 SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
88 const MCInstrInfo &MII,
89 const MCTargetOptions &Options)
90 : MCTargetAsmParser(Options), STI(sti), Parser(parser) {
91 // Initialize the set of available features.
92 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
97 static unsigned IntRegs[32] = {
98 Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,
99 Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7,
100 Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3,
101 Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7,
102 Sparc::L0, Sparc::L1, Sparc::L2, Sparc::L3,
103 Sparc::L4, Sparc::L5, Sparc::L6, Sparc::L7,
104 Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3,
105 Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
107 static unsigned FloatRegs[32] = {
108 Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3,
109 Sparc::F4, Sparc::F5, Sparc::F6, Sparc::F7,
110 Sparc::F8, Sparc::F9, Sparc::F10, Sparc::F11,
111 Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15,
112 Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19,
113 Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23,
114 Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27,
115 Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 };
117 static unsigned DoubleRegs[32] = {
118 Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3,
119 Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
120 Sparc::D8, Sparc::D7, Sparc::D8, Sparc::D9,
121 Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
122 Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
123 Sparc::D20, Sparc::D21, Sparc::D22, Sparc::D23,
124 Sparc::D24, Sparc::D25, Sparc::D26, Sparc::D27,
125 Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
127 static unsigned QuadFPRegs[32] = {
128 Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3,
129 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
130 Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11,
131 Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
133 static unsigned ASRRegs[32] = {
134 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
135 SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
136 SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
137 SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
138 SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
139 SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
140 SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
141 SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
143 static unsigned IntPairRegs[] = {
144 Sparc::G0_G1, Sparc::G2_G3, Sparc::G4_G5, Sparc::G6_G7,
145 Sparc::O0_O1, Sparc::O2_O3, Sparc::O4_O5, Sparc::O6_O7,
146 Sparc::L0_L1, Sparc::L2_L3, Sparc::L4_L5, Sparc::L6_L7,
147 Sparc::I0_I1, Sparc::I2_I3, Sparc::I4_I5, Sparc::I6_I7};
149 /// SparcOperand - Instances of this class represent a parsed Sparc machine
151 class SparcOperand : public MCParsedAsmOperand {
172 SMLoc StartLoc, EndLoc;
201 SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
203 bool isToken() const override { return Kind == k_Token; }
204 bool isReg() const override { return Kind == k_Register; }
205 bool isImm() const override { return Kind == k_Immediate; }
206 bool isMem() const override { return isMEMrr() || isMEMri(); }
207 bool isMEMrr() const { return Kind == k_MemoryReg; }
208 bool isMEMri() const { return Kind == k_MemoryImm; }
210 bool isIntReg() const {
211 return (Kind == k_Register && Reg.Kind == rk_IntReg);
214 bool isFloatReg() const {
215 return (Kind == k_Register && Reg.Kind == rk_FloatReg);
218 bool isFloatOrDoubleReg() const {
219 return (Kind == k_Register && (Reg.Kind == rk_FloatReg
220 || Reg.Kind == rk_DoubleReg));
224 StringRef getToken() const {
225 assert(Kind == k_Token && "Invalid access!");
226 return StringRef(Tok.Data, Tok.Length);
229 unsigned getReg() const override {
230 assert((Kind == k_Register) && "Invalid access!");
234 const MCExpr *getImm() const {
235 assert((Kind == k_Immediate) && "Invalid access!");
239 unsigned getMemBase() const {
240 assert((Kind == k_MemoryReg || Kind == k_MemoryImm) && "Invalid access!");
244 unsigned getMemOffsetReg() const {
245 assert((Kind == k_MemoryReg) && "Invalid access!");
246 return Mem.OffsetReg;
249 const MCExpr *getMemOff() const {
250 assert((Kind == k_MemoryImm) && "Invalid access!");
254 /// getStartLoc - Get the location of the first token of this operand.
255 SMLoc getStartLoc() const override {
258 /// getEndLoc - Get the location of the last token of this operand.
259 SMLoc getEndLoc() const override {
263 void print(raw_ostream &OS) const override {
265 case k_Token: OS << "Token: " << getToken() << "\n"; break;
266 case k_Register: OS << "Reg: #" << getReg() << "\n"; break;
267 case k_Immediate: OS << "Imm: " << getImm() << "\n"; break;
268 case k_MemoryReg: OS << "Mem: " << getMemBase() << "+"
269 << getMemOffsetReg() << "\n"; break;
270 case k_MemoryImm: assert(getMemOff() != nullptr);
271 OS << "Mem: " << getMemBase()
272 << "+" << *getMemOff()
277 void addRegOperands(MCInst &Inst, unsigned N) const {
278 assert(N == 1 && "Invalid number of operands!");
279 Inst.addOperand(MCOperand::createReg(getReg()));
282 void addImmOperands(MCInst &Inst, unsigned N) const {
283 assert(N == 1 && "Invalid number of operands!");
284 const MCExpr *Expr = getImm();
288 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
289 // Add as immediate when possible. Null MCExpr = 0.
291 Inst.addOperand(MCOperand::createImm(0));
292 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
293 Inst.addOperand(MCOperand::createImm(CE->getValue()));
295 Inst.addOperand(MCOperand::createExpr(Expr));
298 void addMEMrrOperands(MCInst &Inst, unsigned N) const {
299 assert(N == 2 && "Invalid number of operands!");
301 Inst.addOperand(MCOperand::createReg(getMemBase()));
303 assert(getMemOffsetReg() != 0 && "Invalid offset");
304 Inst.addOperand(MCOperand::createReg(getMemOffsetReg()));
307 void addMEMriOperands(MCInst &Inst, unsigned N) const {
308 assert(N == 2 && "Invalid number of operands!");
310 Inst.addOperand(MCOperand::createReg(getMemBase()));
312 const MCExpr *Expr = getMemOff();
316 static std::unique_ptr<SparcOperand> CreateToken(StringRef Str, SMLoc S) {
317 auto Op = make_unique<SparcOperand>(k_Token);
318 Op->Tok.Data = Str.data();
319 Op->Tok.Length = Str.size();
325 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind,
327 auto Op = make_unique<SparcOperand>(k_Register);
328 Op->Reg.RegNum = RegNum;
329 Op->Reg.Kind = (SparcOperand::RegisterKind)Kind;
335 static std::unique_ptr<SparcOperand> CreateImm(const MCExpr *Val, SMLoc S,
337 auto Op = make_unique<SparcOperand>(k_Immediate);
344 static bool MorphToIntPairReg(SparcOperand &Op) {
345 unsigned Reg = Op.getReg();
346 assert(Op.Reg.Kind == rk_IntReg);
347 unsigned regIdx = 32;
348 if (Reg >= Sparc::G0 && Reg <= Sparc::G7)
349 regIdx = Reg - Sparc::G0;
350 else if (Reg >= Sparc::O0 && Reg <= Sparc::O7)
351 regIdx = Reg - Sparc::O0 + 8;
352 else if (Reg >= Sparc::L0 && Reg <= Sparc::L7)
353 regIdx = Reg - Sparc::L0 + 16;
354 else if (Reg >= Sparc::I0 && Reg <= Sparc::I7)
355 regIdx = Reg - Sparc::I0 + 24;
356 if (regIdx % 2 || regIdx > 31)
358 Op.Reg.RegNum = IntPairRegs[regIdx / 2];
359 Op.Reg.Kind = rk_IntPairReg;
363 static bool MorphToDoubleReg(SparcOperand &Op) {
364 unsigned Reg = Op.getReg();
365 assert(Op.Reg.Kind == rk_FloatReg);
366 unsigned regIdx = Reg - Sparc::F0;
367 if (regIdx % 2 || regIdx > 31)
369 Op.Reg.RegNum = DoubleRegs[regIdx / 2];
370 Op.Reg.Kind = rk_DoubleReg;
374 static bool MorphToQuadReg(SparcOperand &Op) {
375 unsigned Reg = Op.getReg();
377 switch (Op.Reg.Kind) {
378 default: llvm_unreachable("Unexpected register kind!");
380 regIdx = Reg - Sparc::F0;
381 if (regIdx % 4 || regIdx > 31)
383 Reg = QuadFPRegs[regIdx / 4];
386 regIdx = Reg - Sparc::D0;
387 if (regIdx % 2 || regIdx > 31)
389 Reg = QuadFPRegs[regIdx / 2];
393 Op.Reg.Kind = rk_QuadReg;
397 static std::unique_ptr<SparcOperand>
398 MorphToMEMrr(unsigned Base, std::unique_ptr<SparcOperand> Op) {
399 unsigned offsetReg = Op->getReg();
400 Op->Kind = k_MemoryReg;
402 Op->Mem.OffsetReg = offsetReg;
403 Op->Mem.Off = nullptr;
407 static std::unique_ptr<SparcOperand>
408 CreateMEMr(unsigned Base, SMLoc S, SMLoc E) {
409 auto Op = make_unique<SparcOperand>(k_MemoryReg);
411 Op->Mem.OffsetReg = Sparc::G0; // always 0
412 Op->Mem.Off = nullptr;
418 static std::unique_ptr<SparcOperand>
419 MorphToMEMri(unsigned Base, std::unique_ptr<SparcOperand> Op) {
420 const MCExpr *Imm = Op->getImm();
421 Op->Kind = k_MemoryImm;
423 Op->Mem.OffsetReg = 0;
431 void SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc,
432 SmallVectorImpl<MCInst> &Instructions) {
433 MCOperand MCRegOp = Inst.getOperand(0);
434 MCOperand MCValOp = Inst.getOperand(1);
435 assert(MCRegOp.isReg());
436 assert(MCValOp.isImm() || MCValOp.isExpr());
438 // the imm operand can be either an expression or an immediate.
439 bool IsImm = Inst.getOperand(1).isImm();
440 uint64_t ImmValue = IsImm ? MCValOp.getImm() : 0;
441 const MCExpr *ValExpr;
443 ValExpr = MCConstantExpr::create(ImmValue, getContext());
445 ValExpr = MCValOp.getExpr();
447 MCOperand PrevReg = MCOperand::createReg(Sparc::G0);
449 if (!IsImm || (ImmValue & ~0x1fff)) {
452 SparcMCExpr::create(SparcMCExpr::VK_Sparc_HI, ValExpr, getContext());
453 TmpInst.setLoc(IDLoc);
454 TmpInst.setOpcode(SP::SETHIi);
455 TmpInst.addOperand(MCRegOp);
456 TmpInst.addOperand(MCOperand::createExpr(Expr));
457 Instructions.push_back(TmpInst);
461 if (!IsImm || ((ImmValue & 0x1fff) != 0 || ImmValue == 0)) {
464 SparcMCExpr::create(SparcMCExpr::VK_Sparc_LO, ValExpr, getContext());
465 TmpInst.setLoc(IDLoc);
466 TmpInst.setOpcode(SP::ORri);
467 TmpInst.addOperand(MCRegOp);
468 TmpInst.addOperand(PrevReg);
469 TmpInst.addOperand(MCOperand::createExpr(Expr));
470 Instructions.push_back(TmpInst);
474 bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
475 OperandVector &Operands,
478 bool MatchingInlineAsm) {
480 SmallVector<MCInst, 8> Instructions;
481 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
483 switch (MatchResult) {
484 case Match_Success: {
485 switch (Inst.getOpcode()) {
488 Instructions.push_back(Inst);
491 expandSET(Inst, IDLoc, Instructions);
495 for (const MCInst &I : Instructions) {
496 Out.EmitInstruction(I, STI);
501 case Match_MissingFeature:
503 "instruction requires a CPU feature not currently enabled");
505 case Match_InvalidOperand: {
506 SMLoc ErrorLoc = IDLoc;
507 if (ErrorInfo != ~0ULL) {
508 if (ErrorInfo >= Operands.size())
509 return Error(IDLoc, "too few operands for instruction");
511 ErrorLoc = ((SparcOperand &)*Operands[ErrorInfo]).getStartLoc();
512 if (ErrorLoc == SMLoc())
516 return Error(ErrorLoc, "invalid operand for instruction");
518 case Match_MnemonicFail:
519 return Error(IDLoc, "invalid instruction mnemonic");
521 llvm_unreachable("Implement any new match types added!");
524 bool SparcAsmParser::
525 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc)
527 const AsmToken &Tok = Parser.getTok();
528 StartLoc = Tok.getLoc();
529 EndLoc = Tok.getEndLoc();
531 if (getLexer().getKind() != AsmToken::Percent)
534 unsigned regKind = SparcOperand::rk_None;
535 if (matchRegisterName(Tok, RegNo, regKind)) {
540 return Error(StartLoc, "invalid register name");
543 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
546 bool SparcAsmParser::ParseInstruction(ParseInstructionInfo &Info,
547 StringRef Name, SMLoc NameLoc,
548 OperandVector &Operands) {
550 // First operand in MCInst is instruction mnemonic.
551 Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));
553 // apply mnemonic aliases, if any, so that we can parse operands correctly.
554 applyMnemonicAliases(Name, getAvailableFeatures(), 0);
556 if (getLexer().isNot(AsmToken::EndOfStatement)) {
557 // Read the first operand.
558 if (getLexer().is(AsmToken::Comma)) {
559 if (parseBranchModifiers(Operands) != MatchOperand_Success) {
560 SMLoc Loc = getLexer().getLoc();
561 Parser.eatToEndOfStatement();
562 return Error(Loc, "unexpected token");
565 if (parseOperand(Operands, Name) != MatchOperand_Success) {
566 SMLoc Loc = getLexer().getLoc();
567 Parser.eatToEndOfStatement();
568 return Error(Loc, "unexpected token");
571 while (getLexer().is(AsmToken::Comma)) {
572 Parser.Lex(); // Eat the comma.
573 // Parse and remember the operand.
574 if (parseOperand(Operands, Name) != MatchOperand_Success) {
575 SMLoc Loc = getLexer().getLoc();
576 Parser.eatToEndOfStatement();
577 return Error(Loc, "unexpected token");
581 if (getLexer().isNot(AsmToken::EndOfStatement)) {
582 SMLoc Loc = getLexer().getLoc();
583 Parser.eatToEndOfStatement();
584 return Error(Loc, "unexpected token");
586 Parser.Lex(); // Consume the EndOfStatement.
590 bool SparcAsmParser::
591 ParseDirective(AsmToken DirectiveID)
593 StringRef IDVal = DirectiveID.getString();
595 if (IDVal == ".byte")
596 return parseDirectiveWord(1, DirectiveID.getLoc());
598 if (IDVal == ".half")
599 return parseDirectiveWord(2, DirectiveID.getLoc());
601 if (IDVal == ".word")
602 return parseDirectiveWord(4, DirectiveID.getLoc());
604 if (IDVal == ".nword")
605 return parseDirectiveWord(is64Bit() ? 8 : 4, DirectiveID.getLoc());
607 if (is64Bit() && IDVal == ".xword")
608 return parseDirectiveWord(8, DirectiveID.getLoc());
610 if (IDVal == ".register") {
611 // For now, ignore .register directive.
612 Parser.eatToEndOfStatement();
616 // Let the MC layer to handle other directives.
620 bool SparcAsmParser:: parseDirectiveWord(unsigned Size, SMLoc L) {
621 if (getLexer().isNot(AsmToken::EndOfStatement)) {
624 if (getParser().parseExpression(Value))
627 getParser().getStreamer().EmitValue(Value, Size);
629 if (getLexer().is(AsmToken::EndOfStatement))
632 // FIXME: Improve diagnostic.
633 if (getLexer().isNot(AsmToken::Comma))
634 return Error(L, "unexpected token in directive");
642 SparcAsmParser::OperandMatchResultTy
643 SparcAsmParser::parseMEMOperand(OperandVector &Operands) {
646 unsigned BaseReg = 0;
648 if (ParseRegister(BaseReg, S, E)) {
649 return MatchOperand_NoMatch;
652 switch (getLexer().getKind()) {
653 default: return MatchOperand_NoMatch;
655 case AsmToken::Comma:
656 case AsmToken::RBrac:
657 case AsmToken::EndOfStatement:
658 Operands.push_back(SparcOperand::CreateMEMr(BaseReg, S, E));
659 return MatchOperand_Success;
661 case AsmToken:: Plus:
662 Parser.Lex(); // Eat the '+'
664 case AsmToken::Minus:
668 std::unique_ptr<SparcOperand> Offset;
669 OperandMatchResultTy ResTy = parseSparcAsmOperand(Offset);
670 if (ResTy != MatchOperand_Success || !Offset)
671 return MatchOperand_NoMatch;
674 Offset->isImm() ? SparcOperand::MorphToMEMri(BaseReg, std::move(Offset))
675 : SparcOperand::MorphToMEMrr(BaseReg, std::move(Offset)));
677 return MatchOperand_Success;
680 SparcAsmParser::OperandMatchResultTy
681 SparcAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
683 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
685 // If there wasn't a custom match, try the generic matcher below. Otherwise,
686 // there was a match, but an error occurred, in which case, just return that
687 // the operand parsing failed.
688 if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail)
691 if (getLexer().is(AsmToken::LBrac)) {
693 Operands.push_back(SparcOperand::CreateToken("[",
694 Parser.getTok().getLoc()));
695 Parser.Lex(); // Eat the [
697 if (Mnemonic == "cas" || Mnemonic == "casx") {
698 SMLoc S = Parser.getTok().getLoc();
699 if (getLexer().getKind() != AsmToken::Percent)
700 return MatchOperand_NoMatch;
701 Parser.Lex(); // eat %
703 unsigned RegNo, RegKind;
704 if (!matchRegisterName(Parser.getTok(), RegNo, RegKind))
705 return MatchOperand_NoMatch;
707 Parser.Lex(); // Eat the identifier token.
708 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1);
709 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E));
710 ResTy = MatchOperand_Success;
712 ResTy = parseMEMOperand(Operands);
715 if (ResTy != MatchOperand_Success)
718 if (!getLexer().is(AsmToken::RBrac))
719 return MatchOperand_ParseFail;
721 Operands.push_back(SparcOperand::CreateToken("]",
722 Parser.getTok().getLoc()));
723 Parser.Lex(); // Eat the ]
725 // Parse an optional address-space identifier after the address.
726 if (getLexer().is(AsmToken::Integer)) {
727 std::unique_ptr<SparcOperand> Op;
728 ResTy = parseSparcAsmOperand(Op, false);
729 if (ResTy != MatchOperand_Success || !Op)
730 return MatchOperand_ParseFail;
731 Operands.push_back(std::move(Op));
733 return MatchOperand_Success;
736 std::unique_ptr<SparcOperand> Op;
738 ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"));
739 if (ResTy != MatchOperand_Success || !Op)
740 return MatchOperand_ParseFail;
742 // Push the parsed operand into the list of operands
743 Operands.push_back(std::move(Op));
745 return MatchOperand_Success;
748 SparcAsmParser::OperandMatchResultTy
749 SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op,
752 SMLoc S = Parser.getTok().getLoc();
753 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
757 switch (getLexer().getKind()) {
760 case AsmToken::Percent:
761 Parser.Lex(); // Eat the '%'.
764 if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) {
765 StringRef name = Parser.getTok().getString();
766 Parser.Lex(); // Eat the identifier token.
767 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
770 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
773 Op = SparcOperand::CreateToken("%psr", S);
776 Op = SparcOperand::CreateToken("%wim", S);
779 Op = SparcOperand::CreateToken("%tbr", S);
783 Op = SparcOperand::CreateToken("%xcc", S);
785 Op = SparcOperand::CreateToken("%icc", S);
790 if (matchSparcAsmModifiers(EVal, E)) {
791 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
792 Op = SparcOperand::CreateImm(EVal, S, E);
796 case AsmToken::Minus:
797 case AsmToken::Integer:
798 case AsmToken::LParen:
799 if (!getParser().parseExpression(EVal, E))
800 Op = SparcOperand::CreateImm(EVal, S, E);
803 case AsmToken::Identifier: {
804 StringRef Identifier;
805 if (!getParser().parseIdentifier(Identifier)) {
806 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
807 MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
809 const MCExpr *Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
812 getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_)
813 Res = SparcMCExpr::create(SparcMCExpr::VK_Sparc_WPLT30, Res,
815 Op = SparcOperand::CreateImm(Res, S, E);
820 return (Op) ? MatchOperand_Success : MatchOperand_ParseFail;
823 SparcAsmParser::OperandMatchResultTy
824 SparcAsmParser::parseBranchModifiers(OperandVector &Operands) {
826 // parse (,a|,pn|,pt)+
828 while (getLexer().is(AsmToken::Comma)) {
830 Parser.Lex(); // Eat the comma
832 if (!getLexer().is(AsmToken::Identifier))
833 return MatchOperand_ParseFail;
834 StringRef modName = Parser.getTok().getString();
835 if (modName == "a" || modName == "pn" || modName == "pt") {
836 Operands.push_back(SparcOperand::CreateToken(modName,
837 Parser.getTok().getLoc()));
838 Parser.Lex(); // eat the identifier.
841 return MatchOperand_Success;
844 bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
850 RegKind = SparcOperand::rk_None;
851 if (Tok.is(AsmToken::Identifier)) {
852 StringRef name = Tok.getString();
855 if (name.equals("fp")) {
857 RegKind = SparcOperand::rk_IntReg;
861 if (name.equals("sp")) {
863 RegKind = SparcOperand::rk_IntReg;
867 if (name.equals("y")) {
869 RegKind = SparcOperand::rk_Special;
873 if (name.substr(0, 3).equals_lower("asr")
874 && !name.substr(3).getAsInteger(10, intVal)
875 && intVal > 0 && intVal < 32) {
876 RegNo = ASRRegs[intVal];
877 RegKind = SparcOperand::rk_Special;
881 if (name.equals("icc")) {
883 RegKind = SparcOperand::rk_Special;
887 if (name.equals("psr")) {
889 RegKind = SparcOperand::rk_Special;
893 if (name.equals("wim")) {
895 RegKind = SparcOperand::rk_Special;
899 if (name.equals("tbr")) {
901 RegKind = SparcOperand::rk_Special;
905 if (name.equals("xcc")) {
906 // FIXME:: check 64bit.
908 RegKind = SparcOperand::rk_Special;
913 if (name.substr(0, 3).equals_lower("fcc")
914 && !name.substr(3).getAsInteger(10, intVal)
916 // FIXME: check 64bit and handle %fcc1 - %fcc3
917 RegNo = Sparc::FCC0 + intVal;
918 RegKind = SparcOperand::rk_Special;
923 if (name.substr(0, 1).equals_lower("g")
924 && !name.substr(1).getAsInteger(10, intVal)
926 RegNo = IntRegs[intVal];
927 RegKind = SparcOperand::rk_IntReg;
931 if (name.substr(0, 1).equals_lower("o")
932 && !name.substr(1).getAsInteger(10, intVal)
934 RegNo = IntRegs[8 + intVal];
935 RegKind = SparcOperand::rk_IntReg;
938 if (name.substr(0, 1).equals_lower("l")
939 && !name.substr(1).getAsInteger(10, intVal)
941 RegNo = IntRegs[16 + intVal];
942 RegKind = SparcOperand::rk_IntReg;
945 if (name.substr(0, 1).equals_lower("i")
946 && !name.substr(1).getAsInteger(10, intVal)
948 RegNo = IntRegs[24 + intVal];
949 RegKind = SparcOperand::rk_IntReg;
953 if (name.substr(0, 1).equals_lower("f")
954 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 32) {
955 RegNo = FloatRegs[intVal];
956 RegKind = SparcOperand::rk_FloatReg;
960 if (name.substr(0, 1).equals_lower("f")
961 && !name.substr(1, 2).getAsInteger(10, intVal)
962 && intVal >= 32 && intVal <= 62 && (intVal % 2 == 0)) {
964 RegNo = DoubleRegs[intVal/2];
965 RegKind = SparcOperand::rk_DoubleReg;
970 if (name.substr(0, 1).equals_lower("r")
971 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 31) {
972 RegNo = IntRegs[intVal];
973 RegKind = SparcOperand::rk_IntReg;
980 // Determine if an expression contains a reference to the symbol
981 // "_GLOBAL_OFFSET_TABLE_".
982 static bool hasGOTReference(const MCExpr *Expr) {
983 switch (Expr->getKind()) {
985 if (const SparcMCExpr *SE = dyn_cast<SparcMCExpr>(Expr))
986 return hasGOTReference(SE->getSubExpr());
989 case MCExpr::Constant:
992 case MCExpr::Binary: {
993 const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
994 return hasGOTReference(BE->getLHS()) || hasGOTReference(BE->getRHS());
997 case MCExpr::SymbolRef: {
998 const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr);
999 return (SymRef.getSymbol().getName() == "_GLOBAL_OFFSET_TABLE_");
1003 return hasGOTReference(cast<MCUnaryExpr>(Expr)->getSubExpr());
1008 bool SparcAsmParser::matchSparcAsmModifiers(const MCExpr *&EVal,
1011 AsmToken Tok = Parser.getTok();
1012 if (!Tok.is(AsmToken::Identifier))
1015 StringRef name = Tok.getString();
1017 SparcMCExpr::VariantKind VK = SparcMCExpr::parseVariantKind(name);
1019 if (VK == SparcMCExpr::VK_Sparc_None)
1022 Parser.Lex(); // Eat the identifier.
1023 if (Parser.getTok().getKind() != AsmToken::LParen)
1026 Parser.Lex(); // Eat the LParen token.
1027 const MCExpr *subExpr;
1028 if (Parser.parseParenExpression(subExpr, EndLoc))
1031 bool isPIC = getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_;
1033 // Ugly: if a sparc assembly expression says "%hi(...)" but the
1034 // expression within contains _GLOBAL_OFFSET_TABLE_, it REALLY means
1035 // %pc22. Same with %lo -> %pc10. Worse, if it doesn't contain that,
1036 // the meaning depends on whether the assembler was invoked with
1037 // -KPIC or not: if so, it really means %got22/%got10; if not, it
1038 // actually means what it said! Sigh, historical mistakes...
1042 case SparcMCExpr::VK_Sparc_LO:
1043 VK = (hasGOTReference(subExpr)
1044 ? SparcMCExpr::VK_Sparc_PC10
1045 : (isPIC ? SparcMCExpr::VK_Sparc_GOT10 : VK));
1047 case SparcMCExpr::VK_Sparc_HI:
1048 VK = (hasGOTReference(subExpr)
1049 ? SparcMCExpr::VK_Sparc_PC22
1050 : (isPIC ? SparcMCExpr::VK_Sparc_GOT22 : VK));
1054 EVal = SparcMCExpr::create(VK, subExpr, getContext());
1058 extern "C" void LLVMInitializeSparcAsmParser() {
1059 RegisterMCAsmParser<SparcAsmParser> A(TheSparcTarget);
1060 RegisterMCAsmParser<SparcAsmParser> B(TheSparcV9Target);
1061 RegisterMCAsmParser<SparcAsmParser> C(TheSparcelTarget);
1064 #define GET_REGISTER_MATCHER
1065 #define GET_MATCHER_IMPLEMENTATION
1066 #include "SparcGenAsmMatcher.inc"
1068 unsigned SparcAsmParser::validateTargetOperandClass(MCParsedAsmOperand &GOp,
1070 SparcOperand &Op = (SparcOperand &)GOp;
1071 if (Op.isFloatOrDoubleReg()) {
1075 if (!Op.isFloatReg() || SparcOperand::MorphToDoubleReg(Op))
1076 return MCTargetAsmParser::Match_Success;
1079 if (SparcOperand::MorphToQuadReg(Op))
1080 return MCTargetAsmParser::Match_Success;
1084 if (Op.isIntReg() && Kind == MCK_IntPair) {
1085 if (SparcOperand::MorphToIntPairReg(Op))
1086 return MCTargetAsmParser::Match_Success;
1088 return Match_InvalidOperand;