1 //===-- DelaySlotFiller.cpp - SPARC delay slot filler ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a simple local pass that attempts to fill delay slots with useful
11 // instructions. If no instructions can be moved into the delay slot, then a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "delay-slot-filler"
17 #include "SparcSubtarget.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetRegisterInfo.h"
30 STATISTIC(FilledSlots, "Number of delay slots filled");
32 static cl::opt<bool> DisableDelaySlotFiller(
33 "disable-sparc-delay-filler",
35 cl::desc("Disable the Sparc delay slot filler."),
39 struct Filler : public MachineFunctionPass {
40 /// Target machine description which we query for reg. names, data
44 const SparcSubtarget *Subtarget;
47 Filler(TargetMachine &tm)
48 : MachineFunctionPass(ID), TM(tm),
49 Subtarget(&TM.getSubtarget<SparcSubtarget>()) {
52 virtual const char *getPassName() const {
53 return "SPARC Delay Slot Filler";
56 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
57 bool runOnMachineFunction(MachineFunction &F) {
60 // This pass invalidates liveness information when it reorders
61 // instructions to fill delay slot.
62 F.getRegInfo().invalidateLiveness();
64 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
66 Changed |= runOnMachineBasicBlock(*FI);
70 void insertCallDefsUses(MachineBasicBlock::iterator MI,
71 SmallSet<unsigned, 32>& RegDefs,
72 SmallSet<unsigned, 32>& RegUses);
74 void insertDefsUses(MachineBasicBlock::iterator MI,
75 SmallSet<unsigned, 32>& RegDefs,
76 SmallSet<unsigned, 32>& RegUses);
78 bool IsRegInSet(SmallSet<unsigned, 32>& RegSet,
81 bool delayHasHazard(MachineBasicBlock::iterator candidate,
82 bool &sawLoad, bool &sawStore,
83 SmallSet<unsigned, 32> &RegDefs,
84 SmallSet<unsigned, 32> &RegUses);
86 MachineBasicBlock::iterator
87 findDelayInstr(MachineBasicBlock &MBB, MachineBasicBlock::iterator slot);
89 bool needsUnimp(MachineBasicBlock::iterator I, unsigned &StructSize);
91 bool tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator MBBI);
96 } // end of anonymous namespace
98 /// createSparcDelaySlotFillerPass - Returns a pass that fills in delay
99 /// slots in Sparc MachineFunctions
101 FunctionPass *llvm::createSparcDelaySlotFillerPass(TargetMachine &tm) {
102 return new Filler(tm);
106 /// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
107 /// We assume there is only one delay slot per delayed instruction.
109 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
110 bool Changed = false;
112 const TargetInstrInfo *TII = TM.getInstrInfo();
114 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
115 MachineBasicBlock::iterator MI = I;
118 // If MI is restore, try combining it with previous inst.
119 if (!DisableDelaySlotFiller &&
120 (MI->getOpcode() == SP::RESTORErr
121 || MI->getOpcode() == SP::RESTOREri)) {
122 Changed |= tryCombineRestoreWithPrevInst(MBB, MI);
126 if (!Subtarget->isV9() &&
127 (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD
128 || MI->getOpcode() == SP::FCMPQ)) {
129 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
134 // If MI has no delay slot, skip.
135 if (!MI->hasDelaySlot())
138 MachineBasicBlock::iterator D = MBB.end();
140 if (!DisableDelaySlotFiller)
141 D = findDelayInstr(MBB, MI);
147 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
149 MBB.splice(I, &MBB, D);
151 unsigned structSize = 0;
152 if (needsUnimp(MI, structSize)) {
153 MachineBasicBlock::iterator J = MI;
154 ++J; // skip the delay filler.
155 assert (J != MBB.end() && "MI needs a delay instruction.");
156 BuildMI(MBB, ++J, MI->getDebugLoc(),
157 TII->get(SP::UNIMP)).addImm(structSize);
158 // Bundle the delay filler and unimp with the instruction.
159 MIBundleBuilder(MBB, MachineBasicBlock::iterator(MI), J);
161 MIBundleBuilder(MBB, MachineBasicBlock::iterator(MI), I);
167 MachineBasicBlock::iterator
168 Filler::findDelayInstr(MachineBasicBlock &MBB,
169 MachineBasicBlock::iterator slot)
171 SmallSet<unsigned, 32> RegDefs;
172 SmallSet<unsigned, 32> RegUses;
173 bool sawLoad = false;
174 bool sawStore = false;
176 if (slot == MBB.begin())
179 if (slot->getOpcode() == SP::RET || slot->getOpcode() == SP::TLS_CALL)
182 if (slot->getOpcode() == SP::RETL) {
183 MachineBasicBlock::iterator J = slot;
186 if (J->getOpcode() == SP::RESTORErr
187 || J->getOpcode() == SP::RESTOREri) {
188 // change retl to ret.
189 slot->setDesc(TM.getInstrInfo()->get(SP::RET));
194 // Call's delay filler can def some of call's uses.
196 insertCallDefsUses(slot, RegDefs, RegUses);
198 insertDefsUses(slot, RegDefs, RegUses);
202 MachineBasicBlock::iterator I = slot;
205 done = (I == MBB.begin());
211 if (I->isDebugValue())
214 if (I->hasUnmodeledSideEffects() || I->isInlineAsm() || I->isPosition() ||
215 I->hasDelaySlot() || I->isBundledWithSucc())
218 if (delayHasHazard(I, sawLoad, sawStore, RegDefs, RegUses)) {
219 insertDefsUses(I, RegDefs, RegUses);
228 bool Filler::delayHasHazard(MachineBasicBlock::iterator candidate,
231 SmallSet<unsigned, 32> &RegDefs,
232 SmallSet<unsigned, 32> &RegUses)
235 if (candidate->isImplicitDef() || candidate->isKill())
238 if (candidate->mayLoad()) {
244 if (candidate->mayStore()) {
252 for (unsigned i = 0, e = candidate->getNumOperands(); i!= e; ++i) {
253 const MachineOperand &MO = candidate->getOperand(i);
257 unsigned Reg = MO.getReg();
260 // check whether Reg is defined or used before delay slot.
261 if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
265 // check whether Reg is defined before delay slot.
266 if (IsRegInSet(RegDefs, Reg))
274 void Filler::insertCallDefsUses(MachineBasicBlock::iterator MI,
275 SmallSet<unsigned, 32>& RegDefs,
276 SmallSet<unsigned, 32>& RegUses)
278 // Call defines o7, which is visible to the instruction in delay slot.
279 RegDefs.insert(SP::O7);
281 switch(MI->getOpcode()) {
282 default: llvm_unreachable("Unknown opcode.");
283 case SP::CALL: break;
286 assert(MI->getNumOperands() >= 2);
287 const MachineOperand &Reg = MI->getOperand(0);
288 assert(Reg.isReg() && "CALL first operand is not a register.");
289 assert(Reg.isUse() && "CALL first operand is not a use.");
290 RegUses.insert(Reg.getReg());
292 const MachineOperand &RegOrImm = MI->getOperand(1);
293 if (RegOrImm.isImm())
295 assert(RegOrImm.isReg() && "CALLrr second operand is not a register.");
296 assert(RegOrImm.isUse() && "CALLrr second operand is not a use.");
297 RegUses.insert(RegOrImm.getReg());
302 // Insert Defs and Uses of MI into the sets RegDefs and RegUses.
303 void Filler::insertDefsUses(MachineBasicBlock::iterator MI,
304 SmallSet<unsigned, 32>& RegDefs,
305 SmallSet<unsigned, 32>& RegUses)
307 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
308 const MachineOperand &MO = MI->getOperand(i);
312 unsigned Reg = MO.getReg();
318 // Implicit register uses of retl are return values and
319 // retl does not use them.
320 if (MO.isImplicit() && MI->getOpcode() == SP::RETL)
327 // returns true if the Reg or its alias is in the RegSet.
328 bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg)
330 // Check Reg and all aliased Registers.
331 for (MCRegAliasIterator AI(Reg, TM.getRegisterInfo(), true);
333 if (RegSet.count(*AI))
338 bool Filler::needsUnimp(MachineBasicBlock::iterator I, unsigned &StructSize)
343 unsigned structSizeOpNum = 0;
344 switch (I->getOpcode()) {
345 default: llvm_unreachable("Unknown call opcode.");
346 case SP::CALL: structSizeOpNum = 1; break;
348 case SP::CALLri: structSizeOpNum = 2; break;
349 case SP::TLS_CALL: return false;
352 const MachineOperand &MO = I->getOperand(structSizeOpNum);
355 StructSize = MO.getImm();
359 static bool combineRestoreADD(MachineBasicBlock::iterator RestoreMI,
360 MachineBasicBlock::iterator AddMI,
361 const TargetInstrInfo *TII)
363 // Before: add <op0>, <op1>, %i[0-7]
364 // restore %g0, %g0, %i[0-7]
366 // After : restore <op0>, <op1>, %o[0-7]
368 unsigned reg = AddMI->getOperand(0).getReg();
369 if (reg < SP::I0 || reg > SP::I7)
373 RestoreMI->eraseFromParent();
375 // Change ADD to RESTORE.
376 AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr)
380 // Map the destination register.
381 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
386 static bool combineRestoreOR(MachineBasicBlock::iterator RestoreMI,
387 MachineBasicBlock::iterator OrMI,
388 const TargetInstrInfo *TII)
390 // Before: or <op0>, <op1>, %i[0-7]
391 // restore %g0, %g0, %i[0-7]
392 // and <op0> or <op1> is zero,
394 // After : restore <op0>, <op1>, %o[0-7]
396 unsigned reg = OrMI->getOperand(0).getReg();
397 if (reg < SP::I0 || reg > SP::I7)
400 // check whether it is a copy.
401 if (OrMI->getOpcode() == SP::ORrr
402 && OrMI->getOperand(1).getReg() != SP::G0
403 && OrMI->getOperand(2).getReg() != SP::G0)
406 if (OrMI->getOpcode() == SP::ORri
407 && OrMI->getOperand(1).getReg() != SP::G0
408 && (!OrMI->getOperand(2).isImm() || OrMI->getOperand(2).getImm() != 0))
412 RestoreMI->eraseFromParent();
414 // Change OR to RESTORE.
415 OrMI->setDesc(TII->get((OrMI->getOpcode() == SP::ORrr)
419 // Map the destination register.
420 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
425 static bool combineRestoreSETHIi(MachineBasicBlock::iterator RestoreMI,
426 MachineBasicBlock::iterator SetHiMI,
427 const TargetInstrInfo *TII)
429 // Before: sethi imm3, %i[0-7]
430 // restore %g0, %g0, %g0
432 // After : restore %g0, (imm3<<10), %o[0-7]
434 unsigned reg = SetHiMI->getOperand(0).getReg();
435 if (reg < SP::I0 || reg > SP::I7)
438 if (!SetHiMI->getOperand(1).isImm())
441 int64_t imm = SetHiMI->getOperand(1).getImm();
443 // Is it a 3 bit immediate?
447 // Make it a 13 bit immediate.
448 imm = (imm << 10) & 0x1FFF;
450 assert(RestoreMI->getOpcode() == SP::RESTORErr);
452 RestoreMI->setDesc(TII->get(SP::RESTOREri));
454 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
455 RestoreMI->getOperand(1).setReg(SP::G0);
456 RestoreMI->getOperand(2).ChangeToImmediate(imm);
459 // Erase the original SETHI.
460 SetHiMI->eraseFromParent();
465 bool Filler::tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB,
466 MachineBasicBlock::iterator MBBI)
468 // No previous instruction.
469 if (MBBI == MBB.begin())
472 // assert that MBBI is a "restore %g0, %g0, %g0".
473 assert(MBBI->getOpcode() == SP::RESTORErr
474 && MBBI->getOperand(0).getReg() == SP::G0
475 && MBBI->getOperand(1).getReg() == SP::G0
476 && MBBI->getOperand(2).getReg() == SP::G0);
478 MachineBasicBlock::iterator PrevInst = std::prev(MBBI);
480 // It cannot be combined with a bundled instruction.
481 if (PrevInst->isBundledWithSucc())
484 const TargetInstrInfo *TII = TM.getInstrInfo();
486 switch (PrevInst->getOpcode()) {
489 case SP::ADDri: return combineRestoreADD(MBBI, PrevInst, TII); break;
491 case SP::ORri: return combineRestoreOR(MBBI, PrevInst, TII); break;
492 case SP::SETHIi: return combineRestoreSETHIi(MBBI, PrevInst, TII); break;
494 // It cannot combine with the previous instruction.