1 //===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the Sparc Disassembler.
12 //===----------------------------------------------------------------------===//
15 #include "SparcRegisterInfo.h"
16 #include "SparcSubtarget.h"
17 #include "llvm/MC/MCDisassembler.h"
18 #include "llvm/MC/MCFixedLenDisassembler.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/Support/TargetRegistry.h"
26 #define DEBUG_TYPE "sparc-disassembler"
28 typedef MCDisassembler::DecodeStatus DecodeStatus;
32 /// A disassembler class for Sparc.
33 class SparcDisassembler : public MCDisassembler {
35 SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
36 : MCDisassembler(STI, Ctx) {}
37 virtual ~SparcDisassembler() {}
39 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
40 ArrayRef<uint8_t> Bytes, uint64_t Address,
42 raw_ostream &CStream) const override;
47 extern Target TheSparcTarget, TheSparcV9Target, TheSparcelTarget;
50 static MCDisassembler *createSparcDisassembler(const Target &T,
51 const MCSubtargetInfo &STI,
53 return new SparcDisassembler(STI, Ctx);
57 extern "C" void LLVMInitializeSparcDisassembler() {
58 // Register the disassembler.
59 TargetRegistry::RegisterMCDisassembler(TheSparcTarget,
60 createSparcDisassembler);
61 TargetRegistry::RegisterMCDisassembler(TheSparcV9Target,
62 createSparcDisassembler);
63 TargetRegistry::RegisterMCDisassembler(TheSparcelTarget,
64 createSparcDisassembler);
67 static const unsigned IntRegDecoderTable[] = {
68 SP::G0, SP::G1, SP::G2, SP::G3,
69 SP::G4, SP::G5, SP::G6, SP::G7,
70 SP::O0, SP::O1, SP::O2, SP::O3,
71 SP::O4, SP::O5, SP::O6, SP::O7,
72 SP::L0, SP::L1, SP::L2, SP::L3,
73 SP::L4, SP::L5, SP::L6, SP::L7,
74 SP::I0, SP::I1, SP::I2, SP::I3,
75 SP::I4, SP::I5, SP::I6, SP::I7 };
77 static const unsigned FPRegDecoderTable[] = {
78 SP::F0, SP::F1, SP::F2, SP::F3,
79 SP::F4, SP::F5, SP::F6, SP::F7,
80 SP::F8, SP::F9, SP::F10, SP::F11,
81 SP::F12, SP::F13, SP::F14, SP::F15,
82 SP::F16, SP::F17, SP::F18, SP::F19,
83 SP::F20, SP::F21, SP::F22, SP::F23,
84 SP::F24, SP::F25, SP::F26, SP::F27,
85 SP::F28, SP::F29, SP::F30, SP::F31 };
87 static const unsigned DFPRegDecoderTable[] = {
88 SP::D0, SP::D16, SP::D1, SP::D17,
89 SP::D2, SP::D18, SP::D3, SP::D19,
90 SP::D4, SP::D20, SP::D5, SP::D21,
91 SP::D6, SP::D22, SP::D7, SP::D23,
92 SP::D8, SP::D24, SP::D9, SP::D25,
93 SP::D10, SP::D26, SP::D11, SP::D27,
94 SP::D12, SP::D28, SP::D13, SP::D29,
95 SP::D14, SP::D30, SP::D15, SP::D31 };
97 static const unsigned QFPRegDecoderTable[] = {
98 SP::Q0, SP::Q8, ~0U, ~0U,
99 SP::Q1, SP::Q9, ~0U, ~0U,
100 SP::Q2, SP::Q10, ~0U, ~0U,
101 SP::Q3, SP::Q11, ~0U, ~0U,
102 SP::Q4, SP::Q12, ~0U, ~0U,
103 SP::Q5, SP::Q13, ~0U, ~0U,
104 SP::Q6, SP::Q14, ~0U, ~0U,
105 SP::Q7, SP::Q15, ~0U, ~0U } ;
107 static const unsigned FCCRegDecoderTable[] = {
108 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
110 static const unsigned ASRRegDecoderTable[] = {
111 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
112 SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
113 SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
114 SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
115 SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
116 SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
117 SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
118 SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
120 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst,
123 const void *Decoder) {
125 return MCDisassembler::Fail;
126 unsigned Reg = IntRegDecoderTable[RegNo];
127 Inst.addOperand(MCOperand::createReg(Reg));
128 return MCDisassembler::Success;
131 static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst,
134 const void *Decoder) {
136 return MCDisassembler::Fail;
137 unsigned Reg = IntRegDecoderTable[RegNo];
138 Inst.addOperand(MCOperand::createReg(Reg));
139 return MCDisassembler::Success;
143 static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst,
146 const void *Decoder) {
148 return MCDisassembler::Fail;
149 unsigned Reg = FPRegDecoderTable[RegNo];
150 Inst.addOperand(MCOperand::createReg(Reg));
151 return MCDisassembler::Success;
155 static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst,
158 const void *Decoder) {
160 return MCDisassembler::Fail;
161 unsigned Reg = DFPRegDecoderTable[RegNo];
162 Inst.addOperand(MCOperand::createReg(Reg));
163 return MCDisassembler::Success;
167 static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst,
170 const void *Decoder) {
172 return MCDisassembler::Fail;
174 unsigned Reg = QFPRegDecoderTable[RegNo];
176 return MCDisassembler::Fail;
177 Inst.addOperand(MCOperand::createReg(Reg));
178 return MCDisassembler::Success;
181 static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
183 const void *Decoder) {
185 return MCDisassembler::Fail;
186 Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo]));
187 return MCDisassembler::Success;
190 static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
192 const void *Decoder) {
194 return MCDisassembler::Fail;
195 Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo]));
196 return MCDisassembler::Success;
200 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
201 const void *Decoder);
202 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
203 const void *Decoder);
204 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
205 const void *Decoder);
206 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
207 const void *Decoder);
208 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
209 uint64_t Address, const void *Decoder);
210 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn,
211 uint64_t Address, const void *Decoder);
212 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
213 uint64_t Address, const void *Decoder);
214 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
215 uint64_t Address, const void *Decoder);
216 static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn,
217 uint64_t Address, const void *Decoder);
218 static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn,
219 uint64_t Address, const void *Decoder);
220 static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address,
221 const void *Decoder);
222 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
223 const void *Decoder);
224 static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address,
225 const void *Decoder);
227 #include "SparcGenDisassemblerTables.inc"
229 /// Read four bytes from the ArrayRef and return 32 bit word.
230 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
231 uint64_t &Size, uint32_t &Insn,
232 bool IsLittleEndian) {
233 // We want to read exactly 4 Bytes of data.
234 if (Bytes.size() < 4) {
236 return MCDisassembler::Fail;
239 Insn = IsLittleEndian
240 ? (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
242 : (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) |
245 return MCDisassembler::Success;
248 DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
249 ArrayRef<uint8_t> Bytes,
251 raw_ostream &VStream,
252 raw_ostream &CStream) const {
254 bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian();
255 DecodeStatus Result =
256 readInstruction32(Bytes, Address, Size, Insn, isLittleEndian);
257 if (Result == MCDisassembler::Fail)
258 return MCDisassembler::Fail;
260 // Calling the auto-generated decoder function.
262 decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI);
264 if (Result != MCDisassembler::Fail) {
269 return MCDisassembler::Fail;
273 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
274 const void *Decoder);
276 static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address,
278 bool isLoad, DecodeFunc DecodeRD) {
279 unsigned rd = fieldFromInstruction(insn, 25, 5);
280 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
281 bool isImm = fieldFromInstruction(insn, 13, 1);
282 bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
283 unsigned asi = fieldFromInstruction(insn, 5, 8);
287 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
289 rs2 = fieldFromInstruction(insn, 0, 5);
293 status = DecodeRD(MI, rd, Address, Decoder);
294 if (status != MCDisassembler::Success)
299 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
300 if (status != MCDisassembler::Success)
305 MI.addOperand(MCOperand::createImm(simm13));
307 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
308 if (status != MCDisassembler::Success)
313 MI.addOperand(MCOperand::createImm(asi));
316 status = DecodeRD(MI, rd, Address, Decoder);
317 if (status != MCDisassembler::Success)
320 return MCDisassembler::Success;
323 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
324 const void *Decoder) {
325 return DecodeMem(Inst, insn, Address, Decoder, true,
326 DecodeIntRegsRegisterClass);
329 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
330 const void *Decoder) {
331 return DecodeMem(Inst, insn, Address, Decoder, true,
332 DecodeFPRegsRegisterClass);
335 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
336 const void *Decoder) {
337 return DecodeMem(Inst, insn, Address, Decoder, true,
338 DecodeDFPRegsRegisterClass);
341 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
342 const void *Decoder) {
343 return DecodeMem(Inst, insn, Address, Decoder, true,
344 DecodeQFPRegsRegisterClass);
347 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
348 uint64_t Address, const void *Decoder) {
349 return DecodeMem(Inst, insn, Address, Decoder, false,
350 DecodeIntRegsRegisterClass);
353 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
354 const void *Decoder) {
355 return DecodeMem(Inst, insn, Address, Decoder, false,
356 DecodeFPRegsRegisterClass);
359 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
360 uint64_t Address, const void *Decoder) {
361 return DecodeMem(Inst, insn, Address, Decoder, false,
362 DecodeDFPRegsRegisterClass);
365 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
366 uint64_t Address, const void *Decoder) {
367 return DecodeMem(Inst, insn, Address, Decoder, false,
368 DecodeQFPRegsRegisterClass);
371 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
372 uint64_t Address, uint64_t Offset,
373 uint64_t Width, MCInst &MI,
374 const void *Decoder) {
375 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
376 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
380 static DecodeStatus DecodeCall(MCInst &MI, unsigned insn,
381 uint64_t Address, const void *Decoder) {
382 unsigned tgt = fieldFromInstruction(insn, 0, 30);
384 if (!tryAddingSymbolicOperand(tgt+Address, false, Address,
386 MI.addOperand(MCOperand::createImm(tgt));
387 return MCDisassembler::Success;
390 static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn,
391 uint64_t Address, const void *Decoder) {
392 unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
393 MI.addOperand(MCOperand::createImm(tgt));
394 return MCDisassembler::Success;
397 static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address,
398 const void *Decoder) {
400 unsigned rd = fieldFromInstruction(insn, 25, 5);
401 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
402 unsigned isImm = fieldFromInstruction(insn, 13, 1);
406 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
408 rs2 = fieldFromInstruction(insn, 0, 5);
411 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
412 if (status != MCDisassembler::Success)
416 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
417 if (status != MCDisassembler::Success)
420 // Decode RS1 | SIMM13.
422 MI.addOperand(MCOperand::createImm(simm13));
424 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
425 if (status != MCDisassembler::Success)
428 return MCDisassembler::Success;
431 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
432 const void *Decoder) {
434 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
435 unsigned isImm = fieldFromInstruction(insn, 13, 1);
439 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
441 rs2 = fieldFromInstruction(insn, 0, 5);
444 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
445 if (status != MCDisassembler::Success)
448 // Decode RS2 | SIMM13.
450 MI.addOperand(MCOperand::createImm(simm13));
452 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
453 if (status != MCDisassembler::Success)
456 return MCDisassembler::Success;
459 static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address,
460 const void *Decoder) {
462 unsigned rd = fieldFromInstruction(insn, 25, 5);
463 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
464 unsigned isImm = fieldFromInstruction(insn, 13, 1);
465 bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
466 unsigned asi = fieldFromInstruction(insn, 5, 8);
470 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
472 rs2 = fieldFromInstruction(insn, 0, 5);
475 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
476 if (status != MCDisassembler::Success)
480 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
481 if (status != MCDisassembler::Success)
484 // Decode RS1 | SIMM13.
486 MI.addOperand(MCOperand::createImm(simm13));
488 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
489 if (status != MCDisassembler::Success)
494 MI.addOperand(MCOperand::createImm(asi));
496 return MCDisassembler::Success;