1 //===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the Sparc Disassembler.
12 //===----------------------------------------------------------------------===//
15 #include "SparcRegisterInfo.h"
16 #include "SparcSubtarget.h"
17 #include "llvm/MC/MCDisassembler.h"
18 #include "llvm/MC/MCFixedLenDisassembler.h"
19 #include "llvm/Support/TargetRegistry.h"
23 #define DEBUG_TYPE "sparc-disassembler"
25 typedef MCDisassembler::DecodeStatus DecodeStatus;
29 /// A disassembler class for Sparc.
30 class SparcDisassembler : public MCDisassembler {
32 SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
33 : MCDisassembler(STI, Ctx) {}
34 virtual ~SparcDisassembler() {}
36 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
37 ArrayRef<uint8_t> Bytes, uint64_t Address,
39 raw_ostream &CStream) const override;
45 extern Target TheSparcTarget, TheSparcV9Target;
48 static MCDisassembler *createSparcDisassembler(
50 const MCSubtargetInfo &STI,
52 return new SparcDisassembler(STI, Ctx);
56 extern "C" void LLVMInitializeSparcDisassembler() {
57 // Register the disassembler.
58 TargetRegistry::RegisterMCDisassembler(TheSparcTarget,
59 createSparcDisassembler);
60 TargetRegistry::RegisterMCDisassembler(TheSparcV9Target,
61 createSparcDisassembler);
66 static const unsigned IntRegDecoderTable[] = {
67 SP::G0, SP::G1, SP::G2, SP::G3,
68 SP::G4, SP::G5, SP::G6, SP::G7,
69 SP::O0, SP::O1, SP::O2, SP::O3,
70 SP::O4, SP::O5, SP::O6, SP::O7,
71 SP::L0, SP::L1, SP::L2, SP::L3,
72 SP::L4, SP::L5, SP::L6, SP::L7,
73 SP::I0, SP::I1, SP::I2, SP::I3,
74 SP::I4, SP::I5, SP::I6, SP::I7 };
76 static const unsigned FPRegDecoderTable[] = {
77 SP::F0, SP::F1, SP::F2, SP::F3,
78 SP::F4, SP::F5, SP::F6, SP::F7,
79 SP::F8, SP::F9, SP::F10, SP::F11,
80 SP::F12, SP::F13, SP::F14, SP::F15,
81 SP::F16, SP::F17, SP::F18, SP::F19,
82 SP::F20, SP::F21, SP::F22, SP::F23,
83 SP::F24, SP::F25, SP::F26, SP::F27,
84 SP::F28, SP::F29, SP::F30, SP::F31 };
86 static const unsigned DFPRegDecoderTable[] = {
87 SP::D0, SP::D16, SP::D1, SP::D17,
88 SP::D2, SP::D18, SP::D3, SP::D19,
89 SP::D4, SP::D20, SP::D5, SP::D21,
90 SP::D6, SP::D22, SP::D7, SP::D23,
91 SP::D8, SP::D24, SP::D9, SP::D25,
92 SP::D10, SP::D26, SP::D11, SP::D27,
93 SP::D12, SP::D28, SP::D13, SP::D29,
94 SP::D14, SP::D30, SP::D15, SP::D31 };
96 static const unsigned QFPRegDecoderTable[] = {
97 SP::Q0, SP::Q8, ~0U, ~0U,
98 SP::Q1, SP::Q9, ~0U, ~0U,
99 SP::Q2, SP::Q10, ~0U, ~0U,
100 SP::Q3, SP::Q11, ~0U, ~0U,
101 SP::Q4, SP::Q12, ~0U, ~0U,
102 SP::Q5, SP::Q13, ~0U, ~0U,
103 SP::Q6, SP::Q14, ~0U, ~0U,
104 SP::Q7, SP::Q15, ~0U, ~0U } ;
106 static const unsigned FCCRegDecoderTable[] = {
107 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
109 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst,
112 const void *Decoder) {
114 return MCDisassembler::Fail;
115 unsigned Reg = IntRegDecoderTable[RegNo];
116 Inst.addOperand(MCOperand::CreateReg(Reg));
117 return MCDisassembler::Success;
120 static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst,
123 const void *Decoder) {
125 return MCDisassembler::Fail;
126 unsigned Reg = IntRegDecoderTable[RegNo];
127 Inst.addOperand(MCOperand::CreateReg(Reg));
128 return MCDisassembler::Success;
132 static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst,
135 const void *Decoder) {
137 return MCDisassembler::Fail;
138 unsigned Reg = FPRegDecoderTable[RegNo];
139 Inst.addOperand(MCOperand::CreateReg(Reg));
140 return MCDisassembler::Success;
144 static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst,
147 const void *Decoder) {
149 return MCDisassembler::Fail;
150 unsigned Reg = DFPRegDecoderTable[RegNo];
151 Inst.addOperand(MCOperand::CreateReg(Reg));
152 return MCDisassembler::Success;
156 static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst,
159 const void *Decoder) {
161 return MCDisassembler::Fail;
163 unsigned Reg = QFPRegDecoderTable[RegNo];
165 return MCDisassembler::Fail;
166 Inst.addOperand(MCOperand::CreateReg(Reg));
167 return MCDisassembler::Success;
170 static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
172 const void *Decoder) {
174 return MCDisassembler::Fail;
175 Inst.addOperand(MCOperand::CreateReg(FCCRegDecoderTable[RegNo]));
176 return MCDisassembler::Success;
180 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
181 const void *Decoder);
182 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
183 const void *Decoder);
184 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
185 const void *Decoder);
186 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
187 const void *Decoder);
188 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn,
191 uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
193 uint64_t Address, const void *Decoder);
194 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
195 uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn,
197 uint64_t Address, const void *Decoder);
198 static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn,
199 uint64_t Address, const void *Decoder);
200 static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address,
201 const void *Decoder);
202 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
203 const void *Decoder);
204 static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address,
205 const void *Decoder);
207 #include "SparcGenDisassemblerTables.inc"
209 /// Read four bytes from the ArrayRef and return 32 bit word.
210 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
211 uint64_t &Size, uint32_t &Insn) {
212 // We want to read exactly 4 Bytes of data.
213 if (Bytes.size() < 4) {
215 return MCDisassembler::Fail;
218 // Encoded as a big-endian 32-bit word in the stream.
220 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
222 return MCDisassembler::Success;
225 DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
226 ArrayRef<uint8_t> Bytes,
228 raw_ostream &VStream,
229 raw_ostream &CStream) const {
232 DecodeStatus Result = readInstruction32(Bytes, Address, Size, Insn);
233 if (Result == MCDisassembler::Fail)
234 return MCDisassembler::Fail;
237 // Calling the auto-generated decoder function.
239 decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI);
241 if (Result != MCDisassembler::Fail) {
246 return MCDisassembler::Fail;
250 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
251 const void *Decoder);
253 static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address,
255 bool isLoad, DecodeFunc DecodeRD) {
256 unsigned rd = fieldFromInstruction(insn, 25, 5);
257 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
258 bool isImm = fieldFromInstruction(insn, 13, 1);
262 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
264 rs2 = fieldFromInstruction(insn, 0, 5);
268 status = DecodeRD(MI, rd, Address, Decoder);
269 if (status != MCDisassembler::Success)
274 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
275 if (status != MCDisassembler::Success)
280 MI.addOperand(MCOperand::CreateImm(simm13));
282 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
283 if (status != MCDisassembler::Success)
288 status = DecodeRD(MI, rd, Address, Decoder);
289 if (status != MCDisassembler::Success)
292 return MCDisassembler::Success;
295 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
296 const void *Decoder) {
297 return DecodeMem(Inst, insn, Address, Decoder, true,
298 DecodeIntRegsRegisterClass);
301 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
302 const void *Decoder) {
303 return DecodeMem(Inst, insn, Address, Decoder, true,
304 DecodeFPRegsRegisterClass);
307 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
308 const void *Decoder) {
309 return DecodeMem(Inst, insn, Address, Decoder, true,
310 DecodeDFPRegsRegisterClass);
313 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
314 const void *Decoder) {
315 return DecodeMem(Inst, insn, Address, Decoder, true,
316 DecodeQFPRegsRegisterClass);
319 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
320 uint64_t Address, const void *Decoder) {
321 return DecodeMem(Inst, insn, Address, Decoder, false,
322 DecodeIntRegsRegisterClass);
325 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
326 const void *Decoder) {
327 return DecodeMem(Inst, insn, Address, Decoder, false,
328 DecodeFPRegsRegisterClass);
331 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
332 uint64_t Address, const void *Decoder) {
333 return DecodeMem(Inst, insn, Address, Decoder, false,
334 DecodeDFPRegsRegisterClass);
337 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
338 uint64_t Address, const void *Decoder) {
339 return DecodeMem(Inst, insn, Address, Decoder, false,
340 DecodeQFPRegsRegisterClass);
343 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
344 uint64_t Address, uint64_t Offset,
345 uint64_t Width, MCInst &MI,
346 const void *Decoder) {
347 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
348 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
352 static DecodeStatus DecodeCall(MCInst &MI, unsigned insn,
353 uint64_t Address, const void *Decoder) {
354 unsigned tgt = fieldFromInstruction(insn, 0, 30);
356 if (!tryAddingSymbolicOperand(tgt+Address, false, Address,
358 MI.addOperand(MCOperand::CreateImm(tgt));
359 return MCDisassembler::Success;
362 static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn,
363 uint64_t Address, const void *Decoder) {
364 unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
365 MI.addOperand(MCOperand::CreateImm(tgt));
366 return MCDisassembler::Success;
369 static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address,
370 const void *Decoder) {
372 unsigned rd = fieldFromInstruction(insn, 25, 5);
373 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
374 unsigned isImm = fieldFromInstruction(insn, 13, 1);
378 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
380 rs2 = fieldFromInstruction(insn, 0, 5);
383 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
384 if (status != MCDisassembler::Success)
388 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
389 if (status != MCDisassembler::Success)
392 // Decode RS1 | SIMM13.
394 MI.addOperand(MCOperand::CreateImm(simm13));
396 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
397 if (status != MCDisassembler::Success)
400 return MCDisassembler::Success;
403 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
404 const void *Decoder) {
406 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
407 unsigned isImm = fieldFromInstruction(insn, 13, 1);
411 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
413 rs2 = fieldFromInstruction(insn, 0, 5);
416 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
417 if (status != MCDisassembler::Success)
420 // Decode RS2 | SIMM13.
422 MI.addOperand(MCOperand::CreateImm(simm13));
424 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
425 if (status != MCDisassembler::Success)
428 return MCDisassembler::Success;
431 static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address,
432 const void *Decoder) {
434 unsigned rd = fieldFromInstruction(insn, 25, 5);
435 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
436 unsigned isImm = fieldFromInstruction(insn, 13, 1);
440 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
442 rs2 = fieldFromInstruction(insn, 0, 5);
445 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
446 if (status != MCDisassembler::Success)
450 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
451 if (status != MCDisassembler::Success)
454 // Decode RS1 | SIMM13.
456 MI.addOperand(MCOperand::CreateImm(simm13));
458 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
459 if (status != MCDisassembler::Success)
462 return MCDisassembler::Success;