1 //===-- SparcMCCodeEmitter.cpp - Convert Sparc code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SparcMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #include "SparcMCExpr.h"
15 #include "MCTargetDesc/SparcFixupKinds.h"
16 #include "SparcMCTargetDesc.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSymbol.h"
24 #include "llvm/Support/raw_ostream.h"
28 #define DEBUG_TYPE "mccodeemitter"
30 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
33 class SparcMCCodeEmitter : public MCCodeEmitter {
34 SparcMCCodeEmitter(const SparcMCCodeEmitter &) = delete;
35 void operator=(const SparcMCCodeEmitter &) = delete;
39 SparcMCCodeEmitter(MCContext &ctx): Ctx(ctx) {}
41 ~SparcMCCodeEmitter() override {}
43 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
44 SmallVectorImpl<MCFixup> &Fixups,
45 const MCSubtargetInfo &STI) const override;
47 // getBinaryCodeForInstr - TableGen'erated function for getting the
48 // binary encoding for an instruction.
49 uint64_t getBinaryCodeForInstr(const MCInst &MI,
50 SmallVectorImpl<MCFixup> &Fixups,
51 const MCSubtargetInfo &STI) const;
53 /// getMachineOpValue - Return binary encoding of operand. If the machine
54 /// operand requires relocation, record the relocation and return zero.
55 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
56 SmallVectorImpl<MCFixup> &Fixups,
57 const MCSubtargetInfo &STI) const;
59 unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
60 SmallVectorImpl<MCFixup> &Fixups,
61 const MCSubtargetInfo &STI) const;
62 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
63 SmallVectorImpl<MCFixup> &Fixups,
64 const MCSubtargetInfo &STI) const;
65 unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
66 SmallVectorImpl<MCFixup> &Fixups,
67 const MCSubtargetInfo &STI) const;
68 unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
69 SmallVectorImpl<MCFixup> &Fixups,
70 const MCSubtargetInfo &STI) const;
73 } // end anonymous namespace
75 MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII,
76 const MCRegisterInfo &MRI,
78 return new SparcMCCodeEmitter(Ctx);
81 void SparcMCCodeEmitter::
82 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
83 SmallVectorImpl<MCFixup> &Fixups,
84 const MCSubtargetInfo &STI) const {
85 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
87 // Output the constant in big endian byte order.
88 for (unsigned i = 0; i != 4; ++i) {
89 OS << (char)(Bits >> 24);
93 switch (MI.getOpcode()) {
95 case SP::TLS_CALL: tlsOpNo = 1; break;
99 case SP::TLS_LDXrr: tlsOpNo = 3; break;
102 const MCOperand &MO = MI.getOperand(tlsOpNo);
103 uint64_t op = getMachineOpValue(MI, MO, Fixups, STI);
104 assert(op == 0 && "Unexpected operand value!");
105 (void)op; // suppress warning.
108 ++MCNumEmitted; // Keep track of the # of mi's emitted.
112 unsigned SparcMCCodeEmitter::
113 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
114 SmallVectorImpl<MCFixup> &Fixups,
115 const MCSubtargetInfo &STI) const {
118 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
124 const MCExpr *Expr = MO.getExpr();
125 if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
126 MCFixupKind Kind = (MCFixupKind)SExpr->getFixupKind();
127 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
132 if (Expr->EvaluateAsAbsolute(Res))
135 llvm_unreachable("Unhandled expression!");
139 unsigned SparcMCCodeEmitter::
140 getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
141 SmallVectorImpl<MCFixup> &Fixups,
142 const MCSubtargetInfo &STI) const {
143 const MCOperand &MO = MI.getOperand(OpNo);
144 if (MO.isReg() || MO.isImm())
145 return getMachineOpValue(MI, MO, Fixups, STI);
147 if (MI.getOpcode() == SP::TLS_CALL) {
148 // No fixups for __tls_get_addr. Will emit for fixups for tls_symbol in
149 // EncodeInstruction.
151 // Verify that the callee is actually __tls_get_addr.
152 const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr());
153 assert(SExpr && SExpr->getSubExpr()->getKind() == MCExpr::SymbolRef &&
154 "Unexpected expression in TLS_CALL");
155 const MCSymbolRefExpr *SymExpr = cast<MCSymbolRefExpr>(SExpr->getSubExpr());
156 assert(SymExpr->getSymbol().getName() == "__tls_get_addr" &&
157 "Unexpected function for TLS_CALL");
162 MCFixupKind fixupKind = (MCFixupKind)Sparc::fixup_sparc_call30;
164 if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr())) {
165 if (SExpr->getKind() == SparcMCExpr::VK_Sparc_WPLT30)
166 fixupKind = (MCFixupKind)Sparc::fixup_sparc_wplt30;
169 Fixups.push_back(MCFixup::Create(0, MO.getExpr(), fixupKind));
174 unsigned SparcMCCodeEmitter::
175 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
176 SmallVectorImpl<MCFixup> &Fixups,
177 const MCSubtargetInfo &STI) const {
178 const MCOperand &MO = MI.getOperand(OpNo);
179 if (MO.isReg() || MO.isImm())
180 return getMachineOpValue(MI, MO, Fixups, STI);
182 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
183 (MCFixupKind)Sparc::fixup_sparc_br22));
187 unsigned SparcMCCodeEmitter::
188 getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
189 SmallVectorImpl<MCFixup> &Fixups,
190 const MCSubtargetInfo &STI) const {
191 const MCOperand &MO = MI.getOperand(OpNo);
192 if (MO.isReg() || MO.isImm())
193 return getMachineOpValue(MI, MO, Fixups, STI);
195 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
196 (MCFixupKind)Sparc::fixup_sparc_br19));
199 unsigned SparcMCCodeEmitter::
200 getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
201 SmallVectorImpl<MCFixup> &Fixups,
202 const MCSubtargetInfo &STI) const {
203 const MCOperand &MO = MI.getOperand(OpNo);
204 if (MO.isReg() || MO.isImm())
205 return getMachineOpValue(MI, MO, Fixups, STI);
207 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
208 (MCFixupKind)Sparc::fixup_sparc_br16_2));
209 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
210 (MCFixupKind)Sparc::fixup_sparc_br16_14));
217 #include "SparcGenMCCodeEmitter.inc"