1 //===-- SparcAsmPrinter.cpp - Sparc LLVM assembly writer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format SPARC assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "InstPrinter/SparcInstPrinter.h"
18 #include "MCTargetDesc/SparcBaseInfo.h"
19 #include "MCTargetDesc/SparcMCExpr.h"
20 #include "SparcInstrInfo.h"
21 #include "SparcTargetMachine.h"
22 #include "SparcTargetStreamer.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/CodeGen/AsmPrinter.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Mangler.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCContext.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/MC/MCSymbol.h"
33 #include "llvm/Support/TargetRegistry.h"
34 #include "llvm/Support/raw_ostream.h"
38 class SparcAsmPrinter : public AsmPrinter {
39 SparcTargetStreamer &getTargetStreamer() {
40 return static_cast<SparcTargetStreamer &>(
41 *OutStreamer.getTargetStreamer());
44 explicit SparcAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
45 : AsmPrinter(TM, Streamer) {}
47 virtual const char *getPassName() const {
48 return "Sparc Assembly Printer";
51 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
52 void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS,
53 const char *Modifier = 0);
54 void printCCOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
56 virtual void EmitFunctionBodyStart();
57 virtual void EmitInstruction(const MachineInstr *MI);
59 static const char *getRegisterName(unsigned RegNo) {
60 return SparcInstPrinter::getRegisterName(RegNo);
63 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
64 unsigned AsmVariant, const char *ExtraCode,
66 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
67 unsigned AsmVariant, const char *ExtraCode,
70 } // end of anonymous namespace
72 static MCOperand createPCXCallOP(MCSymbol *Label,
73 MCContext &OutContext)
75 const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Label,
77 const SparcMCExpr *expr = SparcMCExpr::Create(SparcMCExpr::VK_Sparc_None,
79 return MCOperand::CreateExpr(expr);
82 static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind,
83 MCSymbol *GOTLabel, MCSymbol *StartLabel,
85 MCContext &OutContext)
87 const MCSymbolRefExpr *GOT = MCSymbolRefExpr::Create(GOTLabel, OutContext);
88 const MCSymbolRefExpr *Start = MCSymbolRefExpr::Create(StartLabel,
90 const MCSymbolRefExpr *Cur = MCSymbolRefExpr::Create(CurLabel,
93 const MCBinaryExpr *Sub = MCBinaryExpr::CreateSub(Cur, Start, OutContext);
94 const MCBinaryExpr *Add = MCBinaryExpr::CreateAdd(GOT, Sub, OutContext);
95 const SparcMCExpr *expr = SparcMCExpr::Create(Kind,
97 return MCOperand::CreateExpr(expr);
100 static void EmitCall(MCStreamer &OutStreamer,
104 CallInst.setOpcode(SP::CALL);
105 CallInst.addOperand(Callee);
106 OutStreamer.EmitInstruction(CallInst);
109 static void EmitSETHI(MCStreamer &OutStreamer,
110 MCOperand &Imm, MCOperand &RD)
113 SETHIInst.setOpcode(SP::SETHIi);
114 SETHIInst.addOperand(RD);
115 SETHIInst.addOperand(Imm);
116 OutStreamer.EmitInstruction(SETHIInst);
119 static void EmitOR(MCStreamer &OutStreamer, MCOperand &RS1,
120 MCOperand &Imm, MCOperand &RD)
123 ORInst.setOpcode(SP::ORri);
124 ORInst.addOperand(RD);
125 ORInst.addOperand(RS1);
126 ORInst.addOperand(Imm);
127 OutStreamer.EmitInstruction(ORInst);
130 static void EmitADD(MCStreamer &OutStreamer,
131 MCOperand &RS1, MCOperand &RS2, MCOperand &RD)
134 ADDInst.setOpcode(SP::ADDrr);
135 ADDInst.addOperand(RD);
136 ADDInst.addOperand(RS1);
137 ADDInst.addOperand(RS2);
138 OutStreamer.EmitInstruction(ADDInst);
141 static void LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
142 MCStreamer &OutStreamer,
143 MCContext &OutContext)
145 const MachineOperand &MO = MI->getOperand(0);
146 MCSymbol *StartLabel = OutContext.CreateTempSymbol();
147 MCSymbol *EndLabel = OutContext.CreateTempSymbol();
148 MCSymbol *SethiLabel = OutContext.CreateTempSymbol();
150 OutContext.GetOrCreateSymbol(Twine("_GLOBAL_OFFSET_TABLE_"));
152 assert(MO.getReg() != SP::O7 &&
153 "%o7 is assigned as destination for getpcx!");
155 MCOperand MCRegOP = MCOperand::CreateReg(MO.getReg());
156 MCOperand RegO7 = MCOperand::CreateReg(SP::O7);
161 // sethi %hi(_GLOBAL_OFFSET_TABLE_+(<SethiLabel>-<StartLabel>)), <MO>
163 // or <MO>, %lo(_GLOBAL_OFFSET_TABLE_+(<EndLabel>-<StartLabel>))), <MO>
164 // add <MO>, %o7, <MO>
166 OutStreamer.EmitLabel(StartLabel);
167 MCOperand Callee = createPCXCallOP(EndLabel, OutContext);
168 EmitCall(OutStreamer, Callee);
169 OutStreamer.EmitLabel(SethiLabel);
170 MCOperand hiImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_HI,
171 GOTLabel, StartLabel, SethiLabel,
173 EmitSETHI(OutStreamer, hiImm, MCRegOP);
174 OutStreamer.EmitLabel(EndLabel);
175 MCOperand loImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_LO,
176 GOTLabel, StartLabel, EndLabel,
178 EmitOR(OutStreamer, MCRegOP, loImm, MCRegOP);
179 EmitADD(OutStreamer, MCRegOP, RegO7, MCRegOP);
182 void SparcAsmPrinter::EmitInstruction(const MachineInstr *MI)
185 switch (MI->getOpcode()) {
187 case TargetOpcode::DBG_VALUE:
188 // FIXME: Debug Value.
191 LowerGETPCXAndEmitMCInsts(MI, OutStreamer, OutContext);
194 MachineBasicBlock::const_instr_iterator I = MI;
195 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
198 LowerSparcMachineInstrToMCInst(I, TmpInst, *this);
199 OutStreamer.EmitInstruction(TmpInst);
200 } while ((++I != E) && I->isInsideBundle()); // Delay slot check.
203 void SparcAsmPrinter::EmitFunctionBodyStart() {
204 if (!TM.getSubtarget<SparcSubtarget>().is64Bit())
207 const MachineRegisterInfo &MRI = MF->getRegInfo();
208 const unsigned globalRegs[] = { SP::G2, SP::G3, SP::G6, SP::G7, 0 };
209 for (unsigned i = 0; globalRegs[i] != 0; ++i) {
210 unsigned reg = globalRegs[i];
211 if (MRI.use_empty(reg))
214 if (reg == SP::G6 || reg == SP::G7)
215 getTargetStreamer().emitSparcRegisterIgnore(reg);
217 getTargetStreamer().emitSparcRegisterScratch(reg);
221 void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
223 const DataLayout *DL = TM.getDataLayout();
224 const MachineOperand &MO = MI->getOperand (opNum);
225 unsigned TF = MO.getTargetFlags();
227 // Verify the target flags.
228 if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) {
229 if (MI->getOpcode() == SP::CALL)
230 assert(TF == SPII::MO_NO_FLAG &&
231 "Cannot handle target flags on call address");
232 else if (MI->getOpcode() == SP::SETHIi || MI->getOpcode() == SP::SETHIXi)
233 assert((TF == SPII::MO_HI || TF == SPII::MO_H44 || TF == SPII::MO_HH
234 || TF == SPII::MO_TLS_GD_HI22
235 || TF == SPII::MO_TLS_LDM_HI22
236 || TF == SPII::MO_TLS_LDO_HIX22
237 || TF == SPII::MO_TLS_IE_HI22
238 || TF == SPII::MO_TLS_LE_HIX22) &&
239 "Invalid target flags for address operand on sethi");
240 else if (MI->getOpcode() == SP::TLS_CALL)
241 assert((TF == SPII::MO_NO_FLAG
242 || TF == SPII::MO_TLS_GD_CALL
243 || TF == SPII::MO_TLS_LDM_CALL) &&
244 "Cannot handle target flags on tls call address");
245 else if (MI->getOpcode() == SP::TLS_ADDrr)
246 assert((TF == SPII::MO_TLS_GD_ADD || TF == SPII::MO_TLS_LDM_ADD
247 || TF == SPII::MO_TLS_LDO_ADD || TF == SPII::MO_TLS_IE_ADD) &&
248 "Cannot handle target flags on add for TLS");
249 else if (MI->getOpcode() == SP::TLS_LDrr)
250 assert(TF == SPII::MO_TLS_IE_LD &&
251 "Cannot handle target flags on ld for TLS");
252 else if (MI->getOpcode() == SP::TLS_LDXrr)
253 assert(TF == SPII::MO_TLS_IE_LDX &&
254 "Cannot handle target flags on ldx for TLS");
255 else if (MI->getOpcode() == SP::XORri || MI->getOpcode() == SP::XORXri)
256 assert((TF == SPII::MO_TLS_LDO_LOX10 || TF == SPII::MO_TLS_LE_LOX10) &&
257 "Cannot handle target flags on xor for TLS");
259 assert((TF == SPII::MO_LO || TF == SPII::MO_M44 || TF == SPII::MO_L44
261 || TF == SPII::MO_TLS_GD_LO10
262 || TF == SPII::MO_TLS_LDM_LO10
263 || TF == SPII::MO_TLS_IE_LO10 ) &&
264 "Invalid target flags for small address operand");
268 bool CloseParen = true;
271 llvm_unreachable("Unknown target flags on operand");
272 case SPII::MO_NO_FLAG:
275 case SPII::MO_LO: O << "%lo("; break;
276 case SPII::MO_HI: O << "%hi("; break;
277 case SPII::MO_H44: O << "%h44("; break;
278 case SPII::MO_M44: O << "%m44("; break;
279 case SPII::MO_L44: O << "%l44("; break;
280 case SPII::MO_HH: O << "%hh("; break;
281 case SPII::MO_HM: O << "%hm("; break;
282 case SPII::MO_TLS_GD_HI22: O << "%tgd_hi22("; break;
283 case SPII::MO_TLS_GD_LO10: O << "%tgd_lo10("; break;
284 case SPII::MO_TLS_GD_ADD: O << "%tgd_add("; break;
285 case SPII::MO_TLS_GD_CALL: O << "%tgd_call("; break;
286 case SPII::MO_TLS_LDM_HI22: O << "%tldm_hi22("; break;
287 case SPII::MO_TLS_LDM_LO10: O << "%tldm_lo10("; break;
288 case SPII::MO_TLS_LDM_ADD: O << "%tldm_add("; break;
289 case SPII::MO_TLS_LDM_CALL: O << "%tldm_call("; break;
290 case SPII::MO_TLS_LDO_HIX22: O << "%tldo_hix22("; break;
291 case SPII::MO_TLS_LDO_LOX10: O << "%tldo_lox10("; break;
292 case SPII::MO_TLS_LDO_ADD: O << "%tldo_add("; break;
293 case SPII::MO_TLS_IE_HI22: O << "%tie_hi22("; break;
294 case SPII::MO_TLS_IE_LO10: O << "%tie_lo10("; break;
295 case SPII::MO_TLS_IE_LD: O << "%tie_ld("; break;
296 case SPII::MO_TLS_IE_LDX: O << "%tie_ldx("; break;
297 case SPII::MO_TLS_IE_ADD: O << "%tie_add("; break;
298 case SPII::MO_TLS_LE_HIX22: O << "%tle_hix22("; break;
299 case SPII::MO_TLS_LE_LOX10: O << "%tle_lox10("; break;
302 switch (MO.getType()) {
303 case MachineOperand::MO_Register:
304 O << "%" << StringRef(getRegisterName(MO.getReg())).lower();
307 case MachineOperand::MO_Immediate:
308 O << (int)MO.getImm();
310 case MachineOperand::MO_MachineBasicBlock:
311 O << *MO.getMBB()->getSymbol();
313 case MachineOperand::MO_GlobalAddress:
314 O << *getSymbol(MO.getGlobal());
316 case MachineOperand::MO_BlockAddress:
317 O << GetBlockAddressSymbol(MO.getBlockAddress())->getName();
319 case MachineOperand::MO_ExternalSymbol:
320 O << MO.getSymbolName();
322 case MachineOperand::MO_ConstantPoolIndex:
323 O << DL->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
327 llvm_unreachable("<unknown operand type>");
329 if (CloseParen) O << ")";
332 void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
333 raw_ostream &O, const char *Modifier) {
334 printOperand(MI, opNum, O);
336 // If this is an ADD operand, emit it like normal operands.
337 if (Modifier && !strcmp(Modifier, "arith")) {
339 printOperand(MI, opNum+1, O);
343 if (MI->getOperand(opNum+1).isReg() &&
344 MI->getOperand(opNum+1).getReg() == SP::G0)
345 return; // don't print "+%g0"
346 if (MI->getOperand(opNum+1).isImm() &&
347 MI->getOperand(opNum+1).getImm() == 0)
348 return; // don't print "+0"
351 printOperand(MI, opNum+1, O);
354 /// PrintAsmOperand - Print out an operand for an inline asm expression.
356 bool SparcAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
358 const char *ExtraCode,
360 if (ExtraCode && ExtraCode[0]) {
361 if (ExtraCode[1] != 0) return true; // Unknown modifier.
363 switch (ExtraCode[0]) {
365 // See if this is a generic print operand
366 return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
372 printOperand(MI, OpNo, O);
377 bool SparcAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
378 unsigned OpNo, unsigned AsmVariant,
379 const char *ExtraCode,
381 if (ExtraCode && ExtraCode[0])
382 return true; // Unknown modifier
385 printMemOperand(MI, OpNo, O);
391 // Force static initialization.
392 extern "C" void LLVMInitializeSparcAsmPrinter() {
393 RegisterAsmPrinter<SparcAsmPrinter> X(TheSparcTarget);
394 RegisterAsmPrinter<SparcAsmPrinter> Y(TheSparcV9Target);