1 //===-- SparcAsmPrinter.cpp - Sparc LLVM assembly writer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format SPARC assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "SparcInstrInfo.h"
18 #include "SparcTargetMachine.h"
19 #include "llvm/CodeGen/AsmPrinter.h"
20 #include "llvm/CodeGen/MachineInstr.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/MC/MCStreamer.h"
23 #include "llvm/MC/MCSymbol.h"
24 #include "llvm/Target/Mangler.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
32 class SparcAsmPrinter : public AsmPrinter {
34 explicit SparcAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
35 : AsmPrinter(TM, Streamer) {}
37 virtual const char *getPassName() const {
38 return "Sparc Assembly Printer";
41 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
42 void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS,
43 const char *Modifier = 0);
44 void printCCOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
46 virtual void EmitInstruction(const MachineInstr *MI) {
48 raw_svector_ostream OS(Str);
49 printInstruction(MI, OS);
50 OutStreamer.EmitRawText(OS.str());
52 void printInstruction(const MachineInstr *MI, raw_ostream &OS);// autogen'd.
53 static const char *getRegisterName(unsigned RegNo);
55 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
56 unsigned AsmVariant, const char *ExtraCode,
58 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
59 unsigned AsmVariant, const char *ExtraCode,
62 bool printGetPCX(const MachineInstr *MI, unsigned OpNo, raw_ostream &OS);
64 virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB)
67 } // end of anonymous namespace
69 #include "SparcGenAsmWriter.inc"
71 void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
73 const MachineOperand &MO = MI->getOperand (opNum);
74 bool CloseParen = false;
75 if (MI->getOpcode() == SP::SETHIi && !MO.isReg() && !MO.isImm()) {
78 } else if ((MI->getOpcode() == SP::ORri || MI->getOpcode() == SP::ADDri) &&
79 !MO.isReg() && !MO.isImm()) {
83 switch (MO.getType()) {
84 case MachineOperand::MO_Register:
85 O << "%" << LowercaseString(getRegisterName(MO.getReg()));
88 case MachineOperand::MO_Immediate:
89 O << (int)MO.getImm();
91 case MachineOperand::MO_MachineBasicBlock:
92 O << *MO.getMBB()->getSymbol();
94 case MachineOperand::MO_GlobalAddress:
95 O << *Mang->getSymbol(MO.getGlobal());
97 case MachineOperand::MO_ExternalSymbol:
98 O << MO.getSymbolName();
100 case MachineOperand::MO_ConstantPoolIndex:
101 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
105 llvm_unreachable("<unknown operand type>");
107 if (CloseParen) O << ")";
110 void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
111 raw_ostream &O, const char *Modifier) {
112 printOperand(MI, opNum, O);
114 // If this is an ADD operand, emit it like normal operands.
115 if (Modifier && !strcmp(Modifier, "arith")) {
117 printOperand(MI, opNum+1, O);
121 if (MI->getOperand(opNum+1).isReg() &&
122 MI->getOperand(opNum+1).getReg() == SP::G0)
123 return; // don't print "+%g0"
124 if (MI->getOperand(opNum+1).isImm() &&
125 MI->getOperand(opNum+1).getImm() == 0)
126 return; // don't print "+0"
129 if (MI->getOperand(opNum+1).isGlobal() ||
130 MI->getOperand(opNum+1).isCPI()) {
132 printOperand(MI, opNum+1, O);
135 printOperand(MI, opNum+1, O);
139 bool SparcAsmPrinter::printGetPCX(const MachineInstr *MI, unsigned opNum,
141 std::string operand = "";
142 const MachineOperand &MO = MI->getOperand(opNum);
143 switch (MO.getType()) {
144 default: assert(0 && "Operand is not a register ");
145 case MachineOperand::MO_Register:
146 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
147 "Operand is not a physical register ");
148 assert(MO.getReg() != SP::O7 &&
149 "%o7 is assigned as destination for getpcx!");
150 operand = "%" + LowercaseString(getRegisterName(MO.getReg()));
154 unsigned mfNum = MI->getParent()->getParent()->getFunctionNumber();
155 unsigned bbNum = MI->getParent()->getNumber();
157 O << '\n' << ".LLGETPCH" << mfNum << '_' << bbNum << ":\n";
158 O << "\tcall\t.LLGETPC" << mfNum << '_' << bbNum << '\n' ;
161 << "%hi(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum
162 << ")), " << operand << '\n' ;
164 O << ".LLGETPC" << mfNum << '_' << bbNum << ":\n" ;
165 O << "\tor\t" << operand
166 << ", %lo(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum
167 << ")), " << operand << '\n';
168 O << "\tadd\t" << operand << ", %o7, " << operand << '\n';
173 void SparcAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum,
175 int CC = (int)MI->getOperand(opNum).getImm();
176 O << SPARCCondCodeToString((SPCC::CondCodes)CC);
179 /// PrintAsmOperand - Print out an operand for an inline asm expression.
181 bool SparcAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
183 const char *ExtraCode,
185 if (ExtraCode && ExtraCode[0]) {
186 if (ExtraCode[1] != 0) return true; // Unknown modifier.
188 switch (ExtraCode[0]) {
189 default: return true; // Unknown modifier.
195 printOperand(MI, OpNo, O);
200 bool SparcAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
201 unsigned OpNo, unsigned AsmVariant,
202 const char *ExtraCode,
204 if (ExtraCode && ExtraCode[0])
205 return true; // Unknown modifier
208 printMemOperand(MI, OpNo, O);
214 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
215 /// exactly one predecessor and the control transfer mechanism between
216 /// the predecessor and this block is a fall-through.
218 /// This overrides AsmPrinter's implementation to handle delay slots.
219 bool SparcAsmPrinter::
220 isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const {
221 // If this is a landing pad, it isn't a fall through. If it has no preds,
222 // then nothing falls through to it.
223 if (MBB->isLandingPad() || MBB->pred_empty())
226 // If there isn't exactly one predecessor, it can't be a fall through.
227 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
229 if (PI2 != MBB->pred_end())
232 // The predecessor has to be immediately before this block.
233 const MachineBasicBlock *Pred = *PI;
235 if (!Pred->isLayoutSuccessor(MBB))
238 // Check if the last terminator is an unconditional branch.
239 MachineBasicBlock::const_iterator I = Pred->end();
240 while (I != Pred->begin() && !(--I)->getDesc().isTerminator())
242 return I == Pred->end() || !I->getDesc().isBarrier();
247 // Force static initialization.
248 extern "C" void LLVMInitializeSparcAsmPrinter() {
249 RegisterAsmPrinter<SparcAsmPrinter> X(TheSparcTarget);
250 RegisterAsmPrinter<SparcAsmPrinter> Y(TheSparcV9Target);