1 //===-- SparcAsmPrinter.cpp - Sparc LLVM assembly writer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format SPARC assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "InstPrinter/SparcInstPrinter.h"
18 #include "MCTargetDesc/SparcBaseInfo.h"
19 #include "MCTargetDesc/SparcMCExpr.h"
20 #include "SparcInstrInfo.h"
21 #include "SparcTargetMachine.h"
22 #include "SparcTargetStreamer.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/CodeGen/AsmPrinter.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Mangler.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCContext.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/MC/MCSymbol.h"
33 #include "llvm/Support/TargetRegistry.h"
34 #include "llvm/Support/raw_ostream.h"
38 class SparcAsmPrinter : public AsmPrinter {
39 SparcTargetStreamer &getTargetStreamer() {
40 return static_cast<SparcTargetStreamer&>(OutStreamer.getTargetStreamer());
43 explicit SparcAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
44 : AsmPrinter(TM, Streamer) {}
46 virtual const char *getPassName() const {
47 return "Sparc Assembly Printer";
50 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
51 void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS,
52 const char *Modifier = 0);
53 void printCCOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
55 virtual void EmitFunctionBodyStart();
56 virtual void EmitInstruction(const MachineInstr *MI);
58 static const char *getRegisterName(unsigned RegNo) {
59 return SparcInstPrinter::getRegisterName(RegNo);
62 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
63 unsigned AsmVariant, const char *ExtraCode,
65 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
66 unsigned AsmVariant, const char *ExtraCode,
69 virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB)
73 } // end of anonymous namespace
75 static MCOperand createPCXCallOP(MCSymbol *Label,
76 MCContext &OutContext)
78 const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Label,
80 const SparcMCExpr *expr = SparcMCExpr::Create(SparcMCExpr::VK_Sparc_None,
82 return MCOperand::CreateExpr(expr);
85 static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind,
86 MCSymbol *GOTLabel, MCSymbol *StartLabel,
88 MCContext &OutContext)
90 const MCSymbolRefExpr *GOT = MCSymbolRefExpr::Create(GOTLabel, OutContext);
91 const MCSymbolRefExpr *Start = MCSymbolRefExpr::Create(StartLabel,
93 const MCSymbolRefExpr *Cur = MCSymbolRefExpr::Create(CurLabel,
96 const MCBinaryExpr *Sub = MCBinaryExpr::CreateSub(Cur, Start, OutContext);
97 const MCBinaryExpr *Add = MCBinaryExpr::CreateAdd(GOT, Sub, OutContext);
98 const SparcMCExpr *expr = SparcMCExpr::Create(Kind,
100 return MCOperand::CreateExpr(expr);
103 static void EmitCall(MCStreamer &OutStreamer,
107 CallInst.setOpcode(SP::CALL);
108 CallInst.addOperand(Callee);
109 OutStreamer.EmitInstruction(CallInst);
112 static void EmitSETHI(MCStreamer &OutStreamer,
113 MCOperand &Imm, MCOperand &RD)
116 SETHIInst.setOpcode(SP::SETHIi);
117 SETHIInst.addOperand(RD);
118 SETHIInst.addOperand(Imm);
119 OutStreamer.EmitInstruction(SETHIInst);
122 static void EmitOR(MCStreamer &OutStreamer, MCOperand &RS1,
123 MCOperand &Imm, MCOperand &RD)
126 ORInst.setOpcode(SP::ORri);
127 ORInst.addOperand(RD);
128 ORInst.addOperand(RS1);
129 ORInst.addOperand(Imm);
130 OutStreamer.EmitInstruction(ORInst);
133 static void EmitADD(MCStreamer &OutStreamer,
134 MCOperand &RS1, MCOperand &RS2, MCOperand &RD)
137 ADDInst.setOpcode(SP::ADDrr);
138 ADDInst.addOperand(RD);
139 ADDInst.addOperand(RS1);
140 ADDInst.addOperand(RS2);
141 OutStreamer.EmitInstruction(ADDInst);
144 static void LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
145 MCStreamer &OutStreamer,
146 MCContext &OutContext)
148 const MachineOperand &MO = MI->getOperand(0);
149 MCSymbol *StartLabel = OutContext.CreateTempSymbol();
150 MCSymbol *EndLabel = OutContext.CreateTempSymbol();
151 MCSymbol *SethiLabel = OutContext.CreateTempSymbol();
153 OutContext.GetOrCreateSymbol(Twine("_GLOBAL_OFFSET_TABLE_"));
155 assert(MO.getReg() != SP::O7 &&
156 "%o7 is assigned as destination for getpcx!");
158 MCOperand MCRegOP = MCOperand::CreateReg(MO.getReg());
159 MCOperand RegO7 = MCOperand::CreateReg(SP::O7);
164 // sethi %hi(_GLOBAL_OFFSET_TABLE_+(<SethiLabel>-<StartLabel>)), <MO>
166 // or <MO>, %lo(_GLOBAL_OFFSET_TABLE_+(<EndLabel>-<StartLabel>))), <MO>
167 // add <MO>, %o7, <MO>
169 OutStreamer.EmitLabel(StartLabel);
170 MCOperand Callee = createPCXCallOP(EndLabel, OutContext);
171 EmitCall(OutStreamer, Callee);
172 OutStreamer.EmitLabel(SethiLabel);
173 MCOperand hiImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_HI,
174 GOTLabel, StartLabel, SethiLabel,
176 EmitSETHI(OutStreamer, hiImm, MCRegOP);
177 OutStreamer.EmitLabel(EndLabel);
178 MCOperand loImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_LO,
179 GOTLabel, StartLabel, EndLabel,
181 EmitOR(OutStreamer, MCRegOP, loImm, MCRegOP);
182 EmitADD(OutStreamer, MCRegOP, RegO7, MCRegOP);
185 void SparcAsmPrinter::EmitInstruction(const MachineInstr *MI)
188 switch (MI->getOpcode()) {
190 case TargetOpcode::DBG_VALUE:
191 // FIXME: Debug Value.
194 LowerGETPCXAndEmitMCInsts(MI, OutStreamer, OutContext);
197 MachineBasicBlock::const_instr_iterator I = MI;
198 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
201 LowerSparcMachineInstrToMCInst(I, TmpInst, *this);
202 OutStreamer.EmitInstruction(TmpInst);
203 } while ((++I != E) && I->isInsideBundle()); // Delay slot check.
206 void SparcAsmPrinter::EmitFunctionBodyStart() {
207 if (!TM.getSubtarget<SparcSubtarget>().is64Bit())
210 const MachineRegisterInfo &MRI = MF->getRegInfo();
211 const unsigned globalRegs[] = { SP::G2, SP::G3, SP::G6, SP::G7, 0 };
212 for (unsigned i = 0; globalRegs[i] != 0; ++i) {
213 unsigned reg = globalRegs[i];
214 if (MRI.use_empty(reg))
217 if (reg == SP::G6 || reg == SP::G7)
218 getTargetStreamer().emitSparcRegisterIgnore(reg);
220 getTargetStreamer().emitSparcRegisterScratch(reg);
224 void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
226 const DataLayout *DL = TM.getDataLayout();
227 const MachineOperand &MO = MI->getOperand (opNum);
228 unsigned TF = MO.getTargetFlags();
230 // Verify the target flags.
231 if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) {
232 if (MI->getOpcode() == SP::CALL)
233 assert(TF == SPII::MO_NO_FLAG &&
234 "Cannot handle target flags on call address");
235 else if (MI->getOpcode() == SP::SETHIi || MI->getOpcode() == SP::SETHIXi)
236 assert((TF == SPII::MO_HI || TF == SPII::MO_H44 || TF == SPII::MO_HH
237 || TF == SPII::MO_TLS_GD_HI22
238 || TF == SPII::MO_TLS_LDM_HI22
239 || TF == SPII::MO_TLS_LDO_HIX22
240 || TF == SPII::MO_TLS_IE_HI22
241 || TF == SPII::MO_TLS_LE_HIX22) &&
242 "Invalid target flags for address operand on sethi");
243 else if (MI->getOpcode() == SP::TLS_CALL)
244 assert((TF == SPII::MO_NO_FLAG
245 || TF == SPII::MO_TLS_GD_CALL
246 || TF == SPII::MO_TLS_LDM_CALL) &&
247 "Cannot handle target flags on tls call address");
248 else if (MI->getOpcode() == SP::TLS_ADDrr)
249 assert((TF == SPII::MO_TLS_GD_ADD || TF == SPII::MO_TLS_LDM_ADD
250 || TF == SPII::MO_TLS_LDO_ADD || TF == SPII::MO_TLS_IE_ADD) &&
251 "Cannot handle target flags on add for TLS");
252 else if (MI->getOpcode() == SP::TLS_LDrr)
253 assert(TF == SPII::MO_TLS_IE_LD &&
254 "Cannot handle target flags on ld for TLS");
255 else if (MI->getOpcode() == SP::TLS_LDXrr)
256 assert(TF == SPII::MO_TLS_IE_LDX &&
257 "Cannot handle target flags on ldx for TLS");
258 else if (MI->getOpcode() == SP::XORri || MI->getOpcode() == SP::XORXri)
259 assert((TF == SPII::MO_TLS_LDO_LOX10 || TF == SPII::MO_TLS_LE_LOX10) &&
260 "Cannot handle target flags on xor for TLS");
262 assert((TF == SPII::MO_LO || TF == SPII::MO_M44 || TF == SPII::MO_L44
264 || TF == SPII::MO_TLS_GD_LO10
265 || TF == SPII::MO_TLS_LDM_LO10
266 || TF == SPII::MO_TLS_IE_LO10 ) &&
267 "Invalid target flags for small address operand");
271 bool CloseParen = true;
274 llvm_unreachable("Unknown target flags on operand");
275 case SPII::MO_NO_FLAG:
278 case SPII::MO_LO: O << "%lo("; break;
279 case SPII::MO_HI: O << "%hi("; break;
280 case SPII::MO_H44: O << "%h44("; break;
281 case SPII::MO_M44: O << "%m44("; break;
282 case SPII::MO_L44: O << "%l44("; break;
283 case SPII::MO_HH: O << "%hh("; break;
284 case SPII::MO_HM: O << "%hm("; break;
285 case SPII::MO_TLS_GD_HI22: O << "%tgd_hi22("; break;
286 case SPII::MO_TLS_GD_LO10: O << "%tgd_lo10("; break;
287 case SPII::MO_TLS_GD_ADD: O << "%tgd_add("; break;
288 case SPII::MO_TLS_GD_CALL: O << "%tgd_call("; break;
289 case SPII::MO_TLS_LDM_HI22: O << "%tldm_hi22("; break;
290 case SPII::MO_TLS_LDM_LO10: O << "%tldm_lo10("; break;
291 case SPII::MO_TLS_LDM_ADD: O << "%tldm_add("; break;
292 case SPII::MO_TLS_LDM_CALL: O << "%tldm_call("; break;
293 case SPII::MO_TLS_LDO_HIX22: O << "%tldo_hix22("; break;
294 case SPII::MO_TLS_LDO_LOX10: O << "%tldo_lox10("; break;
295 case SPII::MO_TLS_LDO_ADD: O << "%tldo_add("; break;
296 case SPII::MO_TLS_IE_HI22: O << "%tie_hi22("; break;
297 case SPII::MO_TLS_IE_LO10: O << "%tie_lo10("; break;
298 case SPII::MO_TLS_IE_LD: O << "%tie_ld("; break;
299 case SPII::MO_TLS_IE_LDX: O << "%tie_ldx("; break;
300 case SPII::MO_TLS_IE_ADD: O << "%tie_add("; break;
301 case SPII::MO_TLS_LE_HIX22: O << "%tle_hix22("; break;
302 case SPII::MO_TLS_LE_LOX10: O << "%tle_lox10("; break;
305 switch (MO.getType()) {
306 case MachineOperand::MO_Register:
307 O << "%" << StringRef(getRegisterName(MO.getReg())).lower();
310 case MachineOperand::MO_Immediate:
311 O << (int)MO.getImm();
313 case MachineOperand::MO_MachineBasicBlock:
314 O << *MO.getMBB()->getSymbol();
316 case MachineOperand::MO_GlobalAddress:
317 O << *getSymbol(MO.getGlobal());
319 case MachineOperand::MO_BlockAddress:
320 O << GetBlockAddressSymbol(MO.getBlockAddress())->getName();
322 case MachineOperand::MO_ExternalSymbol:
323 O << MO.getSymbolName();
325 case MachineOperand::MO_ConstantPoolIndex:
326 O << DL->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
330 llvm_unreachable("<unknown operand type>");
332 if (CloseParen) O << ")";
335 void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
336 raw_ostream &O, const char *Modifier) {
337 printOperand(MI, opNum, O);
339 // If this is an ADD operand, emit it like normal operands.
340 if (Modifier && !strcmp(Modifier, "arith")) {
342 printOperand(MI, opNum+1, O);
346 if (MI->getOperand(opNum+1).isReg() &&
347 MI->getOperand(opNum+1).getReg() == SP::G0)
348 return; // don't print "+%g0"
349 if (MI->getOperand(opNum+1).isImm() &&
350 MI->getOperand(opNum+1).getImm() == 0)
351 return; // don't print "+0"
354 printOperand(MI, opNum+1, O);
357 /// PrintAsmOperand - Print out an operand for an inline asm expression.
359 bool SparcAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
361 const char *ExtraCode,
363 if (ExtraCode && ExtraCode[0]) {
364 if (ExtraCode[1] != 0) return true; // Unknown modifier.
366 switch (ExtraCode[0]) {
368 // See if this is a generic print operand
369 return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
375 printOperand(MI, OpNo, O);
380 bool SparcAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
381 unsigned OpNo, unsigned AsmVariant,
382 const char *ExtraCode,
384 if (ExtraCode && ExtraCode[0])
385 return true; // Unknown modifier
388 printMemOperand(MI, OpNo, O);
394 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
395 /// exactly one predecessor and the control transfer mechanism between
396 /// the predecessor and this block is a fall-through.
398 /// This overrides AsmPrinter's implementation to handle delay slots.
399 bool SparcAsmPrinter::
400 isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const {
401 // If this is a landing pad, it isn't a fall through. If it has no preds,
402 // then nothing falls through to it.
403 if (MBB->isLandingPad() || MBB->pred_empty())
406 // If there isn't exactly one predecessor, it can't be a fall through.
407 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
409 if (PI2 != MBB->pred_end())
412 // The predecessor has to be immediately before this block.
413 const MachineBasicBlock *Pred = *PI;
415 if (!Pred->isLayoutSuccessor(MBB))
418 // Check if the last terminator is an unconditional branch.
419 MachineBasicBlock::const_iterator I = Pred->end();
420 while (I != Pred->begin() && !(--I)->isTerminator())
422 return I == Pred->end() || !I->isBarrier();
425 // Force static initialization.
426 extern "C" void LLVMInitializeSparcAsmPrinter() {
427 RegisterAsmPrinter<SparcAsmPrinter> X(TheSparcTarget);
428 RegisterAsmPrinter<SparcAsmPrinter> Y(TheSparcV9Target);